GB2150749B - Integrated circuits - Google Patents

Integrated circuits

Info

Publication number
GB2150749B
GB2150749B GB08332336A GB8332336A GB2150749B GB 2150749 B GB2150749 B GB 2150749B GB 08332336 A GB08332336 A GB 08332336A GB 8332336 A GB8332336 A GB 8332336A GB 2150749 B GB2150749 B GB 2150749B
Authority
GB
United Kingdom
Prior art keywords
wafer
faces
integrated circuit
circuit device
device components
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
GB08332336A
Other versions
GB8332336D0 (en
GB2150749A (en
Inventor
Thomas Meirion Jackson
Rudolf August Herbert Heinecke
Geoffrey Laurence Ashcroft
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
STC PLC
Original Assignee
Standard Telephone and Cables PLC
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Standard Telephone and Cables PLC filed Critical Standard Telephone and Cables PLC
Priority to GB08332336A priority Critical patent/GB2150749B/en
Publication of GB8332336D0 publication Critical patent/GB8332336D0/en
Publication of GB2150749A publication Critical patent/GB2150749A/en
Application granted granted Critical
Publication of GB2150749B publication Critical patent/GB2150749B/en
Expired legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/52Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/538Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
    • H01L23/5384Conductive vias through the substrate with or without pins, e.g. buried coaxial conductors
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76898Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics formed through a semiconductor substrate
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    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/02Containers; Seals
    • H01L23/04Containers; Seals characterised by the shape of the container or parts, e.g. caps, walls
    • H01L23/053Containers; Seals characterised by the shape of the container or parts, e.g. caps, walls the container being a hollow construction and having an insulating or insulated base as a mounting for the semiconductor body
    • H01L23/055Containers; Seals characterised by the shape of the container or parts, e.g. caps, walls the container being a hollow construction and having an insulating or insulated base as a mounting for the semiconductor body the leads having a passage through the base
    • HELECTRICITY
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    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/48Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/481Internal lead connections, e.g. via connections, feedthrough structures
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    • H01L24/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/42Wire connectors; Manufacturing methods related thereto
    • H01L24/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L24/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
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    • H01L2224/02Bonding areas; Manufacturing methods related thereto
    • H01L2224/04Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/0401Bonding areas specifically adapted for bump connectors, e.g. under bump metallisation [UBM]
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    • H01L2224/481Disposition
    • H01L2224/48151Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
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    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/484Connecting portions
    • H01L2224/4847Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a wedge bond
    • H01L2224/48472Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a wedge bond the other connecting portion not on the bonding area also being a wedge bond, i.e. wedge-to-wedge
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    • H01L2924/0001Technical content checked by a classifier
    • H01L2924/00014Technical content checked by a classifier the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
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    • H01L2924/01006Carbon [C]
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    • H01L2924/102Material of the semiconductor or solid state bodies
    • H01L2924/1025Semiconducting materials
    • H01L2924/10251Elemental semiconductors, i.e. Group IV
    • H01L2924/10253Silicon [Si]
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    • H01L2924/10Details of semiconductor or other solid state devices to be connected
    • H01L2924/11Device type
    • H01L2924/12Passive devices, e.g. 2 terminal devices
    • H01L2924/1204Optical Diode
    • H01L2924/12042LASER
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    • H01L2924/10Details of semiconductor or other solid state devices to be connected
    • H01L2924/11Device type
    • H01L2924/14Integrated circuits
    • HELECTRICITY
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    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/161Cap
    • H01L2924/1615Shape
    • H01L2924/16152Cap comprising a cavity for hosting the device, e.g. U-shaped cap

Abstract

Discrete electrical through connections in a semiconductor wafer (1), which may include integrated circuit device components or which carries a separate element containing the integrated circuit device components, are comprised by apertures extending through the wafer and hermetically blocked by respective metallic members (9, 11). The metallic members (9, 11) are electrically isolated from the wafer (1), by e.g. electrically insulating material (2, 8) disposed therebetween or junction isolation, and extend towards both faces of the wafer where they may provide contact pads or conductive tracks. Anisotropic etching techniques from one or both faces of the wafer may be employed. Using the technique very high pin count (interconnection) densities may be achieved; this being particularly useful for VLSI devices. <IMAGE>
GB08332336A 1983-12-03 1983-12-03 Integrated circuits Expired GB2150749B (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
GB08332336A GB2150749B (en) 1983-12-03 1983-12-03 Integrated circuits

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
GB08332336A GB2150749B (en) 1983-12-03 1983-12-03 Integrated circuits

Publications (3)

Publication Number Publication Date
GB8332336D0 GB8332336D0 (en) 1984-01-11
GB2150749A GB2150749A (en) 1985-07-03
GB2150749B true GB2150749B (en) 1987-09-23

Family

ID=10552796

Family Applications (1)

Application Number Title Priority Date Filing Date
GB08332336A Expired GB2150749B (en) 1983-12-03 1983-12-03 Integrated circuits

Country Status (1)

Country Link
GB (1) GB2150749B (en)

Families Citing this family (21)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4954875A (en) * 1986-07-17 1990-09-04 Laser Dynamics, Inc. Semiconductor wafer array with electrically conductive compliant material
GB2206729B (en) * 1987-07-01 1990-10-24 British Aerospace A method of forming electrical contacts in a multi-level interconnect system
US5051811A (en) * 1987-08-31 1991-09-24 Texas Instruments Incorporated Solder or brazing barrier
JPH0215652A (en) * 1988-07-01 1990-01-19 Mitsubishi Electric Corp Semiconductor device and manufacture thereof
US5322816A (en) * 1993-01-19 1994-06-21 Hughes Aircraft Company Method for forming deep conductive feedthroughs
WO1996013062A1 (en) * 1994-10-19 1996-05-02 Ceram Incorporated Apparatus and method of manufacturing stacked wafer array
US5841197A (en) * 1994-11-18 1998-11-24 Adamic, Jr.; Fred W. Inverted dielectric isolation process
US6124179A (en) * 1996-09-05 2000-09-26 Adamic, Jr.; Fred W. Inverted dielectric isolation process
EP2270845A3 (en) * 1996-10-29 2013-04-03 Invensas Corporation Integrated circuits and methods for their fabrication
EP1503406A3 (en) * 1996-10-29 2009-07-08 Tru-Si Technologies, Inc. Back-side contact pads of a semiconductor chip
SE511377C2 (en) * 1996-12-19 1999-09-20 Ericsson Telefon Ab L M via structure
JP2894325B2 (en) * 1997-06-25 1999-05-24 日本電気株式会社 Electronic circuit shield structure
US6300670B1 (en) 1999-07-26 2001-10-09 Stmicroelectronics, Inc. Backside bus vias
US6326689B1 (en) 1999-07-26 2001-12-04 Stmicroelectronics, Inc. Backside contact for touchchip
DE10229711B4 (en) * 2002-07-02 2009-09-03 Curamik Electronics Gmbh Semiconductor module with microcooler
US7531445B2 (en) * 2006-09-26 2009-05-12 Hymite A/S Formation of through-wafer electrical interconnections and other structures using a thin dielectric membrane
US9018094B2 (en) 2011-03-07 2015-04-28 Invensas Corporation Substrates with through vias with conductive features for connection to integrated circuit elements, and methods for forming through vias in substrates
JP2016100553A (en) * 2014-11-26 2016-05-30 ローム株式会社 Electronic apparatus
JP2016100555A (en) * 2014-11-26 2016-05-30 ローム株式会社 Electronic apparatus
KR102518803B1 (en) 2018-10-24 2023-04-07 삼성전자주식회사 Semiconductor package
JP6730495B2 (en) * 2019-07-16 2020-07-29 ローム株式会社 Electronic device

Family Cites Families (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
GB603137A (en) * 1945-12-21 1948-06-09 Standard Telephones Cables Ltd Improvements in or relating to dry contact type electrically asymmetric devices
DE1514818A1 (en) * 1951-01-28 1969-05-08 Telefunken Patent Solid-state circuit, consisting of a semiconductor body with inserted active components and an insulating layer with applied passive components and conductor tracks
GB1112992A (en) * 1964-08-18 1968-05-08 Texas Instruments Inc Three-dimensional integrated circuits and methods of making same
USB428447I5 (en) * 1965-01-27
US3648131A (en) * 1969-11-07 1972-03-07 Ibm Hourglass-shaped conductive connection through semiconductor structures
DE2022895B2 (en) * 1970-05-11 1976-12-02 Siemens AG, 1000 Berlin und 8000 München STACKED ARRANGEMENT OF SEMICONDUCTOR BODIES AND PROCESS FOR THEIR PRODUCTION

Also Published As

Publication number Publication date
GB8332336D0 (en) 1984-01-11
GB2150749A (en) 1985-07-03

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Legal Events

Date Code Title Description
732 Registration of transactions, instruments or events in the register (sect. 32/1977)
732E Amendments to the register in respect of changes of name or changes affecting rights (sect. 32/1977)
PCNP Patent ceased through non-payment of renewal fee

Effective date: 19931203