GB2150749B - Integrated circuits - Google Patents
Integrated circuitsInfo
- Publication number
- GB2150749B GB2150749B GB08332336A GB8332336A GB2150749B GB 2150749 B GB2150749 B GB 2150749B GB 08332336 A GB08332336 A GB 08332336A GB 8332336 A GB8332336 A GB 8332336A GB 2150749 B GB2150749 B GB 2150749B
- Authority
- GB
- United Kingdom
- Prior art keywords
- wafer
- faces
- integrated circuit
- circuit device
- device components
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/538—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
- H01L23/5384—Conductive vias through the substrate with or without pins, e.g. buried coaxial conductors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76898—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics formed through a semiconductor substrate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/02—Containers; Seals
- H01L23/04—Containers; Seals characterised by the shape of the container or parts, e.g. caps, walls
- H01L23/053—Containers; Seals characterised by the shape of the container or parts, e.g. caps, walls the container being a hollow construction and having an insulating or insulated base as a mounting for the semiconductor body
- H01L23/055—Containers; Seals characterised by the shape of the container or parts, e.g. caps, walls the container being a hollow construction and having an insulating or insulated base as a mounting for the semiconductor body the leads having a passage through the base
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/481—Internal lead connections, e.g. via connections, feedthrough structures
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/42—Wire connectors; Manufacturing methods related thereto
- H01L24/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L24/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/0401—Bonding areas specifically adapted for bump connectors, e.g. under bump metallisation [UBM]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/484—Connecting portions
- H01L2224/4847—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a wedge bond
- H01L2224/48472—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a wedge bond the other connecting portion not on the bonding area also being a wedge bond, i.e. wedge-to-wedge
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/0001—Technical content checked by a classifier
- H01L2924/00014—Technical content checked by a classifier the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01006—Carbon [C]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01013—Aluminum [Al]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01014—Silicon [Si]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01015—Phosphorus [P]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01019—Potassium [K]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01027—Cobalt [Co]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01028—Nickel [Ni]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01029—Copper [Cu]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01061—Promethium [Pm]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01079—Gold [Au]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01082—Lead [Pb]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/013—Alloys
- H01L2924/014—Solder alloys
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/1015—Shape
- H01L2924/10155—Shape being other than a cuboid
- H01L2924/10157—Shape being other than a cuboid at the active surface
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/102—Material of the semiconductor or solid state bodies
- H01L2924/1025—Semiconducting materials
- H01L2924/10251—Elemental semiconductors, i.e. Group IV
- H01L2924/10253—Silicon [Si]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/11—Device type
- H01L2924/12—Passive devices, e.g. 2 terminal devices
- H01L2924/1204—Optical Diode
- H01L2924/12042—LASER
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/11—Device type
- H01L2924/14—Integrated circuits
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/161—Cap
- H01L2924/1615—Shape
- H01L2924/16152—Cap comprising a cavity for hosting the device, e.g. U-shaped cap
Abstract
Discrete electrical through connections in a semiconductor wafer (1), which may include integrated circuit device components or which carries a separate element containing the integrated circuit device components, are comprised by apertures extending through the wafer and hermetically blocked by respective metallic members (9, 11). The metallic members (9, 11) are electrically isolated from the wafer (1), by e.g. electrically insulating material (2, 8) disposed therebetween or junction isolation, and extend towards both faces of the wafer where they may provide contact pads or conductive tracks. Anisotropic etching techniques from one or both faces of the wafer may be employed. Using the technique very high pin count (interconnection) densities may be achieved; this being particularly useful for VLSI devices. <IMAGE>
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
GB08332336A GB2150749B (en) | 1983-12-03 | 1983-12-03 | Integrated circuits |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
GB08332336A GB2150749B (en) | 1983-12-03 | 1983-12-03 | Integrated circuits |
Publications (3)
Publication Number | Publication Date |
---|---|
GB8332336D0 GB8332336D0 (en) | 1984-01-11 |
GB2150749A GB2150749A (en) | 1985-07-03 |
GB2150749B true GB2150749B (en) | 1987-09-23 |
Family
ID=10552796
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
GB08332336A Expired GB2150749B (en) | 1983-12-03 | 1983-12-03 | Integrated circuits |
Country Status (1)
Country | Link |
---|---|
GB (1) | GB2150749B (en) |
Families Citing this family (21)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US4954875A (en) * | 1986-07-17 | 1990-09-04 | Laser Dynamics, Inc. | Semiconductor wafer array with electrically conductive compliant material |
GB2206729B (en) * | 1987-07-01 | 1990-10-24 | British Aerospace | A method of forming electrical contacts in a multi-level interconnect system |
US5051811A (en) * | 1987-08-31 | 1991-09-24 | Texas Instruments Incorporated | Solder or brazing barrier |
JPH0215652A (en) * | 1988-07-01 | 1990-01-19 | Mitsubishi Electric Corp | Semiconductor device and manufacture thereof |
US5322816A (en) * | 1993-01-19 | 1994-06-21 | Hughes Aircraft Company | Method for forming deep conductive feedthroughs |
WO1996013062A1 (en) * | 1994-10-19 | 1996-05-02 | Ceram Incorporated | Apparatus and method of manufacturing stacked wafer array |
US5841197A (en) * | 1994-11-18 | 1998-11-24 | Adamic, Jr.; Fred W. | Inverted dielectric isolation process |
US6124179A (en) * | 1996-09-05 | 2000-09-26 | Adamic, Jr.; Fred W. | Inverted dielectric isolation process |
EP2270845A3 (en) * | 1996-10-29 | 2013-04-03 | Invensas Corporation | Integrated circuits and methods for their fabrication |
EP1503406A3 (en) * | 1996-10-29 | 2009-07-08 | Tru-Si Technologies, Inc. | Back-side contact pads of a semiconductor chip |
SE511377C2 (en) * | 1996-12-19 | 1999-09-20 | Ericsson Telefon Ab L M | via structure |
JP2894325B2 (en) * | 1997-06-25 | 1999-05-24 | 日本電気株式会社 | Electronic circuit shield structure |
US6300670B1 (en) | 1999-07-26 | 2001-10-09 | Stmicroelectronics, Inc. | Backside bus vias |
US6326689B1 (en) | 1999-07-26 | 2001-12-04 | Stmicroelectronics, Inc. | Backside contact for touchchip |
DE10229711B4 (en) * | 2002-07-02 | 2009-09-03 | Curamik Electronics Gmbh | Semiconductor module with microcooler |
US7531445B2 (en) * | 2006-09-26 | 2009-05-12 | Hymite A/S | Formation of through-wafer electrical interconnections and other structures using a thin dielectric membrane |
US9018094B2 (en) | 2011-03-07 | 2015-04-28 | Invensas Corporation | Substrates with through vias with conductive features for connection to integrated circuit elements, and methods for forming through vias in substrates |
JP2016100553A (en) * | 2014-11-26 | 2016-05-30 | ローム株式会社 | Electronic apparatus |
JP2016100555A (en) * | 2014-11-26 | 2016-05-30 | ローム株式会社 | Electronic apparatus |
KR102518803B1 (en) | 2018-10-24 | 2023-04-07 | 삼성전자주식회사 | Semiconductor package |
JP6730495B2 (en) * | 2019-07-16 | 2020-07-29 | ローム株式会社 | Electronic device |
Family Cites Families (6)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
GB603137A (en) * | 1945-12-21 | 1948-06-09 | Standard Telephones Cables Ltd | Improvements in or relating to dry contact type electrically asymmetric devices |
DE1514818A1 (en) * | 1951-01-28 | 1969-05-08 | Telefunken Patent | Solid-state circuit, consisting of a semiconductor body with inserted active components and an insulating layer with applied passive components and conductor tracks |
GB1112992A (en) * | 1964-08-18 | 1968-05-08 | Texas Instruments Inc | Three-dimensional integrated circuits and methods of making same |
USB428447I5 (en) * | 1965-01-27 | |||
US3648131A (en) * | 1969-11-07 | 1972-03-07 | Ibm | Hourglass-shaped conductive connection through semiconductor structures |
DE2022895B2 (en) * | 1970-05-11 | 1976-12-02 | Siemens AG, 1000 Berlin und 8000 München | STACKED ARRANGEMENT OF SEMICONDUCTOR BODIES AND PROCESS FOR THEIR PRODUCTION |
-
1983
- 1983-12-03 GB GB08332336A patent/GB2150749B/en not_active Expired
Also Published As
Publication number | Publication date |
---|---|
GB8332336D0 (en) | 1984-01-11 |
GB2150749A (en) | 1985-07-03 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
GB2150749B (en) | Integrated circuits | |
US5315481A (en) | Packaging construction for semiconductor wafers | |
CA1201820A (en) | Semiconductor integrated circuit including a lead frame chip support | |
KR910008984B1 (en) | Low resistance electrical inter connection for synchrous rectifiers | |
US4225900A (en) | Integrated circuit device package interconnect means | |
US5952840A (en) | Apparatus for testing semiconductor wafers | |
EP0110285A3 (en) | Interconnection of integrated circuits | |
AU8731291A (en) | Semiconductor chip assemblies, methods of making same and components for same | |
MY113889A (en) | Dual substrate package assembly for being electrically coupled to a conducting member | |
ATE339774T1 (en) | INSULATING MATERIAL FOR POROUS SILICON OXICARBIDE INTEGRATED CIRCUIT | |
JPS5738577A (en) | Connector | |
GB2332562B (en) | Hybrid semiconductor imaging device | |
US5753971A (en) | Power semiconductor module with terminal pins | |
EP0245179A3 (en) | System for detachably mounting semiconductors on conductor substrate. | |
MY129912A (en) | Testing circuits on substrates | |
WO2000035262A3 (en) | Method for mounting an electronic component | |
AU2002326597A1 (en) | Semiconductor device with compliant electrical terminals, apparatus including the semiconductor device, and methods for forming same | |
EP0285277A1 (en) | Chip carrier with energy storage means | |
TR22767A (en) | COMPRESSOR BASIS FOR MICROMINATORY CONNECTIONS | |
DE3361968D1 (en) | Method of positioning interconnecting lines at an electrical contact hole of an integrated circuit | |
MY130993A (en) | Testing circuits on substrates | |
KR100259060B1 (en) | Semiconductor chip test socket and method for contactor fabrication | |
JPS57180155A (en) | Vessel for electronic circuit | |
TW224542B (en) | Method for interconnecting a first conductor array of an electronic device to a second connector array of a first substrate | |
REEDY et al. | Semiconductor-on-Insulator Device Interconnects(Patent) |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
732 | Registration of transactions, instruments or events in the register (sect. 32/1977) | ||
732E | Amendments to the register in respect of changes of name or changes affecting rights (sect. 32/1977) | ||
PCNP | Patent ceased through non-payment of renewal fee |
Effective date: 19931203 |