CN101350308A - 金氧半导体场效应电晶体及源/漏极区中降低损坏的方法 - Google Patents
金氧半导体场效应电晶体及源/漏极区中降低损坏的方法 Download PDFInfo
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Abstract
一种在金氧半导体场效应电晶体(MOSFET)的源/漏极区中降低损坏形成的方法,该方法包含:提供一基板,该基板具有至少一栅极结构,该栅极结构包含:一栅极氧化层;一栅极电极层;及一源/漏极区,具有不纯物离子掺杂;植入一离子种类以产生非晶硅层;沉积一金属层在该源/漏极区中并进行反应;以及快闪退火处理该基板。本发明还公开了一种金氧半导体场效应电晶体和一种半导体元件的制造方法。本发明借由利用非晶硅化布植工艺、硅化镍工艺和快闪退火处理的系统和方法来减轻源/漏极区缺陷。
Description
技术领域
本发明涉及一种半导体元件的制造系统和方法,特别是涉及一种利用非晶硅化布植工艺、硅化镍工艺和快闪退火处理在减轻半导体元件源/漏极区内缺陷的系统及方法。
背景技术
互补式金氧半导体(CMOS)场效应电晶体(FET)技术是一种形成方法并利用n通道场效应(NMOS)与p通道场效应(PMOS)的组合,形成低电流、高功率的积体电路。
在次微米半导体技术中,运用自行对准硅化金属工艺(self-alignmentsilicide processes)以极小化元件的串接阻抗已被广泛地接受。硅化金属工艺的定义是将金属沉积在硅上,借以克服在MOSFET内的金属和多晶硅栅极和源/漏极区之间的高阻抗。在自行对准硅化金属工艺中,先沉积多晶硅,然后是金属沉积,再进行蚀刻。之后借由热处理工艺形成硅化金属。硅化金属工艺的缺点在于会使源/漏极区内与应力相关的缺陷恶化。
非晶硅化布植(pre-amorphous implant;PAI)是使硅化金属在受非晶硅化布植造成的非晶硅层内形成。虽然已知非晶硅化布植工艺可用来减缓应力迟滞反应(stress-retarded reaction)和增加晶核形成的密度,但非晶硅化布植工艺仍有一些缺点。此缺点之一是非晶硅化布植工艺会降低源极与漏极区的导电性。传统的退火处理(anneal process)无法消除这项缺点。尚有一缺点是在PMOS栅极二极管的受损的阻抗会造成PMOS的性能下降。
发明内容
本发明的主要目的在于,克服现有的非晶硅化布植工艺存在的缺陷,而提供一种新的金氧半导体场效应电晶体及源/漏极区中降低损坏的方法,所要解决的技术问题是使其借由利用非晶硅化布植工艺、硅化镍工艺和快闪退火处理的系统和方法来减轻源/漏极区缺陷,从而更加适于实用。
本发明的目的及解决其技术问题是采用以下技术方案来实现的。依据本发明提出的一种在金氧半导体场效应电晶体的源/漏极区中降低损坏形成的方法,该方法包含:提供一基板,该基板具有至少一栅极结构,该栅极结构包含:一栅极氧化层;一栅极电极层;及一源/漏极区,具有不纯物离子掺杂;植入一离子种类以产生非晶硅层;沉积一金属层在该源/漏极区中并进行反应;以及快闪退火处理该基板。
本发明的目的及解决其技术问题还可采用以下技术措施进一步实现。
前述的方法,其中产生该非晶硅层的离子种类是氙(Xenon)。
前述的方法,其中该氙经由两步骤工艺植入。
前述的方法,其中植入该氙的该第一步骤使用5-30千电子伏特(KeV),植入该氙的该第二步骤使用7-30千电子伏特(KeV)。
前述的方法,其中植入该氙的一倾斜角为10度。
前述的方法,其中在该第一步骤植入该氙的剂量约为5E13到5E14原子数/平方公分(atm/cm2),在第二阶段植入该氙的剂量约为5E13到5E14原子数/平方公分(atm/cm2)。
前述的方法,其中该金属是由镍(Ni)和镍/钛(Ni/Ti)其中之一组成。
前述的方法,其中该快闪退火处理具有一预热步骤。
前述的方法,其中该预热步骤的温度在250℃到350℃之间。
前述的方法,其中执行该快闪退火处理的一能量约为19焦耳(J)到30焦耳(J)。
本发明的目的及解决其技术问题还采用以下技术方案来实现。依据本发明提出的一种金氧半导体场效应电晶体,包含:一基板,具有一栅极结构包含:一栅极氧化层;一栅极电极层;及一源/漏极区,具有不纯物离子掺杂;一非晶硅层,在该源/漏极区内;一硅化金属层,在该非晶化层内;以及一快闪退火处理导电性源/漏极区。
本发明的目的及解决其技术问题还可采用以下技术措施进一步实现。
前述的金氧半导体场效应电晶体,其中产生该非晶硅层的一植入种类是氙。
前述的金氧半导体场效应电晶体,其中该硅化金属层为硅化镍或镍/氮化钛(Ni/TiN)硅化金属其中之一。
本发明的目的及解决其技术问题另外还采用以下技术方案来实现。依据本发明提出的一种半导体元件的制造方法,该方法包含:提供具有至少一栅极结构的一基板,该栅极结构包含:一栅极氧化层;一栅极电极层;以及一源/漏极区,具有不纯物离子掺杂;形成一非晶硅层在该源/漏极区中,形成该非晶硅层是利用一氙两步骤的非晶硅化布植工艺;沉积一镍金属于该非晶硅层之上;形成一硅化镍层于该非晶硅层内;以及快闪退火处理该基板。
本发明与现有技术相比具有明显的优点和有益效果。由以上可知,为了达到上述目的,本发明一较佳实施例,提供了一种用来在MOSFET的源/漏极区中减轻缺陷的系统,可包括一基板,基板至少具有一个栅极结构,栅极结构包含栅极氧化层和栅极电极层、具有不纯物离子掺杂的源/漏极区、以非晶硅化布植形成的非晶硅层、限制在非晶硅层中的硅化镍层、以及经过快闪退火处理的源/漏极区。
经由上述可知,本发明是一种适用于减轻金氧半导体场效电晶体源/漏极区缺陷的结构和方法。其基板的栅极结构包含栅极氧化层、栅极电极层和植入不纯物离子的源/漏极区。利用非晶硅化布植工艺在源/漏极区内产生非晶化层。在不使已存在的缺陷恶化的情况下,在非晶化层上沉积金属层,并经反应生成硅化金属。将基板利用快闪退火处理可恢复源/漏极区的导电性。
借由上述技术方案,本发明金氧半导体场效应电晶体及源/漏极区中降低损坏的方法至少具有下列优点:本发明揭露的较佳实施例的应用在于可降低或消除管缺陷(pipe defects)和尖锋(spike)结构的效应。本发明揭露的较佳实施例的更进一步应用是在非晶硅化布植工艺之后,利用退火处理,恢复源/漏极区的导电性。
上述说明仅是本发明技术方案的概述,为了能够更清楚了解本发明的技术手段,而可依照说明书的内容予以实施,并且为了让本发明的上述和其他目的、特征和优点能够更明显易懂,以下特举较佳实施例,并配合附图,详细说明如下。
附图说明
图1a是在源/漏极区的损害剖面图。
图1b是经过现有的硅化金属工艺后所形成源/漏极区的缺陷恶化剖面图。
图2a,图2b和图2c是在修补过程中依照本发明实施例的源/漏极区剖面图。
图3是一种现有的工艺流程图。
图4是一种依照本发明实施例的工艺流程图。
100:基板 102:栅极区
104:间隙壁区 106:轻掺杂漏极区
108:重掺杂漏极区 110:缺陷
112:硅化金属层 200:基板
202:栅极区 204:间隙壁区
206:轻掺杂漏极区 208:漏极区
210:延伸缺陷 214:非晶硅化布植植入区
216:硅化金属层
302、304、306、308、310、312、402、403、404、406、408、410、412:步骤
具体实施方式
为更进一步阐述本发明为达成预定发明目的所采取的技术手段及功效,以下结合附图及较佳实施例,对依据本发明提出的金氧半导体场效应电晶体及源/漏极区中降低损坏的方法具体实施方式、结构、特征及功效,详细说明如后。
下面将揭露多种不同的实施例来实行不同实施例的不同特征。以下将以特殊的组成与安排来简化说明的内容。然而这些仅为范例,本发明的范围并不受其限制。另外,本发明揭露的多种实施例中有许多重复应用的数字与文字,其目的在于简单清楚表达各实施例中的联结关系与装配讨论。此外,文中所叙述的第一结构形成于第二结构之上,在某些实施例中用来表示两者之间有直接的接触,亦可某些实施例中可能有其他结构介入于其中,使得第一结构与第二结构并无直接接触。
本发明揭露将依照本发明较佳实施例在上下文涉及部分作描述,即为MOSFET的漏极区。本发明也可应用在MOSFET的其他区域,包含源极区。
参照图1a,是绘示在现有方法下源/漏极区未修补的损害的剖面示意图。基板100是MOSFET的一部分且具有如图所示的栅极区102。栅极区102包含多晶硅的栅极电极区和薄栅极氧化区(未明确显示)。间隙壁区104位在MOSFET的轻掺杂漏极区106之上的区域与栅极区102邻接。本领域一般技术人员能了解,这是一个对称的源/漏极工艺,尽管未在图中显示出来。重掺杂漏极区108包含延伸缺陷110。接着参照图1b,是形成硅化金属后并经过退火的基板100。硅化金属层112在漏极区106和108内。硅化金属的形成会使在漏极区108和轻掺杂漏极区106内的缺陷线110扩大。这些缺陷会使元件退化和失效的机率增加。
参照图2a,图2b,图2c,是本实施例实行修补工艺的源/漏极区剖面示意图。图2a的结构与图1a相似,显示经过植入过程和退火处理后的源/漏极区有基板200,栅极区202,间隙壁区204,轻掺杂漏极区206,漏极区208,和延伸缺陷210。图2b显示在经过非晶硅化布植工艺后的基板。非晶硅化布植的植入区214是一非晶硅层,因此缺陷不会恶化。最后,参照图2c,是形成硅化金属与经过退火的后的基板200。硅化金属层216在非晶硅化布植的植入区214中形成。在此可注意到,由于硅化金属在非晶硅区中受控制,故在形成硅化金属时,缺陷线并不会恶化。元件性能可得到改善。快闪退火处理工艺是依照本发明实施例的进一步工艺,其中快闪退火处理工艺可修复在源/漏极区内因非晶硅化布植工艺对导电性所造成的损害。
图3是图1所示的现有的工艺流程图,此方法是从一经过标准晶圆工艺的基板开始,基板包括经过植入与退火处理的源/漏极区。在基板上执行标准的光刻胶保护氧化层(resist protect oxide;RPO)蚀刻(步骤302)。随后进行后光刻胶保护氧化层清洁(Post RPO Clean)(步骤304)。通常是使用湿式清洁,但是,在本实施例中,干式清洁亦为范围之内。执行原位(in-situ)清洁并沉积镍与氮化钛(Ni/TiN)层(步骤306),然后完成第一快速热退火处理(rapid thermal anneal:RTA)(步骤308),以形成一硅化金属层,如图1b所示的硅化金属层112。在随后的工艺中,例如将未反应的镍移除(步骤310)和完成第二次退火处理(步骤312),并无法修补如图1b所示的由硅化金属所引起的延伸缺陷的损害。
参照图4,依照本发明实施例所绘示的工艺流程图。如图3所示的流程,在步骤开始之前,先执行标准的晶圆工艺,包括源/漏极区的植入和退火处理。执行标准的光刻胶保护氧化层蚀刻(步骤402)。然后,本发明方法在基板上提供一非晶硅化布植工艺(步骤403)。此非晶硅化布植工艺包含两步骤的氙离子植入工艺。由于氙是重掺杂离子,且其性质不活泼,故可以为一较佳的种类。第一植入过程的能量约为5电子伏特(KeV)到30电子伏特,较佳地为10电子伏特(KeV);第一植入过程的剂量为5E13到5E14原子数/每平方公分(atm/cm2),其植入倾斜角接近10度。第二植入过程的能量约为7电子伏特(KeV)到30电子伏特(KeV),较佳地为15电子伏特(KeV);第二植入过程的剂量为5E13到5E14原子数/每平方公分(atm/cm2),并以10度的倾斜角植入。剂量、能量与倾斜角度将会依照本发明实施例的目的与范围而有改变。然而应注意,不可在太高的能量或太高的剂量下执行非晶硅化布植工艺,因为在高于此范围的植入能量或高剂量将引起元件漏电流。
随后的工艺步骤有:后光刻胶保护氧化层清洁(步骤404),原位清洁并沉积镍与氮化钛层(步骤406),执行快速热退火处理(rapid thermal anneal:RTA)(步骤408),移除未反应的镍(步骤410)。在65奈米(nm)以下的先进元件技术中,硅化镍在硅化金属的应用上有相当的重要性。硅化镍比硅化钛和硅化钴有更多应用是因为形成硅化镍时的低的硅消耗率(consumptionrate),具有低电阻性(范围在15-20μOhm/cm),以及更重要的是具有无或有限的窄线效应。硅化镍的形成工艺是执行单一步骤的退火处理,将未反应镍经过选择性蚀刻处理后移除,形成低电阻的硅化镍相。硅化镍的形成温度约在500℃,所需的温度预算(thermal budget)低。在温度高于750℃以上,会有硅化镍的其他相,二硅化镍(NiSi2)的形成。二硅化镍相较于硅化镍会具有较高的阻抗,约为50μOhm/cm。二硅化镍薄膜的硅晶聚结是发生在高温下,导致高电阻,此高电阻会导致元件性能连续的下降。但是,其他金属系统也可依照本发明实施例使用。
在未反应镍移除之后,将基板经过快闪退火处理(步骤412)。快闪退火处理是一种尖峰退火处理(spike annealing)与次熔融(sub-melt)雷射热退火处理(laser thermal anneal;LTA)的混合。利用电弧灯放电,以仅照射在具有元件的晶圆正面,此被照射面(junction)经历温度约达1300度(℃),温度峰值-50C(Tpeak-50C),持续时间约330微秒,随着传导到晶圆背面而冷却。由于时间的关系,使扩散作用减到最小。温度峰值的固态溶解度保持一定。
下表为快闪退火处理步骤412与图3中第二快速热退火处理步骤312的比较表。快闪退火处理步骤包括一预热步骤,预热步骤的预热温度如比较表所示,是从100℃到500℃,而较佳是从250℃-350℃。执行此快闪退火处理的一能量约为15焦耳(J)到50焦耳(J),特别是由19焦耳(J)到30焦耳(J)较佳。
工艺 | 第二快速热退火处理 | 快闪退火处理 |
设备 | 热脉冲 | 光脉冲 |
预热温度 | 200℃-300℃ | 100℃-500℃ |
升温速度 | 5℃-15℃ | 未定义 |
最大温度 | <500℃(较佳) | <1050℃(较佳) |
降温速度 | 10℃-30℃ | 未定义 |
能量 | 未定义 | (15J-50J)<25J(较佳) |
以上所述,仅是本发明的较佳实施例而已,并非对本发明作任何形式上的限制,虽然本发明已以较佳实施例揭露如上,然而并非用以限定本发明,任何熟悉本专业的技术人员,在不脱离本发明技术方案范围内,当可利用上述揭示的技术内容作出些许更动或修饰为等同变化的等效实施例,但凡是未脱离本发明技术方案内容,依据本发明的技术实质对以上实施例所作的任何简单修改、等同变化与修饰,均仍属于本发明技术方案的范围内。
Claims (14)
1.一种在金氧半导体场效应电晶体的源/漏极区中降低损坏形成的方法,其特征在于该方法包含:
提供一基板,该基板具有至少一栅极结构,该栅极结构包含:
一栅极氧化层;
一栅极电极层;及
一源/漏极区,具有不纯物离子掺杂;
植入一离子种类以产生非晶硅层;
沉积一金属层在该源/漏极区中并进行反应;以及
快闪退火处理该基板。
2.根据权利要求1所述的方法,其特征在于其中产生该非晶硅层的离子种类是氙。
3.根据权利要求2所述的方法,其特征在于其中该氙经由两步骤工艺植入。
4.根据权利要求3所述的方法,其特征在于其中植入该氙的该第一步骤使用5-30千电子伏特,植入该氙的该第二步骤使用7-30千电子伏特。
5.根据权利要求3所述的方法,其特征在于其中植入该氙的一倾斜角为10度。
6.根据权利要求3所述的方法,其特征在于其中在该第一步骤植入该氙的剂量为5E13到5E14原子数/平方公分,在第二阶段植入该氙的剂量为5E13到5E14原子数/平方公分。
7.根据权利要求1所述的方法,其特征在于其中该金属是由镍和镍/钛其中之一组成。
8.根据权利要求1所述的方法,其特征在于其中该快闪退火处理具有一预热步骤。
9.根据权利要求8所述的方法,其特征在于其中该预热步骤的温度在250℃到350℃之间。
10.根据权利要求1所述的方法,其特征在于其中执行该快闪退火处理的一能量为19焦耳到30焦耳。
11.一种金氧半导体场效应电晶体,其特征在于包含:
一基板,具有一栅极结构包含:
一栅极氧化层;
一栅极电极层;及
一源/漏极区,具有不纯物离子掺杂;
一非晶硅层,在该源/漏极区内;
一硅化金属层,在该非晶化层内;以及
一快闪退火处理导电性源/漏极区。
12.根据权利要求11所述的金氧半导体场效应电晶体,其特征在于其中产生该非晶硅层的一植入种类是氙。
13.根据权利要求11所述的金氧半导体场效应电晶体,其特征在于其中该硅化金属层为硅化镍或镍/氮化钛硅化金属其中之一。
14.一种半导体元件的制造方法,其特征在于该方法包含:
提供具有至少一栅极结构的一基板,该栅极结构包含:
一栅极氧化层;
一栅极电极层;以及
一源/漏极区,具有不纯物离子掺杂;
形成一非晶硅层在该源/漏极区中,形成该非晶硅层是利用一氙两步骤的非晶硅化布植工艺;
沉积一镍金属于该非晶硅层之上;
形成一硅化镍层于该非晶硅层内;以及
快闪退火处理该基板。
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US20070010073A1 (en) | 2005-07-06 | 2007-01-11 | Chien-Hao Chen | Method of forming a MOS device having a strained channel region |
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- 2007-11-13 CN CNA2007101664512A patent/CN101350308A/zh active Pending
Cited By (4)
Publication number | Priority date | Publication date | Assignee | Title |
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CN102468172A (zh) * | 2010-11-12 | 2012-05-23 | 中芯国际集成电路制造(上海)有限公司 | 半导体器件制造方法 |
CN102468172B (zh) * | 2010-11-12 | 2015-05-20 | 中芯国际集成电路制造(北京)有限公司 | 半导体器件制造方法 |
CN108987475A (zh) * | 2017-05-31 | 2018-12-11 | 中芯国际集成电路制造(上海)有限公司 | 半导体器件及其形成方法 |
CN108987475B (zh) * | 2017-05-31 | 2021-10-15 | 中芯国际集成电路制造(上海)有限公司 | 半导体器件及其形成方法 |
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US20090020757A1 (en) | 2009-01-22 |
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