CN101304017B - 烧结的功率半导体基片及其制造方法 - Google Patents

烧结的功率半导体基片及其制造方法 Download PDF

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CN101304017B
CN101304017B CN2008100967349A CN200810096734A CN101304017B CN 101304017 B CN101304017 B CN 101304017B CN 2008100967349 A CN2008100967349 A CN 2008100967349A CN 200810096734 A CN200810096734 A CN 200810096734A CN 101304017 B CN101304017 B CN 101304017B
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semiconductor substrate
power semiconductor
pressure
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articulamentum
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C·格布尔
H·布拉姆尔
U·赫尔曼
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Semikron Elektronik GmbH and Co KG
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Abstract

本发明描述一种功率半导体基片，包括一绝缘的面状的基体、至少一个在至少一个主面上设置的层序列，其包括一薄的粘附连接层、一烧结金属层和一导电层。所属的方法具有以下主要的步骤：对面状的绝缘的基本的至少一个主面的至少一部分表面涂覆粘附连接层；将一由烧结金属和一溶剂制成的膏状层设置在粘附连接层的一部分表面上或整个表面上；将导电层设置在烧结金属层上；对功率半导体基片的导电层施加压力。

Description

烧结的功率半导体基片及其制造方法
技术领域
本发明描述一种功率半导体基片，包括一绝缘的基体和至少一个印制导线。这种功率半导体基片至今例如已知作为AMB(活性的金属铜焊)、DCB(直接的铜粘结)或IMS(绝缘的金属基片)基片。
所述至少一个印制导线用作为例如与功率半导体构件或与内部的和/或外部的连接元件的导电连接。这种与印制导线的连接元件可以例如借助于钎焊技术的连接或借助于压力接触的连接构成。
按照现有技术已知DCB基片，其包括一陶瓷的基体，常常是氧化铝或氮化铝，与在其上设置的由铜膜制成的印制导线。US 4 563 383公开了例如已知的DCB基片。
对这样的DCB基片不利的是，由于在制造过程中引入高温，紧接制造过程之后或在一以后的过程步骤中，例如在构造一功率半导体模块的过程中基片具有一挠度。根据实验该挠度的已知值在这里为每单位长度约1％。按照应用目的，一定程度的挠度是可接受的，当然大多数应用共同的是，一尽可能小的挠度是有利的。
本发明的目的在于，提供一种具有微小的挠度的功率半导体基片和一种用于这样的功率半导体基片的简单而便宜的制造方法。
按照本发明该目的这样达到，即借助于一种按权利要求5的方法制造一种具有权利要求1的特征的功率半导体基片。优选的实施形式描述于诸从属权利要求中。
本发明的功率半导体基片的出发点是一种绝缘的面状的基体。在其两主面的至少一个上设置至少一个包括一薄的粘附连接层、一烧结金属层和一导电层的层序列。在这里，至少一个这样的层序列构成一功率半导体基片的印制导线。近似于已知的上述的基片方案在这里也优选的是，在基体的一第一主面上设置多个这样的层序列，使其构成各印制导线并且在一第二主面上设置一层序列并且构成一无结构化的接触层用于一冷却构件。
在这方面有利的是，面状的基体是一工业陶瓷例如氧化铝或氮化铝或氮化硅。
此外有利的是，粘附连接层具有一在0.5μm与10μm之间的厚度。优选该粘附连接层还具有一例如电镀沉积的并指向烧结金属层那边的贵金属表面。烧结金属层有利地具有一在5μm与50μm之间的厚度。在这方面优选的是，烧结金属层具有一贵金属例如银的多于90％的份量。
此外优选的是，导电层构成为厚度在100μm与800μm之间的铜膜并且具有一指向烧结金属层那边的贵金属表面。
本发明用于制造一这样的功率半导体基片的方法具有下列主要的步骤：
·对面状的绝缘的基体的至少一个主面的至少一部分表面涂覆粘附连接层；
·将一膏状的由烧结金属和一溶剂制成的层设置在粘附连接层的一部分表面上或整个表面上；
·将导电层设置在烧结金属层上；
·对功率基片施加压力。
在这方面可以优选的是，借助于丝网印刷方法涂覆膏状层。在这种情况下一方面可以达到在要求的层厚时的所需的定位精度。另一方面可便宜地实现该方法。
通过应用一压力机和两冲模可以提供一对膏状层施压的有利的实施形式。在这方面还优选的是，至少一个冲模构成有一在其上设置的产生近似静压压力的硅酮垫。
在这方面优选在功率半导体基片上设置一薄膜，优选一聚四氟乙烯薄膜，并紧接着对该结合施加压力。
该功率半导体基片和制造方法的特别优选的进一步构成列举于实施例的描述中。并且借助图1的实施例进一步说明本发明的方案。
图1示出一本发明的功率半导体基片10。而且在这里进一步说明本发明的制造方法。功率半导体基片10具有一成面状构成的绝缘的基体12。该基体12应该具有一高的电阻同时具有一低的热阻，因此对此特别适用一工业陶瓷，例如氧化铝或氮化铝或氮化硅。在这里氧化铝提供包括这些要求和一便宜的制造一特别好的综合。
为了准备接着的烧结连接，在这里在基体12的两主面120、122上优选整面地涂覆一粘附连接层20、22、24的薄层，其特别的制造方法不是本发明的目标。在这里重要的是，该粘附连接层20、22、24具有一在0.5μm与10μm之间优选的厚度。该粘附连接层20、22、24有利地具有一至少90％的贵金属份量。附加或可选择地，除所述组成外，粘附连接层20、22、24在远离基体12的表面240上具有一例如电镀沉积的贵金属表面。
此外优选可以将该粘附连接层20、22、24整面地涂覆在或待继续处理的主面120、122上并且在另一过程步骤中按照印制导线的以后的形状构造该粘附连接层20、22、24。
在下一过程步骤中例如借助于丝网印刷技术涂覆层厚在5μm与50μm之间的烧结金属层30、32、34。该烧结金属层30、32、34在制造过程的该时刻由一实际的烧结金属的膏状层和一溶剂组成。该烧结金属在这里构成为具有伸展在微米的数量级内的金属片。
由于在烧结过程开始之前应从膏状层中再次排除达至少90％的份量的溶剂，有利的是，对基片10在一适当的时间间隔施加一在350K与450K之间的温度。
在下一步骤中在膏状层上或在烧结金属层30、32、34上设置导电层40、42、44。在这方面在该实施例中涉及一铜膜，其已按印制导线的以后的形状构造。为了有效地导电，该导电层40、42、44具有一在100μm与800μm之间的厚度。
为了很有效地构成烧结连接，导电层40、42、44的铜膜构成有一指向烧结金属层那边的贵金属表面440。
在将导电层40、42、44设置在烧结金属层30、32、34上以后，在导电层40、42、44上导入一压力。在这里可以有利地在施加压力之前，在导电层40、42、44与压力装置的冲模之间设置一薄膜、优选一聚四氟乙烯薄膜，以便保证在施加压力以后由此容易地脱离。
已证明有利的是采用一大于8MPa的最终压力并同时将功率基片10加热到一在350K与600K之间的温度。
作为上述制造方法的替代方案，也可以在基体的一侧面或两侧面上整面地涂覆各一个包括粘附连接层、烧结金属层和导电层的层序列并且在一最后的过程步骤中按照印制导线合理的预定构造。为此湿化学的腐蚀技术是适用的。
本发明的功率半导体基片10的一个优点是，通过基体12和导电层40、42、44的烧结连接构成一可持久保持的和在定性上很高级的连接。由于在烧结过程的范围内加热优选不超过600K，功率半导体基片10的热造成的挠度比在按现有技术的制造方法中显著地减小。
按照本发明的制造关于需要的材料，同样关于一用于功率半导体构件的一加压烧结连接需要的设备按现有技术是相应的。因此一这样的功率半导体基片10的特别有利的制造是可能的，因为这是简单而便宜的。

Claims (9)

1.用于制造功率半导体基片(10)的方法，包括下列主要的步骤：
对一面状的绝缘的基体(12)的至少一个主面(120、122)的至少一部分表面涂覆一薄的粘附连接层(20、22、24)，该粘附连接层的至少90％由贵金属制成；
将一由一具有至少90％的银份量的烧结金属和一溶剂制成的膏状层设置在粘附连接层(20、22、24)的至少一部分表面上或整个表面上；
分别将一导电层(40、42、44)设置在配设的烧结金属层(30、32、34)上；
对功率半导体基片(10)的至少一个导电层(40、42、44)施加压力；
其中烧结金属层(30、32、34)具有一在5μm与50μm之间的厚度。
2.按照权利要求1所述的方法，其特征在于，面状的基体(12)是工业陶瓷。
3.按照权利要求2所述的方法，其特征在于，所述工业陶瓷是氧化铝或氮化铝或氮化硅。
4.按照权利要求1或2所述的方法，其特征在于，粘附连接层(20、22、24)具有一在0.5μm与10μm之间的厚度并且具有一指向烧结金属层(30、32、34)那边的贵金属表面(240)，和/或导电层(40、42、44)是一厚度在100μm与800μm之间的铜膜并且具有一指向烧结金属层(30、32、34)的贵金属表面(440)。
5.按照权利要求1或2所述的方法，其特征在于，借助于一丝网印刷方法涂覆所述膏状层。
6.按照权利要求1或2所述的方法，其特征在于，借助于一压力机和两冲模施加压力，其中至少一个冲模构成有一个在其上设置的产生近似静压压力的硅酮垫。
7.按照权利要求1或2所述的方法，其特征在于，在施加压力时 最大的最终压力相当于至少8MPa。
8.按照权利要求1或2所述的方法，其特征在于，在施加压力的过程中将功率半导体基片(10)加热到在350K与600K之间的温度。
9.按照权利要求1或2所述的方法，其特征在于，在施加压力之前用一薄膜覆盖功率半导体基片(10)。 
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