CN101263597A - 具有薄板内联机的半导体封装 - Google Patents

具有薄板内联机的半导体封装 Download PDF

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CN101263597A
CN101263597A CNA2006800333427A CN200680033342A CN101263597A CN 101263597 A CN101263597 A CN 101263597A CN A2006800333427 A CNA2006800333427 A CN A2006800333427A CN 200680033342 A CN200680033342 A CN 200680033342A CN 101263597 A CN101263597 A CN 101263597A
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lead
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CN100590860C (zh
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孙明
石磊
何约瑟
刘凯
张晓天
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Alpha and Omega Semiconductor Ltd
Alpha and Omega Semiconductor Inc
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Abstract

本发明公开一种半导体封装，包括一具有漏极、源极、栅极引脚的导线架，一半导体晶粒耦合该导线架，半导体晶粒具有金属化源极区域与栅极区域，其藉由一保护区域分开，一图案化源极连接，其耦合源极引脚至半导体晶粒金属化栅极区域，一半导体晶粒汲极区域耦合至漏极引脚，及一封装体覆盖半导体晶粒及漏极、源极与栅极引脚的至少一部分。

Description

具有薄板内联机的半导体封装
发明背景
本发明涉及一种半导体封装，特别是一种在功率半导体组件的源极、栅极金属化区域与导线架的源极、栅极引脚间具有薄板内联机的半导体封装。
传统的，半导体组件是利用薄板内联机或焊线的方式连接至导线架。例如，美国专利号第5,821,611号公开了一种半导体组件，包括一第一引线，其具有一尖端且该尖端是由一孤立区域形成的，一半导体芯片单元，其藉由一焊层位于该第一引线的孤立区域上，并具有数个电极凸块，及包括额外数个皆具有尖端的引线，其藉由各自的锡膏连接至电极凸块。此额外数个引线包括至少第二与第三引线。然后在一加热熔炉中将引线铸成合金至电极凸块，但在加热期间凸块会扩散而产生不想要的形状。
美国专利号第6,040,626号公开了一半导体封装结构，是在MOSFET上面与电线间使用一种混合的连接方式，其中MOSFET上面包括一低电阻的薄板部，用以连接至源极，焊线是用以连接至栅极。由于在焊线过程中，介电层受损，故焊线可能会造成组件有短路的现象。
美国专利号第6,249,041号所公开的半导体封装是直接连接引脚。一半导体组件包括一半导体芯片，其上表面或下表面具有接触区域。一第一引脚组件具有一引脚组件接触区，附着至半导体芯片的其中的接触区域，其中第一引脚组件是由一金属材质的半硬式薄片所形成的。此第一引脚组件亦具有至少一引脚连接至引脚组件接触区，并从引脚组件接触区延伸回来。一第二引脚组件具有一引脚组件接触区，附着至半导体芯片的其中的另一接触区域，其中第二引脚组件是由一金属材质的半硬式薄片所形成的。此第二引脚组件也具有至少一引脚连接至引脚组件接触区，并从引脚组件接触区延伸回来。一封装体包覆住此半导体芯片、第一引脚组件的引脚接触区与第二引脚组件的引脚接触区。由于引脚组件直接连接至芯片，半导体组件从封装起，具有低电阻与低热阻的分布。引脚组件接触区是藉由一导电黏接层与半导体芯片上的引脚接触区域接触。此导电黏接层可以是填充银的环氧基树脂、聚亚酰胺膏或锡铅凸块，且假若需要的话，导电黏接层可于一硬化炉中硬化，且黏接层并不包括软焊料或锡膏。
另外一个直接利用连接引脚的半导体封装是由美国专利号第6,479,888号公开的，一MOSFET包括复数个内引脚，电性连接至一半导体颗粒的一表面电极，其中此半导体颗粒在其主要表面上具有一场效应晶体管。这些内引脚藉由一栅极连接部和源极连接部连接，与主要表面电性连接，其中栅极连接部和源极连接部是由凸块所构成的。
因此，对于半导体封装包括一半导体功率组件利用图案化薄板连接到一导线架源极、栅极接触区域是有需要的。对于半导体封装组件具有保护区也是有需要的，以用来限制在焊接过程中焊料的流动。对于半导体封装也需要一个由镍/金所形成的金属化区域。对于半导体封装过程，其增加生产率也是有需要的。对于半导体封装方式，其提供图案化薄板至半导体功率组件上的软性附接过程也是必要的。对于半导体封装也需要具有一曝露的源极板。对于半导体封装，其具有减小的电阻也是必要的。对于半导体封装亦需要具有改善热损耗的性质。
发明内容
本发明的目的之一是藉由在导线架的源极、栅极接触区域及功率半导体功率组件的源极、栅极接触区域间具有的薄板联机，以克服背景技术中的限制和缺点，并曝露源极板的一部分以改善热散耗现象。
本发明的另一目的是提供一种半导体封装，其包括一具有漏极、源极与栅极引脚的导线架，一半导体晶粒耦合至导线架，且半导体晶粒具有金属化源极与栅极区域，一图案化源极连接耦合源极引脚至此半导体晶粒金属化源极区域，一图案化栅极连接耦合栅极引脚至此半导体晶粒金属化栅极区域，一半导体晶粒漏极保护区域耦合至漏极引脚，及一封装体覆盖半导体晶粒及漏极、源极与栅极引脚的至少一部分。
本发明的又一目的是提供一种半导体封装，其包括一具有漏极、源极与栅极引脚的导线架，一半导体晶粒耦合至导线架，且半导体晶粒具有镍/金金属化源极与栅极区域，一图案化源极连接耦合源极引脚至此半导体晶粒金属化源极区域，此图案化源极连接焊接至此半导体晶粒金属化源极区域，一图案化栅极连接耦合栅极引脚至此半导体晶粒金属化栅极区域，一半导体晶粒金属化漏极区域耦合至漏极引脚，及一封装体覆盖半导体晶粒及漏极、源极与栅极引脚的至少一部分。
本发明的再一目的是提供一种半导体封装，其具有一栅极固定组件固定至一半导体晶粒金属化栅极区域，半导体封装包括一具有漏极、源极与栅极引脚的导线架，一半导体晶粒耦合至导线架，且半导体晶粒具有金属化源极与栅极区域，一源极固定组件耦合源极引脚至半导体晶粒金属化源极保护区域，一半导体晶粒金属化漏极区域耦合至栅极引脚，一封装体覆盖半导体晶粒及该漏极、源极与栅极引脚的至少一部分，及其中藉由在栅极固定组件中所形成的一孔洞，栅极固定组件耦合栅极引脚至半导体晶粒金属化栅极区域。
本发明的概要、较重要的特征已阐述，然而为了更方便的了解本发明及对此技术领域的贡献，请同时参照以下详细描述的实施方式。当然，本发明的其它特征将也在下述描述，且这些特征将构成专利范围。
在详细阐述本发明的至少一个实施例之前，请了解本发明并未限制在所申请的内容，未限制在发明的细节、下述所提出的组件组合方式、图式内容。本发明能够具有其它实施例，并可用许多不同方式具体实施。再者，于此所使用的措词、用语和摘要是为了描述，并不能视为限制。
对于本技术领域内的技术人员，将会知悉以上所阐述的概念可马上作为其它方式与系统设计用以实现本发明的数个依据。因此，但凡包括等效方法或系统的专利申请内容，都不能脱离本发明的精神与范围。
附图说明
图1为本发明的一半导体封装结构的实施例示意图；
图2为本发明沿着图1的路线2-2的截面示意图；
图3为本发明沿着图1的路线3-3的截面示意图；
图3A为本发明的一图案化栅极连接位于一金属化栅极区域上的示意图；
图3B为本发明的一栅极固定组件示意图；
图3C为本发明图1的半导体封装示意图，其显示了另一种金属化栅极区域；
图4为本发明图1的半导体封装的一部分截面示意图；
图5为本发明图1的半导体封装的另一部分截面示意图；
图6为本发明的另一半导体封装的实施例示意图；
图7为本发明沿着图6的半导体封装的路线A-A的截面示意图；
图8为本发明沿着图6的半导体封装的路线B-B的截面示意图；
图9为本发明图6的半导体封装的一部分截面示意图；
图10为本发明的又一半导体封装的实施例示意图；
图11为本发明沿着图10的半导体封装的路线A-A的截面示意图；
图12为本发明沿着图10的半导体封装的路线B-B的截面示意图。
具体实施方式
以下详细内容是实现本发明的最佳实施例，且该内容并非是要限制本发明的内容，而只是为阐明本发明的主要原理，因为专利权利要求才是最佳定义本发明的范围。
本发明主要提供一半导体组件封装，其在导线架的源极、栅极接触区域及功率半导体功率组件的金属化源极、栅极接触区域间具有薄板联机。金属化源极与栅极保护区域是较佳地镍/金电镀或溅镀表面。由于焊线过程中，介电层损害常会导致短路问题，故金属化源极与栅极区域提供薄板内联机以改良焊接及减少过度焊接。因为软焊料与锡膏是用于连接薄板至金属化源极与栅极区域，故金属化源极与删极区域更进一步消除锡铅凸块与环氧基树脂黏接层的需要。
请参照图1至图5，为本发明的第一实施例，显示了一半导体封装100，其包括一导线架105，其具有一漏极接触部107，一源极接触部110，和一栅极接触部115。一功率半导体晶粒120包括一金属化漏极区域(图中未示)，其借着焊料回流而耦合至漏极接触部107。
半导体源极与栅极金属化区域藉由镍/金电镀或溅镀所形成，并可同时参照图3A，一栅极金属化区域160是一圆形构造。本发明人发现在焊料回流期间，圆形金属化区域160利于限制软焊料与锡膏的回流至圆形金属化区域160的边界，因此减少不想要的形状与短路影响。
一图案化源极板125包括一外部曝露部分127及一内部部分130。内部部分130耦合源极接触部110，外部曝露部分127是曝露在封装体135的外面。图案化源极板125藉由焊料回流，使用软焊料或锡膏耦合至金属化源极区域。金属化源极区域覆盖功率半导体晶粒120上表面的一大部分以改善热损耗、减少电阻与阻抗。
一图案化栅极板137连接金属化栅极区域160至导线架栅极接触区域115。图案化栅极板137包括一孔洞165，其形成在该图案化栅极板137的一栅极板端部167上。一锁固球155在焊料回流时形成，提供图案化栅极板137(图3B)的机械式稳定。在本发明的一方面，软焊料可位于孔洞165中并允许在焊料回流期间流经孔洞165到金属化栅极区域160。金属化栅极区域160提供一用于焊料的焊接表面，限制软焊料至圆形区域的流动。其中，栅极板137的厚度比源极板125的厚度薄。
同时参照图3C，显示了另一种金属化栅极区域170，其包括一个十字形区域。
如图6至图9所示，为本发明的另一实施例，显示了一半导体封装600，包括一导线架605，其具有一漏极接触部607，一源极接触部610，一栅极接触部615。一功率半导体晶粒620具有一金属化漏极区域(图中未示)，借着焊料回流耦合至漏极接触部607。
半导体源极与栅极金属化区域是藉由镍/金电镀或溅镀形成。一图案化源极板625包括一外部曝露部分627及一内部部分630。外部曝露部分627是曝露在封装体635的外面。图案化源极板625藉由焊料回流使用软焊料或锡膏耦合至金属化源极区域。
一图案化栅极板637连接金属化栅极区域640至导线架栅极接触区域。图案化栅极板637藉由焊料回流连接至金属化栅极区域640以提供图案化栅极板637的机械式稳定。
同时参照图10至图12，显示了一半导体封装1000，其包括一导线架1005，其具有一漏极接触部1007，一源极接触部1010，及一栅极接触部1015。一功率半导体晶粒1020包括一金属化漏极区域(图中未示)，其借着焊料回流耦合至漏极接触部1007。
半导体源极与栅极金属化区域是藉由镍/金电镀或溅镀形成。一图案化源极板1025包括一外部曝露部分1027及一内部部分1030。外部曝露部分1027是曝露在封装体1035的外面。图案化源极板1025藉由焊料回流使用软焊料或锡膏耦合至金属化源极区域。
一图案化栅极板1037连接金属化栅极区域1040至导线架栅极接触区域。图案化栅极板1037包括一勾部1039以连接至金属化栅极区域1040。图案化栅极板1037藉由焊料回流连接至金属化栅极区域1040，以提供图案化栅极板1037的机械式稳定。
本发明使用镍/金组件图案化源极、漏极、栅极金属化区域。镍/金提供了在图案化源极板与图案化栅极板间之更好的连接方式，并提供了镍/金制程中的一源极、漏极、栅极金属化的简化过程，因此改善生产量。
此镍/金制程提供一Ni层在金属区域上及一Au层以保护Ni层。因为Ni没有扩散至Al金属区域，一由包括Ni/Al所构成的介金属提供一高密度层至被焊接的图案化源极连接和栅极连接。
本发明提供一种利于图案化源极板与栅极板的连接方式。曝露的源极板提供改善热损耗，栅极板则提供了在栅极金属化区域与导线架栅极接触区域间增进改善的机械式连接关系方式。因焊线不需要耦合栅极至导线架栅极接触连接区域，栅极板和源极板可以在同一程序中连接栅极板和源极板。藉由一保护区域图案化且绝缘金属化区域，以避免在焊料回流期间有焊料扩散发生。
以上所述的实施例仅为说明本发明的技术思想及特点，其目的在于使本领域的技术人员能够了解本发明的内容并据以实施，并不能以此限定本发明的专利范围，即但凡依本发明所描述的精神所作的均等变化或修饰，仍应涵盖在本发明的专利范围内。

Claims (20)

1.一种半导体封装，其特征在于，包括：
一导线架，其具有漏极、源极与栅极引脚；
一半导体晶粒，其耦合该导线架，该半导体晶粒具有金属化源极与栅极区域；
一图案化源极连接，其耦合该源极引脚至该半导体晶粒金属化源极区域；
一图案化栅极连接，其耦合该栅极引脚至该半导体晶粒金属化栅极区域；
一半导体晶粒漏极区域，其耦合至该漏极引脚；以及
一封装体，其覆盖该半导体晶粒及该漏极、该源极与该栅极引脚的至少一部分。
2.如权利要求1所述的半导体封装，其特征在于，所述的图案化源极连接的一部份是曝露在该封装体外面的。
3.如权利要求1所述的半导体封装，其特征在于，所述的图案化栅极连接包括一开口，通过该开口使得图案化栅极连接被焊接至金属化栅极区域。
4.如权利要求3所述的半导体封装，其特征在于，所述的焊料在该图案化栅极连接的顶部形成一固定组件。
5.如权利要求1所述的半导体封装，其特征在于，所述的图案化栅极连接与该图案化源极连接是分别焊接至金属化栅极区域和金属化源极区域的。
6.如权利要求1所述的半导体封装，其特征在于，所述的图案化栅极连接在其一端包括一勾部。
7.如权利要求1所述的半导体封装，其特征在于，所述的图案化栅极连接在其一端包括一平面部。
8.如权利要求1所述的半导体封装，其特征在于，所述的金属化源极与栅极区域包括圆形金属化区域，其透过保护区域绝缘。
9.如权利要求1所述的半导体封装，其特征在于，所述的金属化源极与栅极区域包括一上方镍/金层。
10.如权利要求1所述的半导体封装，其特征在于，所述的漏极区域包括一金属化漏极区域。
11.如权利要求10所述的半导体封装，其特征在于，所述的金属化漏极区域包括一上方镍/金层。
12.如权利要求1所述的半导体封装，其特征在于，所述的漏极引线的底面部份曝露在该封装体外面。
13.一种半导体封装，其特征在于，包括：
一导线架，其具有漏极、源极与栅极引脚；
一半导体晶粒，其耦合该导线架，该半导体晶粒具有镍/金金属化源极与栅极区域；
一图案化源极连接，其耦合该源极引脚至该半导体晶粒金属化源极区域，该图案化源极连接焊接至该半导体晶粒金属化源极区域；
一图案化栅极连接单元，其耦合该栅极引脚至该半导体晶粒金属化栅极区域，该图案化栅极连接焊接至该半导体晶粒金属化栅极区域；
一半导体晶粒漏极区域，其耦合至该漏极引脚；以及
一封装体，其覆盖该半导体晶粒及该漏极、源极与栅极引脚的至少一部分。
14.如权利要求13所述的半导体封装，其特征在于，所述的图案化源极连接的一部份是曝露在该封装体外面的。
15.如权利要求13所述的半导体封装，其特征在于，所述的图案化栅极连接包括一开口，通过该开口使得图案化栅极连接被焊接至金属化栅极区域。
16.如权利要求15所述的半导体封装，其特征在于，所述的焊料在该图案化栅极连接的顶部形成一固定组件。
17.一种半导体封装，其具有一栅极固定组件固定至一半导体晶粒金属化栅极保护区域，其特征在于，该半导体封装包括：
一导架线，其具有漏极、源极与栅极引脚；
一半导体晶粒，其耦合该导线架，该半导体晶粒具有金属化源极与栅极区域；
一源极固定组件，其耦合该源极引脚至该半导体晶粒金属化源极区域；
一半导体晶粒漏极区域，其耦合至该栅极引脚；
一封装体，其覆盖该半导体晶粒及该漏极、源极与栅极引脚的至少一部分；以及
其中藉由在该栅极固定组件中所形成的一孔洞，该栅极固定组件耦合该栅极引脚至该半导体晶粒金属化栅极区域。
18.如权利要求17所述的半导体封装，其特征在于，所述的图案化源极连接的一部份是曝露在该封装体外面的。
19.如权利要求17所述的半导体封装，其特征在于，所述的栅极固定组件与源极固定组件分别焊接至金属化栅极区域与金属化源极区域，且该栅极固定组件焊料形成固定组件。
20.如权利要求17所述的半导体封装，其特征在于，所述的金属化源极与栅极区域包括一上方镍/金层。
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