CN101228624B - 互连接触的干法回蚀 - Google Patents

互连接触的干法回蚀 Download PDF

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Publication number
CN101228624B
CN101228624B CN2006800270555A CN200680027055A CN101228624B CN 101228624 B CN101228624 B CN 101228624B CN 2006800270555 A CN2006800270555 A CN 2006800270555A CN 200680027055 A CN200680027055 A CN 200680027055A CN 101228624 B CN101228624 B CN 101228624B
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CN
China
Prior art keywords
electric conducting
conducting material
gas
fluoro
dielectric layer
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
CN2006800270555A
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English (en)
Chinese (zh)
Other versions
CN101228624A (zh
Inventor
W·布里尔利
S·格雷科
S·桑卡兰
T·斯坦达厄特
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International Business Machines Corp
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International Business Machines Corp
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Publication date
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Publication of CN101228624A publication Critical patent/CN101228624A/zh
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Publication of CN101228624B publication Critical patent/CN101228624B/zh
Expired - Fee Related legal-status Critical Current
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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/01—Manufacture or treatment
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/01—Manufacture or treatment
    • H10W20/071—Manufacture or treatment of dielectric parts thereof
    • H10W20/081—Manufacture or treatment of dielectric parts thereof by forming openings in the dielectric parts
    • H10W20/084—Manufacture or treatment of dielectric parts thereof by forming openings in the dielectric parts for dual-damascene structures
    • H10W20/085—Manufacture or treatment of dielectric parts thereof by forming openings in the dielectric parts for dual-damascene structures involving intermediate temporary filling with material
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D64/00—Electrodes of devices having potential barriers
    • H10D64/01—Manufacture or treatment
    • H10D64/011—Manufacture or treatment of electrodes ohmically coupled to a semiconductor
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P50/00—Etching of wafers, substrates or parts of devices
    • H10P50/20—Dry etching; Plasma etching; Reactive-ion etching
    • H10P50/26—Dry etching; Plasma etching; Reactive-ion etching of conductive or resistive materials
    • H10P50/264—Dry etching; Plasma etching; Reactive-ion etching of conductive or resistive materials by chemical means
    • H10P50/266—Dry etching; Plasma etching; Reactive-ion etching of conductive or resistive materials by chemical means by vapour etching only
    • H10P50/267—Dry etching; Plasma etching; Reactive-ion etching of conductive or resistive materials by chemical means by vapour etching only using plasmas
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P50/00—Etching of wafers, substrates or parts of devices
    • H10P50/20—Dry etching; Plasma etching; Reactive-ion etching
    • H10P50/28—Dry etching; Plasma etching; Reactive-ion etching of insulating materials
    • H10P50/282—Dry etching; Plasma etching; Reactive-ion etching of insulating materials of inorganic materials
    • H10P50/283—Dry etching; Plasma etching; Reactive-ion etching of insulating materials of inorganic materials by chemical means
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/01—Manufacture or treatment
    • H10W20/031—Manufacture or treatment of conductive parts of the interconnections
    • H10W20/032—Manufacture or treatment of conductive parts of the interconnections of conductive barrier, adhesion or liner layers
    • H10W20/033—Manufacture or treatment of conductive parts of the interconnections of conductive barrier, adhesion or liner layers in openings in dielectrics
    • H10W20/036—Manufacture or treatment of conductive parts of the interconnections of conductive barrier, adhesion or liner layers in openings in dielectrics the barrier, adhesion or liner layers being within a main fill metal
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/01—Manufacture or treatment
    • H10W20/031—Manufacture or treatment of conductive parts of the interconnections
    • H10W20/056—Manufacture or treatment of conductive parts of the interconnections by filling conductive material into holes, grooves or trenches
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/40—Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/40—Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes
    • H10W20/41—Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes characterised by their conductive parts
    • H10W20/42—Vias, e.g. via plugs
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/40—Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes
    • H10W20/45—Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes characterised by their insulating parts
    • H10W20/48—Insulating materials thereof

Landscapes

  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Drying Of Semiconductors (AREA)
  • Connections Effected By Soldering, Adhesion, Or Permanent Deformation (AREA)
  • Connections Arranged To Contact A Plurality Of Conductors (AREA)
  • Coupling Device And Connection With Printed Circuit (AREA)
CN2006800270555A 2005-08-08 2006-07-27 互连接触的干法回蚀 Expired - Fee Related CN101228624B (zh)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US11/161,538 US7323410B2 (en) 2005-08-08 2005-08-08 Dry etchback of interconnect contacts
US11/161,538 2005-08-08
PCT/EP2006/064757 WO2007017400A1 (en) 2005-08-08 2006-07-27 Dry etchback of interconnect contacts

Publications (2)

Publication Number Publication Date
CN101228624A CN101228624A (zh) 2008-07-23
CN101228624B true CN101228624B (zh) 2011-07-20

Family

ID=37074972

Family Applications (1)

Application Number Title Priority Date Filing Date
CN2006800270555A Expired - Fee Related CN101228624B (zh) 2005-08-08 2006-07-27 互连接触的干法回蚀

Country Status (9)

Country Link
US (2) US7323410B2 (https=)
EP (1) EP1922753B1 (https=)
JP (1) JP4742147B2 (https=)
KR (1) KR101027172B1 (https=)
CN (1) CN101228624B (https=)
AT (1) ATE504084T1 (https=)
DE (1) DE602006021035D1 (https=)
TW (1) TWI377618B (https=)
WO (1) WO2007017400A1 (https=)

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* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20070037316A1 (en) * 2005-08-09 2007-02-15 Micron Technology, Inc. Memory cell contact using spacers
US20070232048A1 (en) * 2006-03-31 2007-10-04 Koji Miyata Damascene interconnection having a SiCOH low k layer
US8399349B2 (en) 2006-04-18 2013-03-19 Air Products And Chemicals, Inc. Materials and methods of forming controlled void
US7947609B2 (en) * 2007-08-10 2011-05-24 Tokyo Electron Limited Method for etching low-k material using an oxide hard mask
US7935640B2 (en) * 2007-08-10 2011-05-03 Tokyo Electron Limited Method for forming a damascene structure
US8080473B2 (en) * 2007-08-29 2011-12-20 Tokyo Electron Limited Method for metallizing a pattern in a dielectric film
JP5102720B2 (ja) * 2008-08-25 2012-12-19 東京エレクトロン株式会社 基板処理方法
US8435901B2 (en) 2010-06-11 2013-05-07 Tokyo Electron Limited Method of selectively etching an insulation stack for a metal interconnect
KR102057855B1 (ko) 2013-11-13 2019-12-20 삼성전자 주식회사 반도체 소자 및 그 제조 방법
US9514977B2 (en) 2013-12-17 2016-12-06 Kabushiki Kaisha Toshiba Semiconductor device and manufacturing method thereof
US9484401B2 (en) 2014-11-24 2016-11-01 International Business Machines Corporation Capacitance reduction for advanced technology nodes
US9679807B1 (en) * 2015-11-20 2017-06-13 Globalfoundries Inc. Method, apparatus, and system for MOL interconnects without titanium liner

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US4808552A (en) * 1985-09-11 1989-02-28 Texas Instruments Incorporated Process for making vertically-oriented interconnections for VLSI devices
US4793897A (en) * 1987-03-20 1988-12-27 Applied Materials, Inc. Selective thin film etch process
US5244534A (en) * 1992-01-24 1993-09-14 Micron Technology, Inc. Two-step chemical mechanical polishing process for producing flush and protruding tungsten plugs
US5300813A (en) 1992-02-26 1994-04-05 International Business Machines Corporation Refractory metal capped low resistivity metal conductor lines and vias
JPH05267241A (ja) * 1992-03-18 1993-10-15 Fujitsu Ltd 半導体装置の製造方法
DE69213928T2 (de) * 1992-05-27 1997-03-13 Sgs Thomson Microelectronics Verdrahtung auf Wolfram-Plomben
JPH06260441A (ja) * 1993-03-03 1994-09-16 Nec Corp 半導体装置の製造方法
US5413670A (en) * 1993-07-08 1995-05-09 Air Products And Chemicals, Inc. Method for plasma etching or cleaning with diluted NF3
FR2754391B1 (fr) * 1996-10-08 1999-04-16 Sgs Thomson Microelectronics Structure de contact a facteur de forme eleve pour circuits integres
US5970374A (en) 1996-10-18 1999-10-19 Chartered Semiconductor Manufacturing Ltd. Method for forming contacts and vias with improved barrier metal step-coverage
JPH10242271A (ja) * 1997-02-28 1998-09-11 Sony Corp 半導体装置及びその製造方法
US6043163A (en) * 1997-12-29 2000-03-28 Taiwan Semiconductor Manufacturing Company, Ltd. HCL in overetch with hard mask to improve metal line etching profile
WO1999050903A1 (fr) * 1998-03-30 1999-10-07 Hitachi, Ltd. Circuit integre a semi-conducteur et procede de fabrication correspondant
TW377502B (en) * 1998-05-26 1999-12-21 United Microelectronics Corp Method of dual damascene
JP4809961B2 (ja) * 1998-08-07 2011-11-09 株式会社東芝 半導体装置及びその製造方法
US6040243A (en) * 1999-09-20 2000-03-21 Chartered Semiconductor Manufacturing Ltd. Method to form copper damascene interconnects using a reverse barrier metal scheme to eliminate copper diffusion
JP3400770B2 (ja) * 1999-11-16 2003-04-28 松下電器産業株式会社 エッチング方法、半導体装置及びその製造方法
US6534389B1 (en) * 2000-03-09 2003-03-18 International Business Machines Corporation Dual level contacts and method for forming
US6753249B1 (en) * 2001-01-16 2004-06-22 Taiwan Semiconductor Manufacturing Company Multilayer interface in copper CMP for low K dielectric
US6566242B1 (en) * 2001-03-23 2003-05-20 International Business Machines Corporation Dual damascene copper interconnect to a damascene tungsten wiring level
US6426558B1 (en) * 2001-05-14 2002-07-30 International Business Machines Corporation Metallurgy for semiconductor devices
US20020171147A1 (en) * 2001-05-15 2002-11-21 Tri-Rung Yew Structure of a dual damascene via
JP2003068848A (ja) * 2001-08-29 2003-03-07 Fujitsu Ltd 半導体装置及びその製造方法
TW544916B (en) * 2002-01-10 2003-08-01 Winbond Electronics Corp Memory device having complex type contact plug and its manufacturing method
US6867073B1 (en) * 2003-10-21 2005-03-15 Ziptronix, Inc. Single mask via method and device
US7030468B2 (en) * 2004-01-16 2006-04-18 International Business Machines Corporation Low k and ultra low k SiCOH dielectric films and methods to form the same

Also Published As

Publication number Publication date
CN101228624A (zh) 2008-07-23
US7645700B2 (en) 2010-01-12
US20080088027A1 (en) 2008-04-17
EP1922753A1 (en) 2008-05-21
DE602006021035D1 (de) 2011-05-12
JP2009505385A (ja) 2009-02-05
US7323410B2 (en) 2008-01-29
WO2007017400A1 (en) 2007-02-15
KR101027172B1 (ko) 2011-04-05
US20070032055A1 (en) 2007-02-08
ATE504084T1 (de) 2011-04-15
JP4742147B2 (ja) 2011-08-10
EP1922753B1 (en) 2011-03-30
KR20080033300A (ko) 2008-04-16
TWI377618B (en) 2012-11-21
TW200741849A (en) 2007-11-01

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Effective date of registration: 20161229

Address after: The United States Delaware

Patentee after: Globalfoundries second American LLC

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Patentee before: International Business Machines Corp.

Effective date of registration: 20161229

Address after: Cayman Islands Grand Cayman

Patentee after: INTERNATIONAL BUSINESS MACHINES Corp.

Address before: The United States Delaware

Patentee before: Globalfoundries second American LLC

TR01 Transfer of patent right
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Effective date of registration: 20180328

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Patentee after: International Business Machines Corp.

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Patentee before: INTERNATIONAL BUSINESS MACHINES Corp.

CF01 Termination of patent right due to non-payment of annual fee
CF01 Termination of patent right due to non-payment of annual fee

Granted publication date: 20110720

Termination date: 20210727