KR101027172B1 - 인터커넥트 컨택트의 건식 에치백 - Google Patents

인터커넥트 컨택트의 건식 에치백 Download PDF

Info

Publication number
KR101027172B1
KR101027172B1 KR1020087002079A KR20087002079A KR101027172B1 KR 101027172 B1 KR101027172 B1 KR 101027172B1 KR 1020087002079 A KR1020087002079 A KR 1020087002079A KR 20087002079 A KR20087002079 A KR 20087002079A KR 101027172 B1 KR101027172 B1 KR 101027172B1
Authority
KR
South Korea
Prior art keywords
conductive material
providing
layer
contact
tungsten
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
KR1020087002079A
Other languages
English (en)
Korean (ko)
Other versions
KR20080033300A (ko
Inventor
윌리암 브리어리
스테펜 그레코
수자타 산카란
테도루스 스탄다에르트
Original Assignee
인터내셔널 비지네스 머신즈 코포레이션
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 인터내셔널 비지네스 머신즈 코포레이션 filed Critical 인터내셔널 비지네스 머신즈 코포레이션
Publication of KR20080033300A publication Critical patent/KR20080033300A/ko
Application granted granted Critical
Publication of KR101027172B1 publication Critical patent/KR101027172B1/ko
Expired - Fee Related legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Images

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/01—Manufacture or treatment
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/01—Manufacture or treatment
    • H10W20/071—Manufacture or treatment of dielectric parts thereof
    • H10W20/081—Manufacture or treatment of dielectric parts thereof by forming openings in the dielectric parts
    • H10W20/084—Manufacture or treatment of dielectric parts thereof by forming openings in the dielectric parts for dual-damascene structures
    • H10W20/085—Manufacture or treatment of dielectric parts thereof by forming openings in the dielectric parts for dual-damascene structures involving intermediate temporary filling with material
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D64/00—Electrodes of devices having potential barriers
    • H10D64/01—Manufacture or treatment
    • H10D64/011—Manufacture or treatment of electrodes ohmically coupled to a semiconductor
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P50/00—Etching of wafers, substrates or parts of devices
    • H10P50/20—Dry etching; Plasma etching; Reactive-ion etching
    • H10P50/26—Dry etching; Plasma etching; Reactive-ion etching of conductive or resistive materials
    • H10P50/264—Dry etching; Plasma etching; Reactive-ion etching of conductive or resistive materials by chemical means
    • H10P50/266—Dry etching; Plasma etching; Reactive-ion etching of conductive or resistive materials by chemical means by vapour etching only
    • H10P50/267—Dry etching; Plasma etching; Reactive-ion etching of conductive or resistive materials by chemical means by vapour etching only using plasmas
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P50/00—Etching of wafers, substrates or parts of devices
    • H10P50/20—Dry etching; Plasma etching; Reactive-ion etching
    • H10P50/28—Dry etching; Plasma etching; Reactive-ion etching of insulating materials
    • H10P50/282—Dry etching; Plasma etching; Reactive-ion etching of insulating materials of inorganic materials
    • H10P50/283—Dry etching; Plasma etching; Reactive-ion etching of insulating materials of inorganic materials by chemical means
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/01—Manufacture or treatment
    • H10W20/031—Manufacture or treatment of conductive parts of the interconnections
    • H10W20/032—Manufacture or treatment of conductive parts of the interconnections of conductive barrier, adhesion or liner layers
    • H10W20/033—Manufacture or treatment of conductive parts of the interconnections of conductive barrier, adhesion or liner layers in openings in dielectrics
    • H10W20/036—Manufacture or treatment of conductive parts of the interconnections of conductive barrier, adhesion or liner layers in openings in dielectrics the barrier, adhesion or liner layers being within a main fill metal
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/01—Manufacture or treatment
    • H10W20/031—Manufacture or treatment of conductive parts of the interconnections
    • H10W20/056—Manufacture or treatment of conductive parts of the interconnections by filling conductive material into holes, grooves or trenches
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/40—Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/40—Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes
    • H10W20/41—Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes characterised by their conductive parts
    • H10W20/42—Vias, e.g. via plugs
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/40—Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes
    • H10W20/45—Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes characterised by their insulating parts
    • H10W20/48—Insulating materials thereof

Landscapes

  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Drying Of Semiconductors (AREA)
  • Connections Effected By Soldering, Adhesion, Or Permanent Deformation (AREA)
  • Connections Arranged To Contact A Plurality Of Conductors (AREA)
  • Coupling Device And Connection With Printed Circuit (AREA)
KR1020087002079A 2005-08-08 2006-07-27 인터커넥트 컨택트의 건식 에치백 Expired - Fee Related KR101027172B1 (ko)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US11/161,538 US7323410B2 (en) 2005-08-08 2005-08-08 Dry etchback of interconnect contacts
US11/161,538 2005-08-08

Publications (2)

Publication Number Publication Date
KR20080033300A KR20080033300A (ko) 2008-04-16
KR101027172B1 true KR101027172B1 (ko) 2011-04-05

Family

ID=37074972

Family Applications (1)

Application Number Title Priority Date Filing Date
KR1020087002079A Expired - Fee Related KR101027172B1 (ko) 2005-08-08 2006-07-27 인터커넥트 컨택트의 건식 에치백

Country Status (9)

Country Link
US (2) US7323410B2 (https=)
EP (1) EP1922753B1 (https=)
JP (1) JP4742147B2 (https=)
KR (1) KR101027172B1 (https=)
CN (1) CN101228624B (https=)
AT (1) ATE504084T1 (https=)
DE (1) DE602006021035D1 (https=)
TW (1) TWI377618B (https=)
WO (1) WO2007017400A1 (https=)

Families Citing this family (12)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20070037316A1 (en) * 2005-08-09 2007-02-15 Micron Technology, Inc. Memory cell contact using spacers
US20070232048A1 (en) * 2006-03-31 2007-10-04 Koji Miyata Damascene interconnection having a SiCOH low k layer
US8399349B2 (en) 2006-04-18 2013-03-19 Air Products And Chemicals, Inc. Materials and methods of forming controlled void
US7947609B2 (en) * 2007-08-10 2011-05-24 Tokyo Electron Limited Method for etching low-k material using an oxide hard mask
US7935640B2 (en) * 2007-08-10 2011-05-03 Tokyo Electron Limited Method for forming a damascene structure
US8080473B2 (en) * 2007-08-29 2011-12-20 Tokyo Electron Limited Method for metallizing a pattern in a dielectric film
JP5102720B2 (ja) * 2008-08-25 2012-12-19 東京エレクトロン株式会社 基板処理方法
US8435901B2 (en) 2010-06-11 2013-05-07 Tokyo Electron Limited Method of selectively etching an insulation stack for a metal interconnect
KR102057855B1 (ko) 2013-11-13 2019-12-20 삼성전자 주식회사 반도체 소자 및 그 제조 방법
US9514977B2 (en) 2013-12-17 2016-12-06 Kabushiki Kaisha Toshiba Semiconductor device and manufacturing method thereof
US9484401B2 (en) 2014-11-24 2016-11-01 International Business Machines Corporation Capacitance reduction for advanced technology nodes
US9679807B1 (en) * 2015-11-20 2017-06-13 Globalfoundries Inc. Method, apparatus, and system for MOL interconnects without titanium liner

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5970374A (en) 1996-10-18 1999-10-19 Chartered Semiconductor Manufacturing Ltd. Method for forming contacts and vias with improved barrier metal step-coverage
EP0966037A2 (en) 1992-02-26 1999-12-22 International Business Machines Corporation Refractory metal capped low resistivity metal conductor lines and vias formed using PVD and CVD
US20030127708A1 (en) 2002-01-10 2003-07-10 Wen-Chung Liu Memory device with composite contact plug and method for manufacturing the same
US20040106297A1 (en) * 2000-04-19 2004-06-03 Matsushita Electric Industrial Co., Ltd. Etching method, semiconductor and fabricating method for the same

Family Cites Families (22)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4808552A (en) * 1985-09-11 1989-02-28 Texas Instruments Incorporated Process for making vertically-oriented interconnections for VLSI devices
US4793897A (en) * 1987-03-20 1988-12-27 Applied Materials, Inc. Selective thin film etch process
US5244534A (en) * 1992-01-24 1993-09-14 Micron Technology, Inc. Two-step chemical mechanical polishing process for producing flush and protruding tungsten plugs
JPH05267241A (ja) * 1992-03-18 1993-10-15 Fujitsu Ltd 半導体装置の製造方法
DE69213928T2 (de) * 1992-05-27 1997-03-13 Sgs Thomson Microelectronics Verdrahtung auf Wolfram-Plomben
JPH06260441A (ja) * 1993-03-03 1994-09-16 Nec Corp 半導体装置の製造方法
US5413670A (en) * 1993-07-08 1995-05-09 Air Products And Chemicals, Inc. Method for plasma etching or cleaning with diluted NF3
FR2754391B1 (fr) * 1996-10-08 1999-04-16 Sgs Thomson Microelectronics Structure de contact a facteur de forme eleve pour circuits integres
JPH10242271A (ja) * 1997-02-28 1998-09-11 Sony Corp 半導体装置及びその製造方法
US6043163A (en) * 1997-12-29 2000-03-28 Taiwan Semiconductor Manufacturing Company, Ltd. HCL in overetch with hard mask to improve metal line etching profile
WO1999050903A1 (fr) * 1998-03-30 1999-10-07 Hitachi, Ltd. Circuit integre a semi-conducteur et procede de fabrication correspondant
TW377502B (en) * 1998-05-26 1999-12-21 United Microelectronics Corp Method of dual damascene
JP4809961B2 (ja) * 1998-08-07 2011-11-09 株式会社東芝 半導体装置及びその製造方法
US6040243A (en) * 1999-09-20 2000-03-21 Chartered Semiconductor Manufacturing Ltd. Method to form copper damascene interconnects using a reverse barrier metal scheme to eliminate copper diffusion
US6534389B1 (en) * 2000-03-09 2003-03-18 International Business Machines Corporation Dual level contacts and method for forming
US6753249B1 (en) * 2001-01-16 2004-06-22 Taiwan Semiconductor Manufacturing Company Multilayer interface in copper CMP for low K dielectric
US6566242B1 (en) * 2001-03-23 2003-05-20 International Business Machines Corporation Dual damascene copper interconnect to a damascene tungsten wiring level
US6426558B1 (en) * 2001-05-14 2002-07-30 International Business Machines Corporation Metallurgy for semiconductor devices
US20020171147A1 (en) * 2001-05-15 2002-11-21 Tri-Rung Yew Structure of a dual damascene via
JP2003068848A (ja) * 2001-08-29 2003-03-07 Fujitsu Ltd 半導体装置及びその製造方法
US6867073B1 (en) * 2003-10-21 2005-03-15 Ziptronix, Inc. Single mask via method and device
US7030468B2 (en) * 2004-01-16 2006-04-18 International Business Machines Corporation Low k and ultra low k SiCOH dielectric films and methods to form the same

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0966037A2 (en) 1992-02-26 1999-12-22 International Business Machines Corporation Refractory metal capped low resistivity metal conductor lines and vias formed using PVD and CVD
US5970374A (en) 1996-10-18 1999-10-19 Chartered Semiconductor Manufacturing Ltd. Method for forming contacts and vias with improved barrier metal step-coverage
US20040106297A1 (en) * 2000-04-19 2004-06-03 Matsushita Electric Industrial Co., Ltd. Etching method, semiconductor and fabricating method for the same
US20030127708A1 (en) 2002-01-10 2003-07-10 Wen-Chung Liu Memory device with composite contact plug and method for manufacturing the same

Also Published As

Publication number Publication date
CN101228624A (zh) 2008-07-23
US7645700B2 (en) 2010-01-12
US20080088027A1 (en) 2008-04-17
EP1922753A1 (en) 2008-05-21
DE602006021035D1 (de) 2011-05-12
JP2009505385A (ja) 2009-02-05
US7323410B2 (en) 2008-01-29
WO2007017400A1 (en) 2007-02-15
US20070032055A1 (en) 2007-02-08
ATE504084T1 (de) 2011-04-15
JP4742147B2 (ja) 2011-08-10
CN101228624B (zh) 2011-07-20
EP1922753B1 (en) 2011-03-30
KR20080033300A (ko) 2008-04-16
TWI377618B (en) 2012-11-21
TW200741849A (en) 2007-11-01

Similar Documents

Publication Publication Date Title
US7645700B2 (en) Dry etchback of interconnect contacts
US7871923B2 (en) Self-aligned air-gap in interconnect structures
US6713402B2 (en) Methods for polymer removal following etch-stop layer etch
US7629264B2 (en) Structure and method for hybrid tungsten copper metal contact
US20090170221A1 (en) Etch residue reduction by ash methodology
US20070120263A1 (en) Conductor track arrangement and associated production method
US20090087992A1 (en) Method of minimizing via sidewall damages during dual damascene trench reactive ion etching in a via first scheme
US20030181034A1 (en) Methods for forming vias and trenches with controlled SiC etch rate and selectivity
JP2012235124A (ja) 半導体装置の製造方法
KR20000026588A (ko) 콘택홀을 갖는 반도체 장치 및 그 제조방법
US6900123B2 (en) BARC etch comprising a selective etch chemistry and a high polymerizing gas for CD control
US7265450B2 (en) Semiconductor device and method for fabricating the same
US11569127B2 (en) Double patterning approach by direct metal etch
US7541271B2 (en) MOS transistors having low-resistance salicide gates and a self-aligned contact between them and method of manufacture
CN101308809A (zh) 铝导线的制作方法
CN113097127B (zh) 半导体结构的形成方法
JP2005005697A (ja) 半導体装置の製造方法
KR100641980B1 (ko) 반도체 소자의 배선 및 그 형성방법
KR100752174B1 (ko) 2개의 시드층을 이용한 반도체 소자의 구리 배선 형성 방법
TWI512894B (zh) 金屬內連線結構及其製程
KR101024871B1 (ko) 듀얼 다마신 패턴 형성 방법
KR100711926B1 (ko) 반도체 소자의 제조 방법
KR20010025972A (ko) 반도체 장치의 배선 형성방법
KR100928107B1 (ko) 반도체 소자 및 그 제조 방법
KR20070052452A (ko) 반도체 소자의 금속배선 제조방법

Legal Events

Date Code Title Description
PA0105 International application

St.27 status event code: A-0-1-A10-A15-nap-PA0105

PG1501 Laying open of application

St.27 status event code: A-1-1-Q10-Q12-nap-PG1501

A201 Request for examination
P11-X000 Amendment of application requested

St.27 status event code: A-2-2-P10-P11-nap-X000

P13-X000 Application amended

St.27 status event code: A-2-2-P10-P13-nap-X000

PA0201 Request for examination

St.27 status event code: A-1-2-D10-D11-exm-PA0201

R18-X000 Changes to party contact information recorded

St.27 status event code: A-3-3-R10-R18-oth-X000

R18-X000 Changes to party contact information recorded

St.27 status event code: A-3-3-R10-R18-oth-X000

E902 Notification of reason for refusal
PE0902 Notice of grounds for rejection

St.27 status event code: A-1-2-D10-D21-exm-PE0902

E13-X000 Pre-grant limitation requested

St.27 status event code: A-2-3-E10-E13-lim-X000

P11-X000 Amendment of application requested

St.27 status event code: A-2-2-P10-P11-nap-X000

P13-X000 Application amended

St.27 status event code: A-2-2-P10-P13-nap-X000

E701 Decision to grant or registration of patent right
PE0701 Decision of registration

St.27 status event code: A-1-2-D10-D22-exm-PE0701

GRNT Written decision to grant
PR0701 Registration of establishment

St.27 status event code: A-2-4-F10-F11-exm-PR0701

PR1002 Payment of registration fee

St.27 status event code: A-2-2-U10-U12-oth-PR1002

Fee payment year number: 1

PG1601 Publication of registration

St.27 status event code: A-4-4-Q10-Q13-nap-PG1601

LAPS Lapse due to unpaid annual fee
PC1903 Unpaid annual fee

St.27 status event code: A-4-4-U10-U13-oth-PC1903

Not in force date: 20140330

Payment event data comment text: Termination Category : DEFAULT_OF_REGISTRATION_FEE

PC1903 Unpaid annual fee

St.27 status event code: N-4-6-H10-H13-oth-PC1903

Ip right cessation event data comment text: Termination Category : DEFAULT_OF_REGISTRATION_FEE

Not in force date: 20140330

P22-X000 Classification modified

St.27 status event code: A-4-4-P10-P22-nap-X000