WO2007017400A1 - Dry etchback of interconnect contacts - Google Patents

Dry etchback of interconnect contacts Download PDF

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Publication number
WO2007017400A1
WO2007017400A1 PCT/EP2006/064757 EP2006064757W WO2007017400A1 WO 2007017400 A1 WO2007017400 A1 WO 2007017400A1 EP 2006064757 W EP2006064757 W EP 2006064757W WO 2007017400 A1 WO2007017400 A1 WO 2007017400A1
Authority
WO
WIPO (PCT)
Prior art keywords
conductive material
containing gas
approximately
providing
fluorine containing
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Ceased
Application number
PCT/EP2006/064757
Other languages
English (en)
French (fr)
Inventor
William Brearley
Stephen Greco
Sujatha Sankaran
Theodorus Standaert
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
IBM United Kingdom Ltd
International Business Machines Corp
Original Assignee
IBM United Kingdom Ltd
International Business Machines Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by IBM United Kingdom Ltd, International Business Machines Corp filed Critical IBM United Kingdom Ltd
Priority to DE602006021035T priority Critical patent/DE602006021035D1/de
Priority to JP2008525532A priority patent/JP4742147B2/ja
Priority to CN2006800270555A priority patent/CN101228624B/zh
Priority to EP06778036A priority patent/EP1922753B1/en
Priority to AT06778036T priority patent/ATE504084T1/de
Publication of WO2007017400A1 publication Critical patent/WO2007017400A1/en
Anticipated expiration legal-status Critical
Ceased legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/01—Manufacture or treatment
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/01—Manufacture or treatment
    • H10W20/071—Manufacture or treatment of dielectric parts thereof
    • H10W20/081—Manufacture or treatment of dielectric parts thereof by forming openings in the dielectric parts
    • H10W20/084—Manufacture or treatment of dielectric parts thereof by forming openings in the dielectric parts for dual-damascene structures
    • H10W20/085—Manufacture or treatment of dielectric parts thereof by forming openings in the dielectric parts for dual-damascene structures involving intermediate temporary filling with material
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D64/00—Electrodes of devices having potential barriers
    • H10D64/01—Manufacture or treatment
    • H10D64/011—Manufacture or treatment of electrodes ohmically coupled to a semiconductor
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P50/00—Etching of wafers, substrates or parts of devices
    • H10P50/20—Dry etching; Plasma etching; Reactive-ion etching
    • H10P50/26—Dry etching; Plasma etching; Reactive-ion etching of conductive or resistive materials
    • H10P50/264—Dry etching; Plasma etching; Reactive-ion etching of conductive or resistive materials by chemical means
    • H10P50/266—Dry etching; Plasma etching; Reactive-ion etching of conductive or resistive materials by chemical means by vapour etching only
    • H10P50/267—Dry etching; Plasma etching; Reactive-ion etching of conductive or resistive materials by chemical means by vapour etching only using plasmas
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P50/00—Etching of wafers, substrates or parts of devices
    • H10P50/20—Dry etching; Plasma etching; Reactive-ion etching
    • H10P50/28—Dry etching; Plasma etching; Reactive-ion etching of insulating materials
    • H10P50/282—Dry etching; Plasma etching; Reactive-ion etching of insulating materials of inorganic materials
    • H10P50/283—Dry etching; Plasma etching; Reactive-ion etching of insulating materials of inorganic materials by chemical means
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/01—Manufacture or treatment
    • H10W20/031—Manufacture or treatment of conductive parts of the interconnections
    • H10W20/032—Manufacture or treatment of conductive parts of the interconnections of conductive barrier, adhesion or liner layers
    • H10W20/033—Manufacture or treatment of conductive parts of the interconnections of conductive barrier, adhesion or liner layers in openings in dielectrics
    • H10W20/036—Manufacture or treatment of conductive parts of the interconnections of conductive barrier, adhesion or liner layers in openings in dielectrics the barrier, adhesion or liner layers being within a main fill metal
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/01—Manufacture or treatment
    • H10W20/031—Manufacture or treatment of conductive parts of the interconnections
    • H10W20/056—Manufacture or treatment of conductive parts of the interconnections by filling conductive material into holes, grooves or trenches
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/40—Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/40—Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes
    • H10W20/41—Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes characterised by their conductive parts
    • H10W20/42—Vias, e.g. via plugs
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/40—Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes
    • H10W20/45—Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes characterised by their insulating parts
    • H10W20/48—Insulating materials thereof

Definitions

  • the present invention is directed to the manufacture of semiconductor devices and particularly to the manufacture of metallurgy for integrated circuit devices.
  • This invention relates to the formation of metallurgical interconnects for semiconductor devices, and particularly to the formation of contacts formed at the semiconductor surface which interface with metallurgy formed of copper-based metals.
  • local interconnect trenches are etched into a first insulating layer deposited on top of a substrate having active devices.
  • the etched trenches are filled with a liner/tungsten core to make contact with some portions of the substrate devices and polished to be coplanar with the first insulating layer to form the local interconnect (MC) .
  • a second insulating layer is deposited and stud contact holes etched into it.
  • the etched stud contact holes are filled with a liner/tungsten core and polished to be coplanar with a second insulating layer forming the stud contacts (CA) imbedded in the insulating layer which make contact with the local interconnect (MC) and also with additional portions of the devices.
  • the first wiring level (Ml) is then formed by either a deposition and subtractive etch or by a damascene process requiring a third layer. This Ml wiring level makes contact with the stud contacts (CA) .
  • a first aspect of the present invention provides a method of making an electronic device comprising the steps of providing a substrate on which contacts are to be formed; providing a conductive via comprised of a first conductive material formed in an oxide on the substrate; providing a dielectric layer on the conductive via; providing an oxide layer on the dielectric layer; providing a photoresist layer on the oxide layer; forming openings in the photoresist layer; removing the photoresist layer and removing in the openings the dielectric layer and the oxide layer and at least a portion of the first conductive material with a fluorine containing gas; and depositing a second conductive material in the openings to form a composite conductive via comprising the first conductive material and the second conductive material.
  • the present invention can ameliorate the problem of increasing CA
  • the invention can also provide a more reliable contact than in some known devices.
  • the fluorine containing gas is preferably NF 3 , F 2 or SF 6 .
  • the dielectric layer is a low-K SiCOH material.
  • the low-K SiCOH material may be a porous ultra low-K material.
  • the first conductive material is Tungsten and the second conductive material is Copper.
  • the fluorine containing gas comprises approximately 500 seem of Argon and approximately 50 seem of NF 3 .
  • the fluorine containing gas may further comprise approximately 10 seem O 2 and 50 seem of CH 2 F 2 or CH 3 F at a pressure of approximately 100 mTorr to approximately 200 mTorr.
  • a second aspect of the invention provides a method of making an electronic device comprising the steps of: providing a substrate on which contacts are to be formed; providing a conductive via comprised of a first conductive material formed in an oxide on the substrate; providing a dielectric layer on the conductive via; providing an oxide layer on the dielectric layer; providing a photoresist layer on the oxide layer; forming openings in the photoresist layer; removing in the openings the dielectric layer and the oxide layer with a fluorocarbon containing gas; removing the photoresist layer; removing at least a portion of the first conductive material in the openings with a fluorine containing gas; and depositing a second conductive material in the openings to form a composite conductive via comprising the first conductive material and the second conductive material .
  • Another aspect of the invention provides a method of making an electronic device comprising the steps of: providing a substrate on which contacts are to be formed; providing a conductive via comprised of a first conductive material formed in an oxide on the substrate; providing a dielectric layer on the conductive via; providing an oxide layer on the dielectric layer; providing a photoresist layer on the oxide layer; forming openings in the photoresist layer; removing in the openings the dielectric layer and the oxide layer with a fluorocarbon containing gas; removing the photoresist layer and removing in the openings a portion of the first conductive material with a fluorine containing gas; depositing a second conductive material in the openings to form a composite conductive via comprising the first conductive material and the second conductive material.
  • the invention further provides, in another aspect, an electronic device comprising: a poly-silicon gate formed on a substrate; a composite stud via structure in contact with the poly-silicon gate, the composite stud via structure having a first portion and a second portion.
  • the first portion is comprised of Tungsten and the second portion is comprised of Copper.
  • the composite stud via structure is approximately 100 nanometers in width and approximately 2,000 angstroms in height. The first portion is approximately 500 angstroms in height.
  • Figures 1 - 5 illustrate a conventional process for forming a stud contact interconnect
  • Figures 6 - 9 illustrate a method for forming a stud contact interconnect according to the present invention.
  • the present invention reduces the CA contact resistance by partially dry-etching back the tungsten CA contact after or during the Ml RIE process. The recessed CA contact is then subsequently metalized during the Ml liner/plating process. The present invention reduces the tungsten CA height after it has been fully formed. Reducing the CA height will have a significant impact on the CA contact resistance.
  • SiCOH material with a TEOS (Tetraethyl Orthosilicate, Si (OC 2 H 5 ) 4 ) hard mask (HM).
  • TEOS Tetraethyl Orthosilicate, Si (OC 2 H 5 ) 4
  • HM hard mask
  • SiCOH etch chemistry is NF3 based which is expected to readily etch W.
  • the present invention discloses the etchback in the dielectric etch of Ml in order to lower the resistance of the tungsten contact.
  • the recess of the tungsten is not a problem for subsequent metallization since the invention uses conventional liner/seed/plating processes that can reliably fill high aspect ratio features.
  • a conductive via (CA) 15 in an oxide 20 there is shown a conductive via (CA) 15 in an oxide 20.
  • the conductive material will be Tungsten (W) .
  • the next level metal wires can now be created by a conventional damascene process which starts out with the deposition of a low-k dielectric film (Ml dielectric) 30 followed by the deposition of an oxide hardmask (Ml Hardmask) 40 and Ml photoresist 50.
  • FIG. 3 there is shown the transfer of the Ml line pattern 60 into the dielectric 30 by Reactive Ion Etching (RIE) including a resist strip.
  • RIE Reactive Ion Etching
  • Figure 4 there is shown the conventional processing step of liner/seed/plating to form liner 70 and Ml wiring metal 80.
  • Figure 5 there is shown the last conventional processing step of CMP to form the Ml wiring 90.
  • the present invention can be used with the same dielectric deposition steps of the low-k material 30 and oxide hardmask 40, followed by the same lithography step as illustrated in Figure 2.
  • the present invention deviates from the known art either during or after the RIE step.
  • a first embodiment of the present invention is to use a fluorine containing gas (but not a fluorocarbon based gas) such as NF3, F2 or SF6 to selectively etch the low-k dielectric 30 to oxide 20.
  • a fluorine containing gas such as NF3, F2 or SF6
  • the low-k dielectric 30 is a SiCOH-like material, and could be a porous-ULK material.
  • the resist selectivity during this RIE step will be low and the critical dimension (CD) control in this case is provided by the oxide hardmask 40 which exhibits a low etch rate in these fluorine-based chemistries.
  • the fluorine based chemistry can also etch the CA tungsten 15 as well as the CA liner 10. Therefore, the low-k over etch can be used to recess the CA tungsten via to the desired depth. Since the etch rate of resist is high in these chemistries, it can be completely consumed before or during the low-k over etch and no additional resist strip is required.
  • This selective Ml RIE process is compatible with conventional etch tools such as parallel plate and medium density plasma RIE tools.
  • the etch gases comprise approximately 500 seem of Ar and approximately 50 seem of NF 3 .
  • small amounts of O2 and CH 2 F 2 or CH 3 F may be added.
  • the latter additions can help maintain the critical dimensions or increase the selectivity to the oxide hardmask or resist.
  • the pressure is approximately 100 to 200 mTorr with a power of about 500W for both 27 and 2 MHz frequencies.
  • Another embodiment of the present invention is to follow known art after the lithography step.
  • fluorine-based chemistry NF3, F2, SF6
  • the known art is followed after the lithography step.
  • the next step would be to recess the CA tungsten 15 and liner 10 which also strips the remaining photoresist materials 50.
  • Figure 6 shows the final results in cross section.
  • Figure 7 shows a top-down view for these three embodiments illustrating the partially exposed CA tungsten 15 and liner 10 in the recessed trench formed in the low-k dielectric 30 and oxide hardmask 40.
  • the metallization of this structure is achieved by the known art discussed above.
  • the CA stud interconnect is now a composite structure of two conductive materials.
  • the conductive materials are Tungsten and Copper.
  • the composite stud structure is approximately 100 nanometers in width and approximately 2,000 angstroms in height and the Tungsten portion is approximately 500 angstroms in height.
  • This composite CA stud contact will have a lower contact resistance than a conventional contact.
  • a 2,000 angstrom high and 95nm wide conventional Tungsten CA stud has an estimated contact resistance of 19 ohms. Approximately a third of this resistance is from W conductivity. If the Tungsten CA is etch backed to a 500 angstrom height, the contact resistance will drop from 19 to 13 ohms.
  • Another advantage is that the contact area between any misaligned (and recessed) CA stud and the Ml line is increased. Besides a lower contact resistance between the copper line and the CA stud, this also provides a more reliable contact.

Landscapes

  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Drying Of Semiconductors (AREA)
  • Connections Effected By Soldering, Adhesion, Or Permanent Deformation (AREA)
  • Connections Arranged To Contact A Plurality Of Conductors (AREA)
  • Coupling Device And Connection With Printed Circuit (AREA)
PCT/EP2006/064757 2005-08-08 2006-07-27 Dry etchback of interconnect contacts Ceased WO2007017400A1 (en)

Priority Applications (5)

Application Number Priority Date Filing Date Title
DE602006021035T DE602006021035D1 (de) 2005-08-08 2006-07-27 Trocken-rückätzen von verbindungskontakten
JP2008525532A JP4742147B2 (ja) 2005-08-08 2006-07-27 相互接続コンタクトのドライ・エッチバック
CN2006800270555A CN101228624B (zh) 2005-08-08 2006-07-27 互连接触的干法回蚀
EP06778036A EP1922753B1 (en) 2005-08-08 2006-07-27 Dry etchback of interconnect contacts
AT06778036T ATE504084T1 (de) 2005-08-08 2006-07-27 Trocken-rückätzen von verbindungskontakten

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US11/161,538 US7323410B2 (en) 2005-08-08 2005-08-08 Dry etchback of interconnect contacts
US11/161,538 2005-08-08

Publications (1)

Publication Number Publication Date
WO2007017400A1 true WO2007017400A1 (en) 2007-02-15

Family

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Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/EP2006/064757 Ceased WO2007017400A1 (en) 2005-08-08 2006-07-27 Dry etchback of interconnect contacts

Country Status (9)

Country Link
US (2) US7323410B2 (https=)
EP (1) EP1922753B1 (https=)
JP (1) JP4742147B2 (https=)
KR (1) KR101027172B1 (https=)
CN (1) CN101228624B (https=)
AT (1) ATE504084T1 (https=)
DE (1) DE602006021035D1 (https=)
TW (1) TWI377618B (https=)
WO (1) WO2007017400A1 (https=)

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US20070037316A1 (en) * 2005-08-09 2007-02-15 Micron Technology, Inc. Memory cell contact using spacers
US20070232048A1 (en) * 2006-03-31 2007-10-04 Koji Miyata Damascene interconnection having a SiCOH low k layer
US8399349B2 (en) 2006-04-18 2013-03-19 Air Products And Chemicals, Inc. Materials and methods of forming controlled void
US7947609B2 (en) * 2007-08-10 2011-05-24 Tokyo Electron Limited Method for etching low-k material using an oxide hard mask
US7935640B2 (en) * 2007-08-10 2011-05-03 Tokyo Electron Limited Method for forming a damascene structure
US8080473B2 (en) * 2007-08-29 2011-12-20 Tokyo Electron Limited Method for metallizing a pattern in a dielectric film
JP5102720B2 (ja) * 2008-08-25 2012-12-19 東京エレクトロン株式会社 基板処理方法
US8435901B2 (en) 2010-06-11 2013-05-07 Tokyo Electron Limited Method of selectively etching an insulation stack for a metal interconnect
KR102057855B1 (ko) 2013-11-13 2019-12-20 삼성전자 주식회사 반도체 소자 및 그 제조 방법
US9514977B2 (en) 2013-12-17 2016-12-06 Kabushiki Kaisha Toshiba Semiconductor device and manufacturing method thereof
US9484401B2 (en) 2014-11-24 2016-11-01 International Business Machines Corporation Capacitance reduction for advanced technology nodes
US9679807B1 (en) * 2015-11-20 2017-06-13 Globalfoundries Inc. Method, apparatus, and system for MOL interconnects without titanium liner

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US20040106297A1 (en) 2000-04-19 2004-06-03 Matsushita Electric Industrial Co., Ltd. Etching method, semiconductor and fabricating method for the same
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US20030127708A1 (en) * 2002-01-10 2003-07-10 Wen-Chung Liu Memory device with composite contact plug and method for manufacturing the same

Also Published As

Publication number Publication date
CN101228624A (zh) 2008-07-23
US7645700B2 (en) 2010-01-12
US20080088027A1 (en) 2008-04-17
EP1922753A1 (en) 2008-05-21
DE602006021035D1 (de) 2011-05-12
JP2009505385A (ja) 2009-02-05
US7323410B2 (en) 2008-01-29
KR101027172B1 (ko) 2011-04-05
US20070032055A1 (en) 2007-02-08
ATE504084T1 (de) 2011-04-15
JP4742147B2 (ja) 2011-08-10
CN101228624B (zh) 2011-07-20
EP1922753B1 (en) 2011-03-30
KR20080033300A (ko) 2008-04-16
TWI377618B (en) 2012-11-21
TW200741849A (en) 2007-11-01

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