CN101221947B - 具有半导体芯片和无源部件的半导体部件及其制造方法 - Google Patents
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Abstract
本发明涉及具有半导体芯片和无源部件的半导体部件及其制造方法。本发明涉及一种具有半导体芯片(2)和无源部件(3)的半导体部件(1),半导体部件(1)具有作为无源部件(3)的线圈(6)。半导体芯片(2)和无源部件(3)嵌入在具有连接外部接触(31)的连接元件的塑料封装化合物(4)中。
Description
技术领域
本发明涉及一种具有至少一个半导体芯片和至少一个无源部件的半导体部件、和它的制造方法。
背景技术
在该上下文中,措辞无源部件指电阻器、电容器和线圈,而有源元件包括晶体管、晶闸管或二极管。在这种情况下,可以用合适的金属层和隔离层的适当结构在半导体芯片材料上直接提供无源部件,其在功能性有源半导体芯片的制造期间是普通的,以形成电容器或线圈。相反,通常在半导体芯片的半导体材料中提供电阻器。
虽然电容器的提供由半导体芯片的平坦结构辅助,但在这些半导体芯片表面上提供的线圈会不利地限于螺旋形线圈。例如,围绕铁磁的、亚铁磁的或顺磁性的螺旋形线圈的线圈,与半导体芯片的制造方法基本上不相符。
然而,结合在介质塑料面板中的变压器结构,具有螺旋形地围绕变压器芯的线圈匝是已知的。为了这个目的,为了适应线圈芯和线圈绕组的垂直段,借助于碾磨和钻孔制备塑料面板形式的基板。然而,在具有至少一个塑料封装的半导体芯片的常规半导体部件的情况下,例如对于芯材料和垂直线圈段的结合的制备是不可行的。
发明内容
本发明涉及一种具有至少一个半导体芯片和至少一个无源部件的半导体部件。为了该目的,在塑料封装中嵌入半导体芯片和作为无源部件的线圈,在它的塑料封装化合物中,布置该半导体芯片和无源部件以及用于形成外部接触的连接元件。
现在,将参考附图更加详细地说明本发明。
附图说明
图1示出了根据本发明的一个实施例的半导体部件的示意透视图;
图2到10示出了如图1所示的半导体部件制造期间的部件图;
图2示出了通过用于半导体部件制造的具有涂层的安装板的示意截面;
图3示出了在将半导体芯片和线圈芯施加到涂层之后通过图2示出的安装板的示意截面;
图4示出了在将半导体芯片和线圈芯嵌入塑料封装化合物中形成复合晶片之后,通过图3示出的安装板的示意截面;
图5示出了在去除安装板之后,通过图4示出的复合晶片的示意截面;
图6示出了在引入盲孔之后,通过图5示出的复合晶片的示意截面;
图7示出了在用导电性材料填充盲孔形成垂直线圈段之后,通过图6示出的复合晶片的示意截面;
图8示出了在减薄复合晶片之后,通过图7示出的复合晶片的示意截面;
图9示出了在将下布线结构施加到复合晶片的表面之后,通过图8示出的变薄的复合晶片的示意截面;
图10示出了在将上布线结构施加到复合晶片的另一表面以制造具有线圈的半导体部件之后,通过图9示出的变薄的复合晶片的示意截面;
图11到16示出了根据本发明的另一实施例在制造半导体部件期间的部件图;
图11示出了在施加半导体芯片和线圈芯之后并将其嵌入塑料封装化合物中形成复合晶片之后通过安装板的示意截面;
图12示出了在将孔引入到复合晶片的塑料封装化合物之后,通过图11示出的安装板的示意截面;
图13示出了在去除安装板之后,通过图12示出的复合晶片的示意截面;
图14示出了在用导电材料填充所述孔形成垂直线圈段之后,通过图13示出的复合晶片的示意截面;
图15示出了在施加隔离层和下布线结构之后,通过图14示出的复合晶片的示意截面;
图1 6示出了在施加上布线结构以制造具有线圈的半导体部件之后,通过图15示出的复合晶片的示意截面;
图17到22示出了根据本发明的另一实施例在制造半导体部件期间的部件图;
图17示出了通过用于制造半导体部件的具有涂层的安装板的示意截面;
图18示出了在施加半导体芯片、线圈芯和垂直线圈段之后,通过图17示出的安装板的示意截面;
图19示出了在施加塑料封装化合物形成复合晶片之后,通过图18示出的安装板的示意截面;
图20示出了在去除安装板之后,通过图19示出的复合晶片的示意截面;
图21示出了在将下布线结构施加到复合晶片的表面之后,通过图20示出的复合晶片的示意截面;
图22示出了在将上布线结构施加到复合晶片的表面之后,通过图21示出的复合晶片的示意截面;
图23示出了图10、16和22中示出的复合晶片的细节的示意平面图;
图24示出了在分开复合晶片之后,图23中示出的半导体部件的示意平面图;
图25示出了通过如图24中示出的半导体部件的示意截面;
图26示出了在图25中示出的半导体部件的线圈和半导体芯片之间的连接元件的示意透视图。
具体实施方式
图1示出了根据本发明的一个实施例的半导体部件1的示意透视图。半导体部件1具有半导体芯片2和作为无源部件3的线圈6。线圈6和半导体芯片2嵌入在具有连接元件37的塑料封装4的塑料封装化合物5中。在本发明的该实施例中,线圈6的一端7经由互连9连接到半导体芯片2的接触焊盘38。线圈6的另一端8也经由互连9电连接到相邻的接触焊盘38。
互连9、接触焊盘38和线圈6的端7、8布置在由半导体芯片2的较高面30和周围的塑料封装化合物5形成的平面表面28上。该平面表面28使得由互连9、接触焊盘38和线圈6的端7、8构成的上布线结构10能够形成在它上面。线圈6本身具有垂直线圈段14和15以及水平线圈段16和17。水平线圈段16由具有端20和21的上互连段18的上布线结构10来形成,而布置在下平面表面29上的水平线圈段17由具有端22和23的下互连段19的下布线结构11形成。
垂直线圈段14和15从接近于半导体部件1的较高面的区域中的上布线结构10延伸到接近于半导体部件1的较低面的区域中的下布线结构11,并使上互连段18的端20和21连接到下互连段19的端22和23。为了该目的,垂直线圈段14和15具有经由塑料封装4的塑料封装化合物5的通路。此外,垂直线圈段14和15布置成彼此并排的两个相邻行,并交替地分别与上和下布线结构10和11的互连段的端20-23接触,以便以螺旋结构形成线圈匝13。
这些线圈匝13以螺旋形状围绕线圈芯24。为了该目的,线圈6的一匝13具有四个线圈段14到17,且第一互连段16的一端21经由垂直线圈段15连接到第二互连段17的一端22,以及另一垂直线圈段14连接到下互连段19的另一端23。此外,以在上布线结构10上布置线圈连接7和8的方式布置线圈匝13。
线圈芯24可具有铁磁的、亚铁磁的或顺磁性的芯材料。如果芯材料是顺磁性的,则它能够用塑料封装化合物5本身来形成。图1中示出的本发明实施例中的线圈芯是棒状的。然而,也可以将其它线圈芯形状依次嵌入塑料封装化合物中,例如,以形成具有两个或更多个线圈的变压器。最后,半导体部件1也能够具有多个上和下布线层,其相互隔离且形成用于线圈匝13的互连段20到23,并以半导体部件1具有多层线圈6的方式连接到彼此并排布置的多行通路。
在图1中示出的本发明的实施例中,隔离和钝化层27分别布置在塑料封装4的较低面上的下和上布线结构10和11上,并且隔离和钝化层26布置在塑料封装4的较高面12上。另外,半导体部件1在较高面12上具有表面安装的外部接触,外部接触焊盘31,其经由通路51连接到半导体芯片2的较高面30上的上布线结构10上的接触焊盘38。这些表面安装的外部接触可具有台面结构,或可以以焊料球形式焊接到外部接触焊盘31上。
图2到10示出了在制造多个半导体部件1期间的部件图,每个半导体部件1具有至少一个半导体芯片2和作为无源部件3的线圈6。为了该目的,首先由半导体芯片2、线圈芯24和具有包括塑料和半导体芯片2的较高面30的较高面12的塑料封装化合物5来形成复合晶片34。然后在该复合晶片34中将线圈6引入到塑料封装化合物5中。如果仅提供塑料封装化合物5的顺磁性材料作为线圈芯24,则能够完全在复合晶片中布置成行和列的半导体芯片2之间布置线圈6,而不需要先前在塑料封装化合物中嵌入线圈芯。
然而,如果如图1所示提供线圈芯24,则能够在将线圈匝13引入半导体芯片2之间的塑料封装化合物5之前,将这些线圈芯与半导体芯片2布置和封装在一起。因此,这种方法具有亚铁磁和铁磁线圈芯24都可以与可随后引入的线圈匝13结合的优点。然而,在这种情况下应该小心确保线圈芯24的高度小于或等于塑料封装化合物5的厚度。
在该上下文中,图2示出了通过用于制造半导体部件的具有涂层33的安装板32的示意截面,这种安装板32优选为晶片形式,然后能够以行和列在其上提供半导体部件位置。安装板32上的涂层33可以是粘合层或双面粘合膜,以便在它的较高面39上安置半导体部件的各部件。
图3示出了在将半导体芯片2和线圈芯施加到涂层33之后通过图2示出安装板32的示意截面。涂层33的粘合作用致使半导体芯片和线圈芯粘合在预期的半导体部件位置40处,图3示出了两个半导体部件位置40的细节。半导体芯片2通过它们的较高面30固定在涂层33上,以便保护它们的接触焊盘38不被塑料封装化合物弄湿。以能够不损坏线圈芯24地分离半导体部件位置40成单个半导体部件的方式将线圈芯24安置在半导体芯片2之间的间隔中。
图4示出了在将半导体芯片2和线圈芯24嵌入在塑料封装化合物5中形成复合晶片34之后通过图3示出的安装板32的示意截面。这种复合晶片34的尺寸与在半导体制造中的常规半导体晶片的尺寸对应,以便进一步有利地处理该复合晶片34作为由半导体制造已知的适当步骤中的半导体晶片。塑料封装化合物5完全覆盖了半导体芯片2的背面41和端面45和46,和线圈芯24的背面42,在该实施例中复合板的厚度D大于线圈芯24的高度h。
涂层33的较高面39确保在用塑料封装化合物5封装之后,将平面表面28形成为复合晶片34的较高面。由半导体芯片2的较高面30、线圈芯24的较高面43、和塑料封装化合物5的较高面44形成该平面表面28。该公共平面表面28也称为共平面表面并在制造各种隔离和金属化层的平面应用的半导体部件的工艺的其余部分期间使用。
图5示出了在去除安装板32之后通过如图4所示的复合晶片34的示意截面,如同图4示出的。现在,可将平面表面28完全理解为复合晶片34的较高面,并且由塑料封装化合物5的表面44、线圈芯24的表面43和半导体芯片2的较高面30形成。另外,复合晶片34具有由塑料封装化合物5形成的平面表面29作为较低面。
图6示出了在引入肓孔35之后通过如图5示出的复合晶片34的示意截面。肓孔35引入在线圈芯的两侧上,且它们的深度t大于线圈架24的高度h。为引入这样的肓孔35可提供各向异性蚀刻技术,在蚀刻处理期间平面表面28用结构化的保护层保护以免被侵蚀,并且只有肓孔35预期被引入到塑料封装化合物5的那些位置不用这种掩蔽保护层。这种各向异性蚀刻技术可优选借助反应等离子体蚀刻来实现。为了该目的,高度加速的离子与塑料封装化合物起反应以在预期产生肓孔35的暴露区域中形成挥发性物质。
引入这种肓孔35的另一种可能的方法是使用激光束来去除塑料封装化合物5。在这种情况下,以当受到激光束处理时分解成挥发性物质的方式加热塑料封装化合物5。这种激光束方法具有能在微米范围制造盲孔35的优点,以便随后在用导电材料填充它们时能够制造头发丝那样细的垂直线圈段。
图7示出了在用导电材料填充肓孔35之后通过图6示出的复合晶片34的示意截面。在施加所谓的“种子层”之后借助电化学沉积可将这种导电材料施加到肓孔35中,或可以通过汽相沉积和溅射技术来施加。除了这些物理方法之外,也能使用导电材料的化学沉积方法。在已用诸如这些的导电材料填充肓孔35形成垂直线圈段15和16之后,现在能将复合晶片34从它的由塑料封装化合物5形成的较低面29变薄,直到暴露出垂直线圈段15和16端47和48为止。借助CMP工艺可将诸如这样的复合晶片34变薄,在其期间在复合晶片的较低面29上执行化学机械抛光工艺,直到到达垂直线圈段15和16的端47和48为止。
图8示出了在图7中示出的复合晶片34由厚度D已变薄至厚度d之后通过图7示出的复合晶片34的示意截面。该化学机械抛光工艺致使在变薄的复合晶片34的较低面29上产生平面表面29,以便现在能够使两个平面平行的平面表面29和28分别用作复合晶片34的较低面和较高面以进行进一步处理。在该处理期间,将复合晶片34变薄,直到现在还暴露出线圈芯24的背面42为止。因此,在将下布线结构施加到复合晶片34的较低面29之前,首先施加隔离层,其后结构化隔离层致使允许从较低面接近垂直线圈段15和16。
图9示出了在将下布线结构11施加到复合晶片34的一个表面之后通过如图8示出的变薄的复合晶片34的示意截面,该表面在复合晶片34的较低面上由平面表面29形成。为了该目的,首先将隔离层27施加到复合晶片34的较低面上的平面表面29,其后结构化隔离层以便使至少垂直线圈段14和15可自由到达(accesible),同时还用隔离层27覆盖线圈芯24的背面42。现在能将垂直线圈段14和15交替地连接到下布线结构11的水平线圈段17。然后在随后的步骤中可将布线结构10施加到复合晶片34的较高面的平面表面28。
图10示出了在将上布线结构10施加到复合晶片34的一个表面以制造具有线圈6的半导体部件1之后,通过图9示出的变薄的复合晶片34的示意截面。为了该目的,如图10所示,使用在复合晶片34的较高面上的平面表面28,以便首先施加使线圈芯24的较高面43绝缘的平面隔离层26,且在结构化隔离层26之后,以经由水平线圈段16能将垂直线圈段14和15的端交替地彼此连接的方式,使垂直线圈段14和15的端暴露。
这会产生具有螺旋线圈6的半导体部件1的线圈匝13和由四个段,两个水平段16和17以及两个垂直段14和15构成的半导体芯片2,以不同的方式可将其均施加并引入到半导体芯片2之间的塑料封装化合物5中。为了制造单个半导体部件1,复合晶片然后,或在将其它保护层已施加到复合晶片34的较低面和较高面之后,沿分离的接合点50分裂成单个半导体部件1。
图11到16示出了根据本发明的另一实施例在制造半导体部件1期间的部件图。在这种情况下,再一次首先有效地制造具有涂层33的安装板32。安装板用半导体芯片2和线圈芯24安装,之后用塑料封装化合物5覆盖。在本发明的该另一实施例中,塑料封装化合物5和由此的复合晶片34的厚度d也正好与线圈芯24的高度h对应。在这种情况下,也能够使用线圈芯24以借助于擦拭器(wiper)使塑料封装化合物5的厚度d等于线圈芯24的高度h。
在该上下文中,图11示出了在施加半导体芯片2和线圈芯24之后,并将这些嵌入塑料封装化合物5中形成复合晶片34之后通过安装板32的示意截面。在这种情况下,图11仅示出了在复合面板34上的两个半导体部件位置40。用相同的参考符号表示具有与以前图中同样功能的部件,且将不再说明这些部件。本发明的该第二实施例的一个优点在于不需要将塑料封装化合物研磨变薄。
图12示出了在将孔36引入到复合晶片34的塑料封装化合物5之后通过图11示出的安装板32的示意截面。在这种情况下,孔36为通过塑料封装化合物5的通路的形式,以便在去除具有涂层33的安装板32之后,在塑料封装化合物5中产生通路。
图13示出了在去除安装板32之后,通过如图12示出的复合晶片34的示意截面。该复合面板34已具有与线圈芯24的高度h对应的其最终厚度d。此外,在去除具有涂层33的安装板32之后,该复合面板具有现在能用导电材料填充的通路以形成垂直线圈段。通路36现在能将隔离层和布线结构施加到复合晶片34较低面的平面表面29。
图14示出了在用导电材料填充孔形成线圈段14和15之后,通过图13示出的复合晶片34的示意截面。为了该目的,该导电材料可具有金属或重掺杂的多晶硅。借助于化学或电解沉积能施加该导电材料。在电解沉积的情况下,首先例如借助于溅射技术再次沉积“种子层”,以便电流能在电解沉积槽中流动。也能使用其它的CVD或PVD方法以在孔36中沉积垂直线圈段14和15。
图15示出了在施加隔离层26,然后结构化隔离层以暴露垂直线圈段14和15的端之后,通过图14示出的复合晶片34的示意截面。借助于在复合晶片34的较低面上布置的布线结构11和借助适当的水平互连段17,将这些垂直线圈段14和15依次交替地彼此连接,已示于图9中。
图16示出了在施加上布线结构10以实现具有线圈6的半导体部件1之后,通过图15示出的复合晶片34的示意截面。为了该目的,首先再次施加结构隔离层26,然后在其上沉积结构金属层以施加互连9和水平线圈段16。
图17到22示出了根据本发明的另一实施例在制造半导体部件1期间的部件图。首先,如图17所示,该工艺再次由制造半导体部件1的具有涂层33的安装板32开始。然而,在这种情况下,不仅将半导体芯片2和线圈芯24施加到涂层33,还有网状物25,如图18所示。
图18示出了在施加半导体芯片2、线圈芯24和布置在网状物25中的垂直线圈段14和15之后,通过图17示出的安装板的示意截面。这些网状物25可由高阻抗硅构成且可具有垂直线圈段14和15,以便能够用简单的方法将这种网状物25安装在安装板32上和在涂层33上的每个半导体部件位置40中的线圈芯24的两侧上。诸如具有垂直线圈段14和15的这种网状物25能够以低成本大量生产。在装配具有垂直布置的线圈段14和15的半导体部件期间,由此能够方便地使用由所谓的晶片级封装提供的性能,以便使制造具有半导体芯片2和螺旋线圈6的半导体部件合理化。代替具有相应的具有几微米的厚度的细丝(filigrane)线圈段14和15的硅网状物,也能使用其它的隔离网状物用于诸如这些的线圈段14和15。
图19示出了在施加塑料封装化合物5形成复合晶片34之后,通过图18示出的安装板32的示意截面。在这种情况下,能再次使用其中将相对平的平面表面29制造成复合晶片34的较低面的方法。至少能由该平面表面29的垂直线圈段来制造接触。在这种情况下,其已在图19中示出,也暴露出线圈芯24的背面42,使得在线圈芯的背面上需要绝缘。
图20示出了在去除图19中示出的安装板32之后通过复合晶片34的示意截面。该复合晶片34具有适合分别施加下和上布线结构的平坦较低面29和平坦较高面28。
为了该目的,如图21所示,首先将隔离层27施加到复合晶片34的较低面的平面表面29,结构化隔离层27并用下布线结构11覆盖。
然后,如下一图22所示,同样复合晶片34的较高面上的平面表面28被提供有结构化的隔离层26,对其施加上布线结构11,同时其经由互连9在线圈6和半导体芯片2、以及半导体芯片2上的接触焊盘38之间产生连接。这能通过单一选择金属化步骤实现,否则在线圈6的匝13的区域中能实现导电加强,以分别表示水平线圈段16和17。
图22因此示出了在将上布线结构10施加到复合晶片34的一个表面以实现具有半导体芯片2和螺旋线圈6的半导体部件1之后通过复合晶片34的示意截面。
图23示出了如图10、16和22所示的在半导体部件位置40区域中的复合晶片34的细节的示意平面图。为了该目的,在图23中省略了上隔离层26,以示出线圈6和半导体芯片2之间的相互作用。垂直线圈段14和15与线圈芯24并排地排成行。
在这种情况下,垂直线圈段14和15没有直接彼此相对,而是彼此相互偏移布置,以便使这种线圈6的螺旋结构变得明显。线圈端7和8经由互连9并借助上布线结构10与半导体芯片2的较高面30上对应提供的相邻接触焊盘38电连接。复合晶片34具有以行和列排列的并在图23中示出的半导体部件位置40,且分离接合点50布置在列方向上并且分离接合点49布置在行方向上,借助于其能将复合晶片34分成单个半导体部件1。另外,外部接触焊盘可以布置在接触焊盘38上,且本身被及时配备有外部接触,在这种情况下,外部接触可以是表面安装的且可以是焊料球或台面结构的形式。
图24示出了在分开复合晶片,以便现在在嵌入半导体芯片2和线圈6的塑料封装化合物5中产生半导体部件1之后,如图23所示的半导体部件1的示意平面图。在本发明的该实施例中,线圈6具有六个线圈匝13,其每个由四个线圈段构成,同样也以图25中所示的截面示出。
图25示出了如图24中示出的半导体部件1的示意截面。在该截面能够看出线圈匝13的垂直线圈段14,同时仅用虚线表示相关的第二垂直线圈段15。线圈6的一匝13具有与垂直线圈段14和15连接的水平线圈段16和17。隔离层26和27布置在各个水平线圈段14和15及线圈芯24之间,以确保线圈芯24的亚铁磁材料或铁磁材料在线圈匝13之间不会引起短路。线圈6的一端7经由平面表面28上的上布线结构10中的互连9电连接到半导体芯片2上的接触焊盘38。接触焊盘38也可以配备有外部接触焊盘,作为实例,在其上设置焊料球作为外部接触。
图26示出了在线圈6和半导体芯片2之间的连接元件37的示意透视图。如图1所示,用隔离层覆盖半导体芯片2,通路51或通路窗口通过隔离层会在外部接触焊盘31和半导体芯片2的较高面上的接触焊盘38之间产生连接。用点划线表示半导体部件1的外部轮廓,同时用点线大概表示半导体芯片2的轮廓。
参考标记列表
1半导体部件
2半导体芯片
3无源部件
4塑料封装
5塑料封装化合物
6线圈
7线圈或线圈连接的端
8线圈或线圈连接的端
9互连
10上布线结构
11下布线结构
12塑料封装的较高面
13线圈或线圈匝
14垂直线圈段或第三线圈段
15垂直线圈段或第四线圈段
16水平线圈段或第一线圈段
17水平线圈段或第二线圈段
18上互连段
19下互连段
20互连段的端
21互连段的端
22互连段的端
23互连段的端
24线圈芯或线圈材料
25网状物
26隔离层
27隔离层
28复合晶片的平面表面或较高面
29复合晶片的平面表面或较高面
30半导体芯片的较高面
31外部接触焊盘
32安装板
33安装板上的涂层
34复合晶片
35盲孔
36孔
37连接元件
38接触焊盘
39涂层的较高面
40半导体部件位置
41半导体芯片的背面
42线圈芯的背面
43线圈芯的较高面
44塑料封装化合物的较高面
45半导体芯片的端面
46半导体芯片的端面
47垂直线圈段的端
48垂直线圈段的端
49行方向上的分离接合点
50列方向上的分离接合点
51通路
D复合晶片的厚度
d变薄的复合晶片的厚度
t盲孔或孔的深度
Claims (25)
1.一种半导体部件,包括:
半导体芯片(2),
作为无源部件(3)的线圈(6),
塑料封装(4),在其塑料封装化合物(5)中嵌入了半导体芯片(2)和无源部件(3)以及用于形成外部接触的连接元件;
其中,所述线圈(6)的一端(7)经由互连(9)被连接到所述半导体芯片(2)的接触焊盘(38)上,并且所述线圈(6)的另一端(8)被电连接到相邻的接触焊盘上;
并且,所述互连(9)、所述接触焊盘(38)和所述线圈(6)的所述端(7,8)被布置在由所述半导体芯片(2)的较高面(30)和周围的所述塑料封装化合物(5)形成的平面表面(28)上。
2.根据权利要求1所述的半导体部件,其中线圈(6)的至少一端(7,8)经由塑料封装(4)的较高面(12)上的上布线结构(10)的互连电连接到半导体芯片(2)。
3.根据前述权利要求之一所述的半导体部件,
其中线圈(6)具有垂直(14,15)和水平(16,17)线圈段。
4.根据权利要求3所述的半导体部件,其中垂直线圈段(14,15)在半导体部件(1)中从接近较高面的区域中的上布线结构(10)延伸到接近较低面的区域中的下布线结构(11)。
5.根据权利要求3所述的半导体部件,
其中垂直线圈段(14,15)包括穿过塑料封装(4)的塑料封装化合物(5)的通路。
6.根据权利要求3所述的半导体部件,
其中垂直线圈段(14,15)彼此并排地布置成两个相邻行。
7.根据权利要求3所述的半导体部件,
其中在半导体部件(1)中水平线圈段(16,17)包括接近较高面的区域中的上布线结构(10)的互连段(18),和接近较低面的区域中的下布线结构(11)的互连段(19)。
8.根据权利要求6所述的半导体部件,
其中上和下布线结构(10,11)的互连段的端(20至23)与垂直线圈段(14,15)交替接触,以便线圈匝(13)具有螺旋结构。
9.根据权利要求1或权利要求2所述的半导体部件,
其中线圈(6)围绕着线圈芯(24)。
10.根据权利要求9所述的半导体部件,其中芯材料(24)包括塑料封装化合物(5)。
11.根据权利要求9所述的半导体部件,其中芯材料(24)包括亚铁磁材料。
12.根据权利要求9所述的半导体部件,其中芯材料(24)包括铁磁材料。
13.根据权利要求9所述的半导体部件,其中芯材料(24)包括顺磁性材料。
14.根据权利要求3所述的半导体部件,
其中多个垂直线圈段(14,15)成行地嵌入在预定绝缘网状物(25)中,并且其中具有其嵌入的垂直线圈段(14,15)的网状物(25)从下布线结构(11)延伸到上布线结构(10)。
15.根据权利要求2所述的半导体部件,
其中半导体部件具有彼此绝缘的多个上和下布线层,形成线圈匝(13)的互连段(20至23)并且以半导体部件(1)包括多层线圈(6)的方式连接到彼此并排布置的多行通路。
16.根据权利要求2所述的半导体部件,
其中隔离层和/或钝化层(26,27)布置在下和上布线结构(10,11)上。
17.根据权利要求1所述的半导体部件,
其中半导体部件(1)包括在半导体部件(1)的较高面(12)上的表面安装的外部接触,其布置在上布线结构(10)的外部接触焊盘(31)上。
18.一种制造多个半导体部件(1)的方法,所述多个半导体部件(1)中的每个均包括至少一个半导体芯片(2)和作为无源部件(3)的线圈(6),
其中所述方法具有以下方法步骤:
制造由半导体芯片(2)和具有较高面(12)的塑料封装化合物(5)构成的复合晶片,所述复合晶片包括塑料和所述半导体芯片(2)的较高面(30);
将线圈(6)引入到所述塑料封装化合物(5)中;
其中所述方法包括用于制造复合晶片的以下进一步的方法步骤:
提供具有多个半导体部件位置的安装板;
将所述半导体芯片(2)的所述较高面(30)施加到所述安装板;
将所述塑料封装化合物(5)施加到所述安装板,且所述半导体芯片(2)的端面(45,46)和背面(41)被嵌入,以及;
一旦所述塑料封装化合物(5)被固化,就去除所述安装板;
其中,在施加塑料封装化合物之前,具有彼此并排地排列成行的垂直线圈段(14)的绝缘网状物(25)和具有彼此并排地排列成行的垂直线圈段(15)的绝缘网状物(25)被布置在所述安装板(32)上,且所述网状物(25)和所述垂直线圈段(14,15)的高度与将要施加的所述塑料封装化合物(5)的厚度对应。
19.根据权利要求18所述的方法,
其中该方法包括制造线圈(6)的以下进一步的方法步骤:
将上和下布线结构(10,11)分别施加到复合晶片的较高面(28)和较低面(29),并且制造水平互连段(16,17),其使垂直线圈段(14,15)彼此连接以形成线圈(6),并将线圈(6)连接到半导体芯片(2)的较高面(30)上的至少一个接触焊盘(32)。
20.根据权利要求18所述的方法,其中该方法包括将垂直线圈段(14,15)引入到半导体芯片(2)之间的塑料封装化合物(15)中的以下进一步的方法步骤:
引入垂直孔;
将导电材料引入,且通路被形成为垂直线圈段(14,15);
用半导体芯片(2)的较高面(30)上的隔离层(26)涂覆复合晶片,且使半导体芯片(2)的接触焊盘(38)和垂直线圈段(14,15)的上端(20,21)暴露出。
21.根据权利要求18所述的方法,
其中该方法包括将水平线圈段(16,17)施加到复合晶片的以下进一步的方法步骤:
施加上布线结构(10)且形成外部接触焊盘(31)和互连段(18),其中互连段(18)连接垂直线圈段(14,15)的上端(20,21);
将隔离层(26)施加到上布线结构(10),且使用于上布线结构(10)的外部接触的外部接触焊盘(31)暴露;
用连接垂直线圈段(14,15)的下端(22,23)的互连段(19)将下布线结构(11)施加到复合晶片的较低面(29);
将隔离层(27)施加到下布线结构(11);
分裂复合晶片以在塑料封装(4)中形成具有至少一个半导体芯片(2)和至少一个线圈(6)的半导体部件(1)。
22.根据权利要求18所述的方法,
其中,在施加塑料封装化合物(5)之前,邻近安装板上的半导体芯片(2)安装由磁性材料构成的线圈芯(24),并且在施加塑料封装化合物(5)期间将线圈芯(24)与半导体芯片(2)一起嵌入。
23.根据权利要求21所述的方法,
其中并入盲孔(35)作为塑料封装化合物(5)中的孔(36),并且一旦将导电材料引入到孔(36),就将复合晶片(34)从其较低面变薄并且形成垂直线圈段(14,15),直到暴露出垂直线圈段(14,15)的下端(22,23)为止。
24.根据权利要求18所述的方法,
其中,甚至在去除安装板(32)之前,也能将盲孔(35)从复合晶片(34)的较低面引入到塑料封装化合物(5)中直至安装板(32)的较高面,并且所述盲孔被提供有导电材料以便形成垂直线圈段(14,15)。
25.根据权利要求18所述的方法,
其中,在去除安装板(32)之后,较高面和较低面能够被提供有布线结构(10,11)。
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Families Citing this family (28)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US7868445B2 (en) * | 2007-06-25 | 2011-01-11 | Epic Technologies, Inc. | Integrated structures and methods of fabrication thereof with fan-out metallization on a chips-first chip layer |
US8659154B2 (en) * | 2008-03-14 | 2014-02-25 | Infineon Technologies Ag | Semiconductor device including adhesive covered element |
US8354304B2 (en) * | 2008-12-05 | 2013-01-15 | Stats Chippac, Ltd. | Semiconductor device and method of forming conductive posts embedded in photosensitive encapsulant |
US7955942B2 (en) * | 2009-05-18 | 2011-06-07 | Stats Chippac, Ltd. | Semiconductor device and method of forming a 3D inductor from prefabricated pillar frame |
US8169065B2 (en) * | 2009-12-22 | 2012-05-01 | Epic Technologies, Inc. | Stackable circuit structures and methods of fabrication thereof |
US8895440B2 (en) | 2010-08-06 | 2014-11-25 | Stats Chippac, Ltd. | Semiconductor die and method of forming Fo-WLCSP vertical interconnect using TSV and TMV |
DE102010039156A1 (de) * | 2010-08-10 | 2012-02-16 | Robert Bosch Gmbh | Verfahren zum Herstellen einer elektrischen Schaltung und elektrische Schaltung |
US8461691B2 (en) * | 2011-04-29 | 2013-06-11 | Infineon Technologies Ag | Chip-packaging module for a chip and a method for forming a chip-packaging module |
US9343442B2 (en) * | 2012-09-20 | 2016-05-17 | Taiwan Semiconductor Manufacturing Company, Ltd. | Passive devices in package-on-package structures and methods for forming the same |
US9721920B2 (en) | 2012-10-19 | 2017-08-01 | Infineon Technologies Ag | Embedded chip packages and methods for manufacturing an embedded chip package |
US9203373B2 (en) | 2013-01-11 | 2015-12-01 | Qualcomm Incorporated | Diplexer design using through glass via technology |
US9935166B2 (en) | 2013-03-15 | 2018-04-03 | Qualcomm Incorporated | Capacitor with a dielectric between a via and a plate of the capacitor |
US9634640B2 (en) | 2013-05-06 | 2017-04-25 | Qualcomm Incorporated | Tunable diplexers in three-dimensional (3D) integrated circuits (IC) (3DIC) and related components and methods |
US9264013B2 (en) | 2013-06-04 | 2016-02-16 | Qualcomm Incorporated | Systems for reducing magnetic coupling in integrated circuits (ICS), and related components and methods |
US9190389B2 (en) * | 2013-07-26 | 2015-11-17 | Infineon Technologies Ag | Chip package with passives |
US9978700B2 (en) | 2014-06-16 | 2018-05-22 | STATS ChipPAC Pte. Ltd. | Method for building up a fan-out RDL structure with fine pitch line-width and line-spacing |
US9704739B2 (en) | 2014-07-30 | 2017-07-11 | Taiwan Semiconductor Manufacturing Company, Ltd. | Semiconductor device packages, packaging methods, and packaged semiconductor devices |
KR101785306B1 (ko) * | 2014-12-09 | 2017-10-17 | 인텔 코포레이션 | 몰드 화합물 내의 3차원 구조체 |
US9831159B2 (en) * | 2015-06-09 | 2017-11-28 | Infineon Technologies Americas Corp. | Semiconductor package with embedded output inductor |
KR102384863B1 (ko) * | 2015-09-09 | 2022-04-08 | 삼성전자주식회사 | 반도체 칩 패키지 및 이의 제조 방법 |
US10026546B2 (en) * | 2016-05-20 | 2018-07-17 | Qualcomm Incorported | Apparatus with 3D wirewound inductor integrated within a substrate |
US10269732B2 (en) * | 2016-07-20 | 2019-04-23 | Taiwan Semiconductor Manufacturing Company, Ltd. | Info package with integrated antennas or inductors |
US10332841B2 (en) | 2016-07-20 | 2019-06-25 | Taiwan Semiconductor Manufacturing Company, Ltd. | System on integrated chips and methods of forming the same |
DE102016115629A1 (de) * | 2016-08-23 | 2018-03-01 | Osram Opto Semiconductors Gmbh | Verfahren zum herstellen eines optoelektronischen bauelements |
US10181449B1 (en) * | 2017-09-28 | 2019-01-15 | Taiwan Semiconductor Manufacturing Co., Ltd. | Semiconductor structure |
US10790244B2 (en) * | 2017-09-29 | 2020-09-29 | Taiwan Semiconductor Manufacturing Company, Ltd. | Semiconductor device and method |
EP3557608A1 (en) * | 2018-04-19 | 2019-10-23 | AT & S Austria Technologie & Systemtechnik Aktiengesellschaft | Packaged integrated circuit with interposing functionality and method for manufacturing such a packaged integrated circuit |
US11121699B2 (en) | 2019-02-19 | 2021-09-14 | Qualcomm Incorporated | Wideband filter with resonators and inductors |
Citations (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5576680A (en) * | 1994-03-01 | 1996-11-19 | Amer-Soi | Structure and fabrication process of inductors on semiconductor chip |
US6148500A (en) * | 1995-07-24 | 2000-11-21 | Autosplice Systems Inc. | Electronic inductive device and method for manufacturing |
US6441715B1 (en) * | 1999-02-17 | 2002-08-27 | Texas Instruments Incorporated | Method of fabricating a miniaturized integrated circuit inductor and transformer fabrication |
Family Cites Families (17)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
FR2599893B1 (fr) | 1986-05-23 | 1996-08-02 | Ricoh Kk | Procede de montage d'un module electronique sur un substrat et carte a circuit integre |
US5070317A (en) | 1989-01-17 | 1991-12-03 | Bhagat Jayant K | Miniature inductor for integrated circuits and devices |
DE4432725C1 (de) | 1994-09-14 | 1996-01-11 | Fraunhofer Ges Forschung | Verfahren zur Herstellung eines dreidimensionalen Bauteils oder einer Bauteilgruppe |
US20020190389A1 (en) * | 1995-11-15 | 2002-12-19 | Koenck Steven E. | Reduction of electromagnetic interference in integrated circuit device packages |
US5886587A (en) * | 1997-02-11 | 1999-03-23 | Raytheon Company | Flipped lumped element circulator |
US5909050A (en) | 1997-09-15 | 1999-06-01 | Microchip Technology Incorporated | Combination inductive coil and integrated circuit semiconductor chip in a single lead frame package and method therefor |
US6239980B1 (en) | 1998-08-31 | 2001-05-29 | General Electric Company | Multimodule interconnect structure and process |
US6542379B1 (en) | 1999-07-15 | 2003-04-01 | International Business Machines Corporation | Circuitry with integrated passive components and method for producing |
EP1093081A1 (en) | 1999-10-14 | 2001-04-18 | Nippon Telegraph and Telephone Corporation | Integrated circuit chip, method of manufacturing the same, IC card, and method of manufacturing the same |
US6531945B1 (en) | 2000-03-10 | 2003-03-11 | Micron Technology, Inc. | Integrated circuit inductor with a magnetic core |
US6424263B1 (en) * | 2000-12-01 | 2002-07-23 | Microchip Technology Incorporated | Radio frequency identification tag on a single layer substrate |
DE10144462C1 (de) * | 2001-09-10 | 2002-11-28 | Infineon Technologies Ag | Elektronisches Bauteil mit wenigstens einem Halbleiterchip und Verfahren zu seiner Herstellung |
US6642811B2 (en) * | 2002-01-30 | 2003-11-04 | International Business Machines Corporation | Built-in power supply filter for an integrated circuit |
WO2005038916A2 (en) * | 2003-10-16 | 2005-04-28 | Koninklijke Philips Electronics N.V. | Inductor coil for an ic chip |
US7459781B2 (en) * | 2003-12-03 | 2008-12-02 | Wen-Kun Yang | Fan out type wafer level package structure and method of the same |
EP1544917A1 (en) * | 2003-12-15 | 2005-06-22 | Dialog Semiconductor GmbH | Integrated battery pack with lead frame connection |
US7531893B2 (en) * | 2006-07-19 | 2009-05-12 | Texas Instruments Incorporated | Power semiconductor devices having integrated inductor |
-
2006
- 2006-12-07 DE DE102006058068.0A patent/DE102006058068B4/de not_active Expired - Fee Related
- 2006-12-21 US US11/614,579 patent/US8471393B2/en active Active
-
2007
- 2007-12-06 CN CN2007101648859A patent/CN101221947B/zh active Active
Patent Citations (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5576680A (en) * | 1994-03-01 | 1996-11-19 | Amer-Soi | Structure and fabrication process of inductors on semiconductor chip |
US6148500A (en) * | 1995-07-24 | 2000-11-21 | Autosplice Systems Inc. | Electronic inductive device and method for manufacturing |
US6441715B1 (en) * | 1999-02-17 | 2002-08-27 | Texas Instruments Incorporated | Method of fabricating a miniaturized integrated circuit inductor and transformer fabrication |
Also Published As
Publication number | Publication date |
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DE102006058068B4 (de) | 2018-04-05 |
US8471393B2 (en) | 2013-06-25 |
US20080135977A1 (en) | 2008-06-12 |
CN101221947A (zh) | 2008-07-16 |
DE102006058068A1 (de) | 2008-06-12 |
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