CN101207091B - 闪存器件的制造方法 - Google Patents

闪存器件的制造方法 Download PDF

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Publication number
CN101207091B
CN101207091B CN2007103018967A CN200710301896A CN101207091B CN 101207091 B CN101207091 B CN 101207091B CN 2007103018967 A CN2007103018967 A CN 2007103018967A CN 200710301896 A CN200710301896 A CN 200710301896A CN 101207091 B CN101207091 B CN 101207091B
Authority
CN
China
Prior art keywords
layer
semiconductor substrate
gate pattern
voluntarily
silicide
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
CN2007103018967A
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English (en)
Chinese (zh)
Other versions
CN101207091A (zh
Inventor
朴真河
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
DB HiTek Co Ltd
Original Assignee
Dongbu Electronics Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority claimed from KR1020060135571A external-priority patent/KR100789610B1/ko
Priority claimed from KR1020060137287A external-priority patent/KR100840645B1/ko
Application filed by Dongbu Electronics Co Ltd filed Critical Dongbu Electronics Co Ltd
Publication of CN101207091A publication Critical patent/CN101207091A/zh
Application granted granted Critical
Publication of CN101207091B publication Critical patent/CN101207091B/zh
Expired - Fee Related legal-status Critical Current
Anticipated expiration legal-status Critical

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Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
    • H10B41/30—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the memory core region
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • H01L21/28008—Making conductor-insulator-semiconductor electrodes
    • H01L21/28017—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon
    • H01L21/28026—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor
    • H01L21/28123—Lithography-related aspects, e.g. sub-lithography lengths; Isolation-related aspects, e.g. to solve problems arising at the crossing with the side of the device isolation; Planarisation aspects
    • H01L21/28141—Lithography-related aspects, e.g. sub-lithography lengths; Isolation-related aspects, e.g. to solve problems arising at the crossing with the side of the device isolation; Planarisation aspects insulating part of the electrode is defined by a sidewall spacer, e.g. dummy spacer, or a similar technique, e.g. oxidation under mask, plating
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
    • H01L21/67005—Apparatus not specifically provided for elsewhere
    • H01L21/67011—Apparatus for manufacture or treatment
    • H01L21/67017—Apparatus for fluid treatment
    • H01L21/67063—Apparatus for fluid treatment for etching
    • H01L21/67075—Apparatus for fluid treatment for etching for wet etching
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76897—Formation of self-aligned vias or contact plugs, i.e. involving a lithographically uncritical step
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/401—Multistep manufacturing processes
    • H01L29/4011—Multistep manufacturing processes for data storage electrodes
    • H01L29/40114—Multistep manufacturing processes for data storage electrodes the electrodes comprising a conductor-insulator-conductor-insulator-semiconductor structure
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
    • H10B41/10—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the top-view layout

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Ceramic Engineering (AREA)
  • Semiconductor Memories (AREA)
  • Non-Volatile Memory (AREA)
CN2007103018967A 2006-12-20 2007-12-20 闪存器件的制造方法 Expired - Fee Related CN101207091B (zh)

Applications Claiming Priority (9)

Application Number Priority Date Filing Date Title
KR1020060131443 2006-12-20
KR10-2006-0131443 2006-12-20
KR1020060131443A KR100831158B1 (ko) 2006-12-20 2006-12-20 플래시 메모리 소자의 제조방법
KR10-2006-0135571 2006-12-27
KR1020060135571A KR100789610B1 (ko) 2006-12-27 2006-12-27 플래시 메모리 소자의 제조 방법
KR1020060135571 2006-12-27
KR10-2006-0137287 2006-12-29
KR1020060137287 2006-12-29
KR1020060137287A KR100840645B1 (ko) 2006-12-29 2006-12-29 플래시 메모리 소자의 제조 방법

Publications (2)

Publication Number Publication Date
CN101207091A CN101207091A (zh) 2008-06-25
CN101207091B true CN101207091B (zh) 2010-06-02

Family

ID=39567140

Family Applications (1)

Application Number Title Priority Date Filing Date
CN2007103018967A Expired - Fee Related CN101207091B (zh) 2006-12-20 2007-12-20 闪存器件的制造方法

Country Status (2)

Country Link
KR (1) KR100831158B1 (ko)
CN (1) CN101207091B (ko)

Families Citing this family (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN103187368B (zh) * 2011-12-31 2015-06-03 中芯国际集成电路制造(上海)有限公司 嵌入式闪存中晶体管的形成方法
CN106356299B (zh) * 2015-07-13 2021-04-13 联华电子股份有限公司 具有自我对准间隙壁的半导体结构及其制作方法
CN106558545A (zh) * 2015-09-30 2017-04-05 中芯国际集成电路制造(上海)有限公司 半导体器件的形成方法
US10784270B2 (en) * 2018-06-26 2020-09-22 Taiwan Semiconductor Manufacturing Co., Ltd. Method to improve fill-in window for embedded memory
DE102018119907B4 (de) 2018-06-26 2022-06-02 Taiwan Semiconductor Manufacturing Co. Ltd. Integrierte Schaltung und Verfahren zum Ausbilden einer integrierten Schaltung und zur Verbesserung des Einfüllfensters für eingebetteten Speicher
CN110190058A (zh) * 2019-05-27 2019-08-30 武汉新芯集成电路制造有限公司 半导体器件及其制造方法

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6610571B1 (en) * 2002-02-07 2003-08-26 Taiwan Semiconductor Manufacturing Company Approach to prevent spacer undercut by low temperature nitridation
CN1458683A (zh) * 2002-05-14 2003-11-26 三星电子株式会社 具有增加的有效沟槽长度的半导体器件的制造方法
CN1551334A (zh) * 2003-05-14 2004-12-01 旺宏电子股份有限公司 形成非挥发性存储元件的方法
CN1591823A (zh) * 2003-08-27 2005-03-09 上海宏力半导体制造有限公司 增加集成电路构装密度的制造方法

Family Cites Families (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100538066B1 (ko) 1998-10-27 2006-03-14 주식회사 하이닉스반도체 플래쉬 메모리 셀의 제조 방법
KR100297728B1 (ko) 1999-05-17 2001-09-26 윤종용 플래쉬 메모리 소자의 제조방법 및 그에 의해 제조된 플래쉬 메모리 소자
KR100590380B1 (ko) 1999-12-28 2006-06-15 주식회사 하이닉스반도체 플래쉬 메모리 소자의 제조방법
KR100671627B1 (ko) * 2004-10-25 2007-01-19 주식회사 하이닉스반도체 플래쉬 메모리소자의 소스 콘택 형성방법

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6610571B1 (en) * 2002-02-07 2003-08-26 Taiwan Semiconductor Manufacturing Company Approach to prevent spacer undercut by low temperature nitridation
CN1458683A (zh) * 2002-05-14 2003-11-26 三星电子株式会社 具有增加的有效沟槽长度的半导体器件的制造方法
CN1551334A (zh) * 2003-05-14 2004-12-01 旺宏电子股份有限公司 形成非挥发性存储元件的方法
CN1591823A (zh) * 2003-08-27 2005-03-09 上海宏力半导体制造有限公司 增加集成电路构装密度的制造方法

Non-Patent Citations (4)

* Cited by examiner, † Cited by third party
Title
JP特开2000-174270A 2000.06.23
说明书第[0022]段至第[0140]段、附图1-14.
说明书第[0034]段至第[0066]段、附图2a-2d.
说明书第3页至第4页、附图1-6.

Also Published As

Publication number Publication date
CN101207091A (zh) 2008-06-25
KR100831158B1 (ko) 2008-05-20

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Granted publication date: 20100602

Termination date: 20131220