CN101106131A - 半导体结构及其形成方法 - Google Patents

半导体结构及其形成方法 Download PDF

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CN101106131A
CN101106131A CNA200610172428XA CN200610172428A CN101106131A CN 101106131 A CN101106131 A CN 101106131A CN A200610172428X A CNA200610172428X A CN A200610172428XA CN 200610172428 A CN200610172428 A CN 200610172428A CN 101106131 A CN101106131 A CN 101106131A
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drain
transistor
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semiconductor structure
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CN100499129C (zh
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彭远清
陈欣仪
卢叙伟
林学仕
陈伟铭
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Taiwan Semiconductor Manufacturing Co TSMC Ltd
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Abstract

本发明提供一种半导体结构及其形成方法，其采用栅极置换工艺。半导体结构具有端接接触部结构(butted contact)，其电性连接源极/漏极至栅极延伸部(gate extension)。上述的半导体结构还包括设于源极/漏极上并与其电性连接的接触垫。接触垫可降低电阻，也可减少端接接触部与源极/漏极间断路(open)的可能性。接触垫的上表面优选与栅极延伸部等高。

Description

半导体结构及其形成方法
技术领域
本发明涉及一种半导体结构及其形成方法，更特别涉及一种端接接触部(butted contact)。
背景技术
端接接触部已广泛应用于半导体元件的电性连接，由于只需较少的布局区域，特别适用于高密度集成电路，如静态随机存储存储器(static randomaccess memory，以下简称SRAM)。
图1、2所示为应用端接接触部的例子。图1显示已知的六晶体管SRAM(以下简称6T SRAM)单元，其具有通栅晶体管10及锁存器，锁存器包括晶体管12、14、16、及18。通栅晶体管10(pass gate transistor)的栅极1由字线WL控制，以选择特定的存储单元，锁存器则通过上拉晶体管12、下拉晶体管14、晶体管16及18来存储状态。通过位线BL可读取被存储的状态。
端接接触部可应用于图1中电路的多种电性连接。举例来说，端接接触部可应用于下述情况：通栅晶体管10的源极2，与晶体管16、18的栅极6的电性连接；晶体管16、18的栅极6，与晶体管12、14各自的漏极4、8的电性连接；以及晶体管12、14的栅极21，与晶体管16、18各自的漏极15、23的电性连接。
图2显示端接接触部42的剖面图，其介于晶体管16及18的栅极或栅极延伸部6，与通栅晶体管10的源极2之间。40指的是浅沟槽绝缘区(以下简称STI)。已知工艺的端接接触部有蚀刻负载效应的缺点，会形成非垂直的轮廓。如图3所示，其底部比顶部窄，其底部与晶体管10的漏极2的重叠区域44因此缩小，并增加端接接触部的电阻。最糟的情况为重叠区域44将完全消失并形成断路(open)，使集成电路失效。
因此，现在需要设计新的端接接触部，以克服上述问题。
发明内容
本发明提供一种半导体结构，包括一浅沟槽绝缘区，位于一基板中；第一晶体管，包括一栅极位于该基板上，以及一源极/漏极邻接该浅沟槽绝缘区；一栅极延伸部，位于该浅沟槽绝缘区之上，且电性连接至一第二晶体管的一栅极；一端接接触部，位于该栅极延伸部之上，并电性连接至该栅极延伸部；一接触垫，电性连接该端接接触部与该第一晶体管的该源极/漏极，其中该接触垫位于该端接接触部之下，且该接触垫的上表面实质上与该栅极延伸部的上表面等高。
本发明进一步提供一种半导体结构，包括：一半导体基板；一绝缘结构，自该半导体基板的上表面延伸至该半导体基板中；一层间介电层，位于该半导体基板上；一第一晶体管，包括：一第一与一第二源极/漏极，位于该层间介电层之下，且该第一源极/漏极邻接该绝缘结构、一第一与一第二金属硅化层，各自介于该层间介电层及该第一与该第二源极/漏极之间、以及一栅极，位于该层间介电层中，且该栅极介于该第一与该第二源极/漏极之间，并具有与该层间介电层上表面等高的上表面；一接触垫，位于该层间介电层中及该第一金属硅化层之上；一栅极延伸部，位于该绝缘结构上；以及一端接接触部，电性连接该接触垫及该栅极延伸部。
本发明进一步提供一种半导体结构，包括一晶体管及其源极/漏极；一介电层，邻接该源极/漏极；一导电图案，位于该介电层上，并具有一上表面实质上高于该源极/漏极的上表面；一接触垫，位于该源极/漏极上，并电性连接至该源极/漏极；以及一端接接触部，电性连接该接触垫与该导电图案。
本发明还提供一种半导体结构的形成方法，其采用置换栅极工艺，包括形成一晶体管，该晶体管具有一虚置栅极；沉积一层间介电层并平坦化，该层间介电层的上表面高度与该虚置栅极的上表面等高；移除该虚置栅极，形成一第一开口；移除部分该层间介电层，形成一第二开口，且该第二开口至少露出该第一晶体管部分的源极/漏极；以金属填满该第一开口形成该第一晶体管的一金属栅极，并同时以金属填满该第二开口形成一接触垫；以及形成一端接接触部，其电性连接该接触垫与一浅沟槽绝缘上的一栅极延伸部，且该浅沟槽绝缘区邻接该第一晶体管的源极/漏极。
本发明优选实施例的接触垫可减少端接接触部的缩减距离，因此可增加接触面积并降低接触电阻，同时降低断路(open)的可能性。另一个优点是，现有的技术即可将接触垫整合至工艺中，而不一定需要额外的步骤及掩膜。
附图说明
图1为6T SRAM单元的电路图；
图2为端接接触部的剖面图，其电性连接一晶体管的漏极及另一晶体管的栅极延伸部，且该端接接触部具有垂直的轮廓；
图3为端接接触部的剖面图，其为负向轮廓，因底部较顶部窄；
图4为本发明优选实施例的半导体结构；
图5至图13为本发明优选实施例的剖面图，显示半导体结构的工艺。
【主要元件符号说明】
BL～位线；WL～字线；10～通栅晶体管；12、14、16、18～锁存器的晶体管；1～栅极；2～源极；6～栅极延伸部；40～浅沟槽绝缘区；42～端接接触部；48～接触垫；α～顶角；D1、D2～缩减距离；D3～接触垫与源极/漏极接触的宽度；D4～源极/漏极的宽度；H1、端接接触部的高度；H2～接触垫的高度；100～pMOS；200～nMOS；102～n型阱区；104～栅极介电层；108～侧壁间隔物；202～p型阱区；106、206、306～虚置栅极；109、209～金属硅化层；110、210～源极/漏极；112、116～开口；120～金属栅极；122～接触垫；305～浅沟槽绝缘区；308、320、～层间介电层；310、322～光阻层；318～金属层；324～接触开口；326～金属插塞；328～端接接触部。
具体实施方式
如图3所示，若以端接接触部的顶角α来分，端接接触部具有三种可能的轮廓。值得注意的是，邻接端接接触部的介电层已被省略以简化图示。当顶角α大于90度时，其为正向轮廓；等于90度时，其为垂直轮廓；小于90度时，其为负向轮廓。图2为垂直轮廓，而图3为负向轮廓。一般说来，优选垂直轮廓。
由于蚀刻负载效应，集成电路中各别的端接接触部其轮廓通常不一致。其中一些端接接触部具有垂直轮廓，其它则为正向轮廓或负向轮廓。端接接触部的轮廓控制可通过工艺参数调整，比如将介电层进行蚀刻/成形(shaping)的过蚀刻时间。举例来说，在介电层形成开口时可增加过蚀刻时间，如此则可解决端接接触部的轮廓问题。然而这会造成负作用，如开口的鸟嘴。
如图3所示，负向轮廓的端接接触部42，其底部缩减的距离为D1。当D1增加，将减少源极/漏极2与端接接触部42的接触区域，并增加接触电阻。最后，当顶角α够小时，接触区域将完全消失并形成断路(open)。缩减距离D1与端接接触部的高度H1的关系如下述公式：D1＝H1*cot(α)。α趋近于90度或H1降低均有助于减少D1。
图4为本发明的优选实施例，其可有效减少底部缩减的距离D1。端接接触部42电性连接一晶体管的栅极延伸部6以及另一晶体管的源极/漏极2，两者间设有一接触垫48。端接接触部的剖面优选为垂直轮廓的长方形，然而为了解释方便，其剖面为负向轮廓。源极/漏极2上更可包括一金属硅化层5。顾名思义，栅极延伸部6可电性连接栅极，但其也可电性连接至其它的导电图案。接触垫48的材料可为金属、金属硅化物、多晶硅、或其它合适的材料，其形成方法为一般已知的方法。若接触垫选用金属硅化物，其上表面的高度需高于已知技艺的金属硅化物。值得注意的是，端接接触部42具有一缩减距离D2＝cot(α)*(H1-H2)，且D2小于D1。接触垫48与栅极延伸部6的上表面优选为等高，两者上表面的高度差为ΔH。ΔH优选小于接触垫高度H2的10％，最优选为0。
接触垫48优选为延伸覆盖STI 40。为降低接触垫48与其下的源极/漏极2之间的接触电阻，两者间的重叠宽度D3优选大于源极/漏极2宽度D4的一半，最好D3等于D4。由于缩减距离D2减少，再加上接触垫48延伸覆盖至STI 40，因此更增加了接触垫48与其上的端接接触部42的接触面积，断路(open)的可能性与接触电阻均因此而明显地降低。
本发明实施例的一个优点是，额外的接触垫48并不需增加太多额外的工艺步骤。在仔细设计下，接触垫可整合至现有工艺，而不需增加掩膜或其它工艺。图5-图13显示本发明实施例应用栅极置换步骤的工艺。半导体元件具有虚置栅极(dummy gate)、侧壁间隔物、及源极/漏极，并进行热退火步骤。的后以金属栅极取代虚置栅极，可避免热退火对金属栅极的不利影响。
图5中，以STI 305分隔pMOS晶体管100与nMOS晶体管200。基板的102区域优选掺杂为n型阱区，202区域优选掺杂为p型阱区。值得注意的是，虽然图示中晶体管100及200的距离很近，但在实际应用上两者通常彼此远离。在优选实施例中，栅极介电层104、204可为HfO2。在其它实施例中，栅极介电层104、204可为硅酸盐，如HfSiO4、HfSiON、HfSiN、ZrSiO4、或其它合适的硅酸盐。其它合适的材料还包含金属氧化物、金属氮化物、过渡金属硅酸盐。源极/漏极110、210各自对应于元件100、200，活化方式优选为热退火。源极/漏极110、210优选为半导体材料各自掺杂适当的p型或n型杂质，并各自可具有金属硅化层109、209于其上。
优选实施例中，虚置栅极106、206具有TaN层于HfN层上的两层结构。在其它实施例中，虚置栅极为多晶硅。形成于STI 305上的栅极延伸部306优选电性连接至另一晶体管(未图示)的栅极，也可电性连接至其它的导电元件如源极/漏极、接点、或其它导电元件。栅极延伸部306的组成可为多晶硅或其它的导电材质如金属。
如图6所示，等厚沉积一层间介电层(Inter-layer dielectric，以下简称ILD)后进行平坦化步骤，使其上表面与虚置栅极106、206的上表面等高如图中ILD308所示。
接着形成光阻层310并图案化。优选的实施例中，以非等向蚀刻移除虚置栅极106以及部分的ILD 308，形成开口112与116。举例来说，蚀刻剂为HBr、Cl2、O2、CH2F2、CHF3、CF4、及Ar时，可移除材料为磷硅酸玻璃(PSG)或二氧化硅(SiO2)的ILD 308与多晶虚置栅极106。在另一实施例中，优选以HBr、Cl2、及O2蚀刻多晶虚置栅极106，以CF4蚀刻材料为磷硅酸玻璃(PSG)或二氧化硅(SiO2)的ILD 308。开口116将露出源极/漏极110。如图7所示，为了降低端接接触部的接触电阻，开口116优选邻接侧壁间隔物108，但本领域技术人员可视需要将开口远离侧壁间隔物108以避免对位误差(misalignment)。开口116优选延伸至STI 305。
如图8所示，沉积金属层318以填满开口112与116后进行平坦化步骤。优选的平坦化步骤为化学机械抛光(Chemical mechanical polish，以下简称CMP)，金属层优选为高工作函数的金属。如图9所示，开口112与116中的金属分别形成金属栅极120与接触垫122。
如图10所示，另一ILD 320沉积于上述结构。ILD 320的材料优选为低介电常数材料如四乙基硅酸盐(TEOS)，优选的形成方式为化学气相沉积(CVD)、等离子增强式化学气相沉积(PECVD)、低压化学气相沉积法(LPCVD)、或其它合适的沉积方法。ILD 320使MOS元件100、200及其上的金属线路彼此绝缘。此技艺人士自可依需要形成接触蚀刻停止层(因简化而未图示)于ILD 320下。
如图11所示，于ILD 320上形成光阻层322，之后图案化光阻层322以形成接触开口。图12显示光阻层322未屏蔽部分的ILD 320及ILD 308均被蚀刻。在形成接触开口324后，移除光阻层322。
如图13所示，以导电材料填满接触开口324以形成金属插塞326与端接接触部328，之后以CMP移除多余的导电材料，只留下金属插塞326与端接接触部328。合适的导电材料可为W、Al、Cu、或其它已知的导电材料。金属插塞326与端接接触部328也可为复合结构，比如含有阻挡层及粘着层如Ti/TiN、Ta/TaN、或其它类似的结构。
值得注意的是，图4可用来电性连接其它导电图案如接点、导电线路、或其它适合的半导体元件，而不限于电性连接源极/漏极。利用接触垫的观念，可降低端接接触部的高度，并减少其底部的缩减距离并增加底部的接触面积，进而改善可靠度与接触电阻。

Claims (10)

1.一种半导体结构，其特征在于，包括：
一浅沟槽绝缘区，位于一基板中；
一第一晶体管，包括一栅极位于该基板上，以及一源极/漏极邻接该浅沟槽绝缘区；
一栅极延伸部，位于该浅沟槽绝缘区之上，且电性连接至一第二晶体管的一栅极；
一端接接触部，位于该栅极延伸部之上，并电性连接至该栅极延伸部；
一接触垫，电性连接该端接接触部与该第一晶体管的该源极/漏极，其中该接触垫位于该端接接触部之下，且该接触垫的上表面实质上与该栅极延伸部的上表面等高。
2.如权利要求1所述的半导体结构，其特征在于，还包括一金属硅化层，位于该源极/漏极之上及该接触垫之下。
3.如权利要求1所述的半导体结构，其特征在于，该端接接触部的下表面比其上表面窄。
4.如权利要求1所述的半导体结构，其特征在于，该接触垫实质上覆盖该浅沟槽绝缘区。
5.一种半导体结构，其特征在于，包括：
一半导体基板；
一绝缘结构，自该半导体基板的上表面延伸至该半导体基板中；
一层间介电层，位于该半导体基板上；
一第一晶体管，包括：
一第一与一第二源极/漏极，位于该层间介电层之下，且该第一源极/漏极邻接该绝缘结构；
一第一与一第二金属硅化层，各自介于该层间介电层及该第一与该第二源极/漏极之间；以及
一栅极，位于该层间介电层中，且该栅极介于该第一与该第二源极/漏极之间，并具有与该层间介电层上表面等高的上表面；
一接触垫，位于该层间介电层中及该第一金属硅化层之上；
一栅极延伸部，位于该绝缘结构上；以及
一端接接触部，电性连接该接触垫及该栅极延伸部。
6.如权利要求5所述的半导体结构，其特征在于，该接触垫的上表面与该第一晶体管的该栅极的上表面等高。
7.一种半导体结构，其特征在于，包括：
一晶体管，包括一源极/漏极；
一介电层，邻接该源极/漏极；
一导电图案，位于该介电层上，并具有一上表面实质上高于该源极/漏极的上表面；
一接触垫，位于该源极/漏极上，并电性连接至该源极/漏极；以及
一端接接触部，电性连接该接触垫与该导电图案。
8.如权利要求7所述的半导体结构，其特征在于，该接触垫的上表面实质上与该导电图案的上表面等高。
9.一种半导体结构的形成方法，其采用置换栅极工艺，其特征在于，包括如下步骤：
形成一晶体管，该晶体管具有一虚置栅极；
沉积一层间介电层并平坦化，该层间介电层的上表面高度与该虚置栅极的上表面等高；
移除该虚置栅极，形成一第一开口；
移除部分该层间介电层，形成一第二开口，且该第二开口至少露出该第一晶体管部分的源极/漏极；
以金属填满该第一开口形成该第一晶体管的一金属栅极，并同时以金属填满该第二开口形成一接触垫；以及
形成一端接接触部，其电性连接该接触垫与一浅沟槽绝缘区上的一栅极延伸部，且该浅沟槽绝缘区邻接该第一晶体管的源极/漏极。
10.如权利要求9所述的半导体结构的形成方法，其特征在于，还包括形成一金属硅化层的步骤，该金属硅化层位于该第一晶体管的源极/漏极之上及该接触垫之下。
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