CN103077887B - 半导体器件及其制造方法 - Google Patents
半导体器件及其制造方法 Download PDFInfo
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- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
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Abstract
公开了一种用于制造半导体器件的方法。在位于衬底上方的层间电介质(ILD)中的两个有源栅极部件之间形成伪栅极部件。在衬底中形成隔离部件,以及在隔离部件上方形成伪栅极部件。在衬底中的有源栅极部件的边缘处形成源极/漏极(S/D)部件,用于形成晶体管器件。所公开的方法提供了用于降低晶体管器件之间的寄生电容的改进方法。在实施例中,通过将物质引入到伪栅极部件内以增加伪栅极部件的电阻来实现这种改进的形成方法。本发明还提供了一种半导体器件。
Description
技术领域
本发明涉及集成电路制造,更具体而言,涉及具有应变结构的半导体器件。
背景技术
当诸如金属氧化物半导体场效应晶体管(MOSFET)的半导体器件通过各种技术节点按比例缩小时,将高k栅极介电层和金属栅电极层结合在MOSFET的栅极堆叠内,从而随部件尺寸的降低而改进器件性能。MOSFET工艺包括“后栅极”工艺,该工艺用金属栅电极替换原始多晶硅栅电极从而改进器件性能。
然而,在互补金属氧化物半导体(CMOS)制造中应用这些部件和工艺存在挑战。当器件之间的栅极长度和间隔减小时,加重了这些问题。例如,由于栅极堆叠之间的间隔减小,难以阻止MOSFET的栅极堆叠之间的寄生电容,从而影响器件性能。
因此,需要的是在半导体器件中制造栅极堆叠的改进了的方法。
发明内容
为了解决现有技术中存在的问题,根据本发明的一个方面,提供了一种用于制造半导体器件的方法,包括:在衬底上方的层间介电(ILD)层中形成第一栅极部件和第二栅极部件,其中,所述第一栅极部件和所述第二栅极部件具有第一电阻;将所述第一栅极部件转变成具有第二电阻的经处理的栅极部件,其中,所述第二电阻高于所述第一电阻;去除所述第二栅极部件以在所述ILD层中形成开口;以及在所述开口中形成导电栅极部件。
在上述方法中,其中,转变的步骤包括:对所述第一栅极部件实施处理;以及之后退火所述衬底。
在上述方法中,其中,转变的步骤包括:对所述第一栅极部件实施处理;以及之后退火所述衬底,其中,在约700℃至约1000℃的温度范围内,在约10秒至约30分钟的时间范围内实施退火。
在上述方法中,其中,转变的步骤包括:对所述第一栅极部件实施处理;以及之后退火所述衬底,其中,通过所述处理将含氧物质引入所述第一栅极部件中。
在上述方法中,其中,转变的步骤包括:对所述第一栅极部件实施处理;以及之后退火所述衬底,其中,采用离子注入工艺实施所述处理。
在上述方法中,其中,转变的步骤包括:对所述第一栅极部件实施处理;以及之后退火所述衬底,其中,采用离子注入工艺实施所述处理,其中,在约2KeV至约20KeV的能量范围内,采用约1E13atom/cm2至约1E17atom/cm2范围内的剂量实施所述离子注入工艺。
在上述方法中,其中,所述导电栅极部件是金属栅极。
在上述方法中,其中,所述经处理的栅极部件包含至少50%体积的氧化硅。
在上述方法中,其中,所述第一栅极部件和所述第二栅极部件包括位于高k介电层上方的多晶硅栅电极。
在上述方法中,其中,去除所述第二栅极部件的步骤是两步法干法蚀刻工艺,所述两步法干法蚀刻工艺包括去除位于多晶硅膜上方的本征氧化膜的第一步骤和去除所述多晶硅膜的第二步骤。
根据本发明的另一方面,还提供了一种用于制造半导体器件的方法,包括:在衬底上方形成第一多晶硅栅电极、第二多晶硅栅电极、和第三多晶硅栅电极,其中,所述第一多晶硅栅电极位于所述第二多晶硅栅电极和所述第三多晶硅栅电极之间;在所述第一多晶硅栅电极、所述第二多晶硅栅电极、和所述第三多晶硅栅电极内部和上方形成层间电介质(ILD);平坦化所述ILD以形成具有与所述第一多晶硅栅电极、所述第二多晶硅栅电极、和所述第三多晶硅栅电极的顶面基本上共平面的表面的经平坦化的ILD;将物质引入到所述第一多晶硅栅电极内;去除所述第二多晶硅栅电极和所述第三多晶硅栅电极以在所述ILD中形成第一开口和第二开口;在所述第一开口中形成用于p型金属氧化物半导体(PMOS)器件的第一金属栅电极;以及在所述第二开口中形成用于n型金属氧化物半导体(NMOS)器件的第二金属栅电极。
在上述方法中,进一步包括:在将物质引入到所述第一多晶硅栅电极内之后实施退火工艺。
在上述方法中,进一步包括:在将物质引入到所述第一多晶硅栅电极内之后实施退火工艺,其中,所述退火工艺将至少一部分所述第一多晶硅栅电极转变成氧化硅。
在上述方法中,其中,引入到所述第一多晶硅栅电极内的所述物质包括O2、O3、CO2、或其组合。
在上述方法中,其中,当去除所述第二多晶硅栅电极和所述第三多晶硅栅电极时,不去除所述第一多晶硅栅电极。
在上述方法中,其中采用离子注入工艺实施引入物质的步骤。
在上述方法中,其中采用离子注入工艺实施引入物质的步骤,其中,在约2KeV至约20KeV的能量范围内,采用约1E13atom/cm2至约1E17atom/cm2范围内的剂量实施所述离子注入工艺。
根据本发明的又一方面,还提供一种用于制造半导体器件的方法,包括:在衬底上方形成牺牲栅电极和伪栅电极;在所述牺牲栅电极和所述伪栅电极内形成层间电介质(ILD);将所述伪栅电极转变成经处理的伪栅电极,所述经处理的伪栅电极的电阻高于所述牺牲栅电极或所述伪栅电极的电阻;去除所述牺牲栅电极以在所述ILD中形成开口;以及在所述开口中形成用于有源器件的金属栅电极。
在上述方法中,其中将所述伪栅电极转变成经处理的伪栅电极的步骤包括:对伪栅电极实施处理;以及之后退火所述衬底。
在上述方法中,其中将所述伪栅电极转变成经处理的伪栅电极的步骤包括:对伪栅电极实施处理;以及之后退火所述衬底,其中,所述处理将含氧物质引入到所述伪栅电极内。
附图说明
当结合附图进行阅读时,根据下面详细的描述可以更好地理解本发明。应该强调的是,根据工业中的标准实践,对各种部件没有按比例绘制并且仅仅用于说明的目的。实际上,为了清楚讨论起见,各种部件的相对尺寸可以被任意增大或缩小。
图1是示出了根据本发明的各个方面制造包括栅极堆叠的半导体器件的方法的流程图;以及
图2至图10是根据本发明的各个方面的处于各个制造阶段的半导体器件的栅极堆叠的示意性剖面图。
具体实施方式
应当了解为了实施本发明的不同部件,以下公开内容提供了许多不同的实施例或实例。在下面描述元件和布置的特定实例以简化本发明。当然这些仅仅是实例并不打算限定。例如,在下面的描述中第一部件在第二部件上方或者在第二部件上的形成可以包括其中第一和第二部件以直接接触形成的实施例,并且也可以包括其中可以在第一和第二部件之间形成额外的部件,使得第一和第二部件可以不直接接触的实施例。此外,本发明可在各个实例中重复参照数字和/或字母。这种重复是为了简明和清楚的目的,而且其本身没有规定所讨论的各个实施例和/或结构之间的关系。
图1是示出了根据本发明的各个方面制造半导体器件的方法100的流程图。图2至图10示出了根据图1的方法100的实施例的处于各个制造阶段的半导体器件200的示意性剖面图。半导体器件200可以包括在微处理器、存储器单元、和/或其他集成电路(IC)中。注意到图1的方法并没有生产出完整的半导体器件200。可以采用互补金属氧化物半导体(CMOS)技术加工来制造完整的半导体器件200。因此,应该理解可以在图1的方法100之前、之中和之后提供其他工艺,并且一些其他工艺可能在本文中仅进行简述。而且,为了更好地理解本发明,简化了图1至图10。例如,尽管附图示出了半导体器件200,但是应该理解,IC可以包括许多其他器件,包括电阻器、电容器、电感器、熔丝等。
参考图1和图2,方法100开始于步骤102,在步骤102中,提供了衬底210。在一个实施例中,衬底210包括晶体硅衬底(例如,晶圆)。在可选实施例中,衬底210可以包括绝缘体上硅(SOI)结构。衬底210可以进一步包括有源区(未示出)。根据本领域中已知的设计要求,有源区可以包括各种掺杂结构。在一些实施例中,有源区可以掺杂有p型或n型掺杂剂。例如,有源区可以掺杂有p型掺杂剂,使用诸如硼或BF2的化学品来实施掺杂;n型掺杂剂,使用诸如磷或砷的化学品来实施掺杂;和/或其组合。有源区可以用作为N型金属氧化物半导体晶体管器件(称作NMOS)配置的区域和为P型金属氧化物半导体晶体管器件(称作PMOS)配置的区域。
在一些实施例中,在衬底210中形成隔离结构212,以隔离各个有源区。例如,采用诸如硅的局部氧化(LOCOS)或浅沟槽隔离(STI)的隔离技术来形成隔离结构212,从而限定并电隔离各个有源区。在本实施例中,隔离结构212包括STI。隔离结构212可以包括:氧化硅、氮化硅、氮氧化硅、氟掺杂的硅酸盐玻璃(FSG)、低K介电材料、本领域中已知的其他合适的材料、和/或其组合。可以通过任何合适的工艺形成隔离结构212。作为一个实例,STI的形成可以包括:通过光刻工艺图案化半导体衬底210、在衬底210中蚀刻沟槽(例如,通过采用干法蚀刻、湿法蚀刻、和/或等离子体蚀刻工艺)、以及用介电材料填充沟槽(例如,通过采用化学汽相沉积工艺)。在一些实施例中,经填充的沟槽可以具有多层结构,比如填充有氮化硅或氧化硅的热氧化物衬垫层。
仍参考图2,在至少一个实施例中,在衬底210的表面上方形成栅极堆叠240A、240B、和240C。在本实施例中,栅极堆叠240A、240B被设计用于形成有源器件,以及栅极堆叠240C是伪栅极堆叠。在本实施例中,伪栅极堆叠240C位于隔离结构212上方以及栅极堆叠240A和240B之间。在一些实施例中,栅极堆叠240A、240B和伪栅极堆叠240C中的每一个都包括依次位于衬底210上方的栅极介电部件214、栅电极部件216和硬掩模部件218。在一些实施例中,在衬底210上方依次沉积栅极介电层(未示出)、栅电极层(未示出)、和硬掩模层(未示出)。然后,在硬掩模层上方形成经图案化的感光层(未示出)。将感光层的图案转印到硬掩模层,然后转印到栅电极层和栅极介电层,从而形成栅极堆叠240A、240B和伪栅极堆叠240C。然后,通过干式剥离工艺和/或湿式剥离工艺来剥离感光层。
在一个实例中,栅极介电部件214是薄膜,该薄膜包含氧化硅、氮化硅、氮氧化硅、高k电介质、本领域中已知的其他合适的介电材料、或者其组合。高k电介质包括金属氧化物。用于高k电介质的金属氧化物的实例包括:Li、Be、Mg、Ca、Sr、Sc、Y、Zr、Hf、Al、La、Ce、Pr、Nd、Sm、Eu、Gd、Tb、Dy、Ho、Er、Tm、Yb、Lu的氧化物,以及其混合物。在本实施例中,栅极介电部件214包含厚度处于约10埃至约30埃范围内的高k介电层。可以采用合适的工艺比如原子层沉积(ALD)、化学汽相沉积(CVD)、物理汽相沉积(PVD)、热氧化、UV-臭氧氧化、或者其组合形成栅极介电部件214。在栅极介电部件214下方可以进一步包括界面层(未示出),从而减少栅极介电部件214和衬底210之间的可能损伤。界面层可以包含氧化硅。
在一些实施例中,位于栅极介电部件214上方的栅电极部件216可以包括单层或多层结构。在本实施例中,栅电极部件216可以包含多晶硅。此外,栅电极部件216可以为具有掺杂物质的掺杂多晶硅。在一个实施例中,栅电极部件216具有约30nm至约60nm范围内的厚度。可以采用诸如低压化学汽相沉积(LPCVD)、等离子体增强化学汽相沉积(PECVD)、其他合适的工艺、或者其组合的工艺形成栅电极部件216。在一个实施例中,在CVD工艺中使用硅烷(SiH4)作为化学气体来形成栅电极部件216。在其他实施例中,栅电极部件216和/或栅极介电部件214可以是牺牲层,并将在后续工艺中通过替换步骤去除掉。
在一些实施例中,位于栅电极部件216上方的硬掩模部件218包含氧化硅。可选地,硬掩模部件218可以包含氮化硅、氮氧化硅、和/或其他合适的介电材料,并且可以采用诸如CVD或PVD的方法形成硬掩模部件218。在一些实施例中,硬掩模部件218具有处于约100埃至约800埃范围内的厚度。
参考图1和图3,方法100继续到步骤104,在步骤104中,毗连栅极堆叠240A、240B、以及伪栅极堆叠240C的相对侧壁形成栅极间隔件220。在一些实施例中,栅极间隔件220可以包括单层或多层结构。在本实施例中,通过沉积工艺(包括CVD、PVD、ALD、或者其他合适的技术)在栅极堆叠240A、240B、以及伪栅极堆叠240C的内部和上方形成均厚间隔材料层(未示出)。在一些实施例中,间隔材料包括:氧化硅、氮化硅、氮氧化硅、其他合适的材料、或者其组合。在一些实施例中,间隔材料具有处于约5nm至约15nm范围内的厚度。然后,对间隔材料实施各向异性蚀刻工艺,以形成栅极间隔件220。在一些实施例中,栅极间隔件220的高度小于栅极堆叠240A、240B、以及伪栅极堆叠240C的高度。在实施例中,栅极间隔件220毗连栅极介电部件214和栅电极部件216的侧壁,但暴露出硬掩模部件218的侧壁。
参考图1和图4,方法100继续到步骤106,在步骤106中在衬底210中形成源极/漏极(S/D)部件222和224。在一个实施例中,对栅极堆叠240A配置源极/漏极(S/D)部件222用于PMOS器件,以及对栅极堆叠240B配置源极/漏极(S/D)部件224用于NMOS器件。S/D部件222的形成工艺可以从在位于栅极堆叠240A任一侧的衬底210中形成凹进腔(未示出)开始。在本实施例中,采用各向同性干法蚀刻工艺然后接着采用各向异性湿法或干法蚀刻工艺来形成凹进腔。在实施例中,生长应变材料以填充凹进腔,从而形成S/D部件222。在一些实施例中,应变材料的生长工艺包括选择性外延生长(SEG)、交错沉积和蚀刻(cyclicdepositionandetching)(CDE)、化学汽相沉积(CVD)技术(例如,汽相外延(VPE)和/或超高真空CVD(UHV-CVD))、分子束外延(MBE)、本领域中已知的其他合适的外延工艺、或其组合。在一些实施例中,应变材料是硅锗(SiGe)。在一些实施例中,应变材料是具有p型掺杂剂(比如硼)的外延SiGe。
在实施例中,通过一种或多种离子注入工艺在位于栅极堆叠240B任一侧的衬底210中形成S/D部件224。在设计的注入能量和倾斜角满足器件性能要求的情况下,例如采用n型掺杂剂(比如磷或砷)实施注入。在可选实施例中,S/D部件224包括具有n型掺杂剂的外延硅(Si)。用于形成外延Si的工艺可以包括在衬底210中形成凹进腔(未示出)然后用外延Si填充凹进腔的一些蚀刻工艺。外延Si的生长工艺包括SEG、CDE、CVD技术、MBE、本领域中已知的其他合适的外延工艺、或其组合。
参考图1和图5,方法100继续到步骤108,在步骤108中,通过蚀刻工艺从栅极堆叠240A、240B以及伪栅极堆叠240C去除硬掩模部件218。蚀刻工艺可以包括例如采用干法蚀刻、湿法蚀刻、和/或等离子体蚀刻工艺。在一些实施例中,使用NF3气体和/或氩气,分别以处于约10sccm至约100sccm和约10sccm至约200sccm的范围内的流速实施蚀刻工艺。在一些实施例中,在约10mTorr至约100mTorr范围内的真空压强下,采用大于约60V的RF偏压实施蚀刻工艺的第一步骤。在一些实施例中,RF偏压处于约60V和约200V之间。去除硬掩模部件218的步骤可以降低栅极堆叠240A、240B和伪栅极堆叠240C的高度;从而降低了栅极堆叠240A、240B和伪栅极堆叠240C之间的间隙的纵横比。降低的纵横比有助于后续的间隙填充工艺。
参考图1和图6,方法100继续到步骤110,在步骤110中,在栅极堆叠240A、240B和伪栅极堆叠240C内形成层间电介质(ILD)226。ILD226可以包括诸如氧化物、氮化物、氮氧化物、低k介电材料、超低k介电材料、极低k介电材料、其他介电材料、和/或其组合的材料。在一些实施例中,通过在栅极堆叠240A、240B和伪栅极堆叠240C内部和上方沉积ILD层(未示出),形成ILD226,然后,应用平坦化工艺去除位于栅极堆叠240A、240B和伪栅极堆叠240C上方的ILD层部分。在一些实施例中,沉积ILD层的步骤包括CVD工艺、HDPCVD工艺、HARP、旋涂工艺、其他沉积工艺、和/或其任何组合。在一些实施例中,平坦化工艺包括化学机械抛光(CMP)工艺、干法蚀刻工艺、湿法蚀刻工艺、和/或其组合。平坦化工艺可以形成具有与栅极堆叠240A、240B和伪栅极堆叠240C的顶面基本上共平面的顶面的ILD226。
参考图1和图7,方法100继续到步骤112,在步骤112中对伪栅极堆叠240C提供处理230,之后,栅电极部件216被转变成经处理的栅电极部件216’。可以通过离子注入工艺或者本领域中已知的其他合适的工艺(包括热扩散、等离子体、电子束、紫外(UV)、或其组合)提供处理230的能量源。在实施例中,处理230将含氧物质(包括O2、O3、CO2、或其组合)引入到栅电极部件216内以形成经处理的栅电极部件216’。在一个实施例中,在整个经处理的栅电极部件216’内分布含氧物质。在可选实施例中,至少50%体积的经处理的栅电极部件216’含有含氧物质。在一些实施例中,处理230是在约2KeV至约20KeV范围内的能量下实施的离子注入工艺。在一些实施例中,处理230是用约1E13atoms/cm2和约1E17atoms/cm2范围内的剂量实施的离子注入工艺。栅极堆叠240A和240B未被处理230转变,因为栅极堆叠240A和240B被保护件228(例如,光刻胶图案)覆盖。在一些实施例中,在处理230后通过剥离工艺去除保护件228。
参考图1和图8,方法100继续到步骤114,在步骤114中,对衬底210实施退火工艺232。在一些实施例中,实施退火工艺232用于扩散和/或活化在经处理的栅电极部件216’中分布的物质。在一个实施例中,在约700℃至约1000℃的温度范围内实施退火工艺232,持续约10秒至约30min的时间范围。在一些实施例中,通过炉工艺、RTA(快速热退火)工艺、快速退火(flashanneal)、或本领域中已知的其他合适的工艺实施退火工艺232。在一些实施例中,退火工艺232通过引起经处理的栅电极部件216’中的含氧物质和多晶硅之间的化学反应来氧化经处理的栅电极部件216’。在一个实施例中,在退火工艺232之后多晶硅完全被氧化,从而形成由氧化硅组成的经处理的栅电极部件216’。在可选实施例中,在退火工艺232之后至少50%体积的多晶硅被氧化,从而形成由至少50%的氧化硅和多晶硅组成的经处理的栅电极部件216’。处理230和/或退火工艺232可以形成具有比栅电极部件216更高的电阻或更低的电导率的经处理的栅电极部件216’。
参考图1和图9,方法100继续到步骤116,在步骤116中,实施去除工艺以去除栅极堆叠240A和240B,从而分别在ILD226中形成开口236和238。经处理的栅电极部件216’通过在其上提供保护件234(例如,光刻胶图案)而未在去除工艺中被去除掉。在实施例中,如果栅极介电部件214包含高k介电材料,则去除工艺去除栅极堆叠240A和240B中的栅电极部件216,但留下栅极堆叠240A和240B的栅极介电部件214。在可选实施例中,如果栅极介电部件214不是由高k介电材料组成,则去除工艺去除栅极堆叠240A和240B的栅电极部件216和栅极介电部件214。去除工艺可以包括干法蚀刻工艺和/或湿法蚀刻工艺。在一些实施例中,去除工艺是两步法干法蚀刻工艺,其包括破除(去除)位于栅电极部件216上方的本征氧化物(nativeoxide)(未示出)的第一步骤,和去除栅电极部件216(例如,多晶硅)的第二步骤。在一些实施例中,使用NF3气体和/或氩气,分别以处于约10sccm至约100sccm和约10sccm至约200sccm的范围内的流速实施蚀刻工艺的第一步骤。在一些实施例中,在处于约10mTorr至约100mTorr范围内的真空压强下,采用大于约60V的RF偏压实施蚀刻工艺的第一步骤。在一些实施例中,RF偏压处于约60V和约200V之间。使用例如Cl气体、HBr气体、He气体、或其组合实施蚀刻工艺的第二步骤。在本实施例中,Cl气体、HBr气体、和He的流速分别处于约10accm至约100sccm、约200sccm至约400sccm、和约100sccm至约300sccm的范围内。在一些实施例中,用小于实施蚀刻工艺第一步骤的RF偏压的RF偏压实施蚀刻工艺的第二步骤。用于实施蚀刻工艺的第二步骤的RF偏压是例如处于约60V和约200V之间的范围内。在一些实施例中,在处于约10mTorr至约100mTorr范围内的真空压强下实施蚀刻工艺的第二步骤。之后通过剥离工艺去除保护件234。
参考图1和图10,方法100继续到步骤118,在步骤118中,分别在开口236和238中形成金属栅极244和242。形成金属栅极244和242以替换栅极堆叠240A和240B的栅电极部件216(即,多晶硅栅极层)。如上面所提及的,栅极堆叠240A被设计用于PMOS器件以及栅极堆叠240B被设计用于NMOS器件。金属栅极244具有用于PMOS器件的第一功函数,以及金属栅极242具有用于NMOS器件的第二功函数。在一些实施例中,金属栅极244和242包含任何合适的材料,包括铝、铜、钨、钛、钽、钽铝、氮化钽铝、氮化钛、氮化钽、硅化镍、硅化钴、银、TaC、TaSiN、TaCN、TiAl、TiAlN、WN、金属合金、本领域中已知的其他合适的材料、和/或其组合。
后续加工可以在衬底上形成被配置用于连接半导体器件的各个部件或结构的各种接触件/通孔/线和多层互连部件(例如,金属层和层间电介质)。额外的部件可以提供与器件的电连接。例如,多层互连包括纵向互连件,比如常规通孔或接触件;和横向互连件,比如金属线。各种互连部件可以应用各种导电材料,包括铜、钨、和/或硅化物。在一个实例中,采用镶嵌和/或双镶嵌工艺来形成与铜相关的多层互连结构。
上面所讨论的本发明的各个实施例提供了优于常规方法的优点,可以理解无特定的优点是所有实施例所必需的,并且不同的实施例可以提供不同的优点。优点之一是相邻的导电栅极之间的间隔增大了,从而降低了晶体管器件之间的寄生电容。因此,可以增强器件运行速度,从而提升器件性能。另一个优点是可以降低击穿ILD和/或器件故障的可能性。
在一个实施例中,一种用于制造半导体器件的方法包括:在衬底上方的层间介电(ILD)层中形成第一栅极部件和第二栅极部件,其中,第一栅极部件和第二栅极部件具有第一电阻;将第一栅极部件转变成具有第二电阻的经处理的栅极部件,其中,第二电阻高于第一电阻;去除第二栅极部件以在ILD层中形成开口;以及在开口中形成导电栅极部件。
在另一个实施例中,一种用于制造半导体器件的方法包括:在衬底上方形成第一多晶硅栅电极、第二多晶硅栅电极、和第三多晶硅栅电极,其中,第一多晶硅栅电极位于第二多晶硅栅电极和第三多晶硅栅电极之间;在第一多晶硅栅电极、第二多晶硅栅电极、和第三多晶硅栅电极内部和上方形成层间电介质(ILD);平坦化ILD以形成具有与第一多晶硅栅电极、第二多晶硅栅电极、和第三多晶硅栅电极的顶面基本上共平面的表面的经平坦化的ILD;将物质引入到第一多晶硅栅电极内;去除第二多晶硅栅电极和第三多晶硅栅电极以在ILD中形成第一开口和第二开口;在第一开口中形成第一金属栅电极用于PMOS器件;以及在第二开口中形成第二金属栅电极用于NMOS器件。
在又一个实施例中,一种用于制造半导体器件的方法包括:在衬底上方形成牺牲栅电极和伪栅电极;在牺牲栅电极和伪栅电极内形成层间电介质(ILD);将伪栅电极转变成具有高于牺牲栅电极或伪栅电极的电阻的电阻的经处理的伪栅电极;去除牺牲栅电极以在ILD中形成开口;以及在开口中形成金属栅电极用于有源器件。
虽然通过实例和根据优选的实施例描述了本发明,但是应理解本发明不限于所公开的实施例。相反地,本发明意图涵盖各种改进和相似的布置(对本领域的技术人员来说显而易见的)。因此,所附权利要求的范围应与最广泛的解释一致以涵盖所有这些改进和相似的布置。
Claims (19)
1.一种用于制造半导体器件的方法,包括:
在衬底上方的层间介电(ILD)层中形成第一栅极部件和第二栅极部件,其中,所述第一栅极部件和所述第二栅极部件具有第一电阻;
将所述第一栅极部件转变成具有第二电阻的经处理的栅极部件,其中,所述第二电阻高于所述第一电阻,所述经处理的栅极部件包含至少50%体积的氧化硅;
去除所述第二栅极部件以在所述层间介电层中形成开口;以及
在所述开口中形成导电栅极部件。
2.根据权利要求1所述的方法,其中,转变的步骤包括:
对所述第一栅极部件实施处理;以及
之后退火所述衬底。
3.根据权利要求2所述的方法,其中,在700℃至1000℃的温度范围内,在10秒至30分钟的时间范围内实施退火。
4.根据权利要求2所述的方法,其中,通过所述处理将含氧物质引入所述第一栅极部件中。
5.根据权利要求2所述的方法,其中,采用离子注入工艺实施所述处理。
6.根据权利要求5所述的方法,其中,在2KeV至20KeV的能量范围内,采用1E13atom/cm2至1E17atom/cm2范围内的剂量实施所述离子注入工艺。
7.根据权利要求1所述的方法,其中,所述导电栅极部件是金属栅极。
8.根据权利要求1所述的方法,其中,所述第一栅极部件和所述第二栅极部件包括位于高k介电层上方的多晶硅栅电极。
9.根据权利要求1所述的方法,其中,去除所述第二栅极部件的步骤是两步法干法蚀刻工艺,所述两步法干法蚀刻工艺包括去除位于多晶硅膜上方的本征氧化膜的第一步骤和去除所述多晶硅膜的第二步骤。
10.一种用于制造半导体器件的方法,包括:
在衬底上方形成第一多晶硅栅电极、第二多晶硅栅电极、和第三多晶硅栅电极,其中,所述第一多晶硅栅电极位于所述第二多晶硅栅电极和所述第三多晶硅栅电极之间;
在所述第一多晶硅栅电极、所述第二多晶硅栅电极、和所述第三多晶硅栅电极内部和上方形成层间电介质(ILD);
平坦化所述层间电介质以形成具有与所述第一多晶硅栅电极、所述第二多晶硅栅电极、和所述第三多晶硅栅电极的顶面共平面的表面的经平坦化的层间电介质;
将物质引入到所述第一多晶硅栅电极内;
去除所述第二多晶硅栅电极和所述第三多晶硅栅电极以在所述层间电介质中形成第一开口和第二开口;
在所述第一开口中形成用于p型金属氧化物半导体(PMOS)器件的第一金属栅电极;以及
在所述第二开口中形成用于n型金属氧化物半导体(NMOS)器件的第二金属栅电极。
11.根据权利要求10所述的方法,进一步包括:
在将物质引入到所述第一多晶硅栅电极内之后实施退火工艺。
12.根据权利要求11所述的方法,其中,所述退火工艺将至少一部分所述第一多晶硅栅电极转变成氧化硅。
13.根据权利要求10所述的方法,其中,引入到所述第一多晶硅栅电极内的所述物质包括O2、O3、CO2或它们的组合。
14.根据权利要求10所述的方法,其中,当去除所述第二多晶硅栅电极和所述第三多晶硅栅电极时,不去除所述第一多晶硅栅电极。
15.根据权利要求10所述的方法,其中采用离子注入工艺实施引入物质的步骤。
16.根据权利要求15所述的方法,其中,在2KeV至20KeV的能量范围内,采用1E13atom/cm2至1E17atom/cm2范围内的剂量实施所述离子注入工艺。
17.一种用于制造半导体器件的方法,包括:
在衬底上方形成牺牲栅电极和伪栅电极,其中,所述伪栅电极位于所述衬底中的隔离结构的顶部上方;
在所述牺牲栅电极和所述伪栅电极内形成层间电介质(ILD);
将所述伪栅电极转变成经处理的伪栅电极,所述经处理的伪栅电极的电阻高于所述牺牲栅电极或所述伪栅电极的电阻;
去除所述牺牲栅电极以在所述层间电介质中形成开口;以及
在所述开口中形成用于有源器件的金属栅电极。
18.根据权利要求17所述的方法,其中将所述伪栅电极转变成经处理的伪栅电极的步骤包括:
对伪栅电极实施处理;以及
之后退火所述衬底。
19.根据权利要求18所述的方法,其中,所述处理将含氧物质引入到所述伪栅电极内。
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US8093116B2 (en) * | 2008-10-06 | 2012-01-10 | Taiwan Semiconductor Manufacturing Company, Ltd. | Method for N/P patterning in a gate last process |
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CN101106131A (zh) * | 2005-12-27 | 2008-01-16 | 台湾积体电路制造股份有限公司 | 半导体结构及其形成方法 |
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US20140203372A1 (en) | 2014-07-24 |
US9437434B2 (en) | 2016-09-06 |
US8703594B2 (en) | 2014-04-22 |
CN103077887A (zh) | 2013-05-01 |
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