TW434908B - Manufacturing method of metal oxide semiconductor transistor - Google Patents

Manufacturing method of metal oxide semiconductor transistor Download PDF

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Publication number
TW434908B
TW434908B TW088121807A TW88121807A TW434908B TW 434908 B TW434908 B TW 434908B TW 088121807 A TW088121807 A TW 088121807A TW 88121807 A TW88121807 A TW 88121807A TW 434908 B TW434908 B TW 434908B
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Taiwan
Prior art keywords
gate
layer
manufacturing
item
plasma
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TW088121807A
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Chinese (zh)
Inventor
Jeng-Hung Li
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United Semiconductor Corp
United Microelectronics Corp
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Priority to TW088121807A priority Critical patent/TW434908B/en
Priority to US09/488,303 priority patent/US20020048939A1/en
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Publication of TW434908B publication Critical patent/TW434908B/en

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/49—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET
    • H01L29/4983—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET with a lateral structure, e.g. a Polysilicon gate with a lateral doping variation or with a lateral composition variation or characterised by the sidewalls being composed of conductive, resistive or dielectric material
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • H01L21/28008—Making conductor-insulator-semiconductor electrodes
    • H01L21/28017—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon
    • H01L21/28026—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor
    • H01L21/28035—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor the final conductor layer next to the insulator being silicon, e.g. polysilicon, with or without impurities
    • H01L21/28044—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor the final conductor layer next to the insulator being silicon, e.g. polysilicon, with or without impurities the conductor comprising at least another non-silicon conductive layer
    • H01L21/28052—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor the final conductor layer next to the insulator being silicon, e.g. polysilicon, with or without impurities the conductor comprising at least another non-silicon conductive layer the conductor comprising a silicide layer formed by the silicidation reaction of silicon with a metal layer
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • H01L21/283—Deposition of conductive or insulating materials for electrodes conducting electric current
    • H01L21/285—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation
    • H01L21/28506—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers
    • H01L21/28512—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers on semiconductor bodies comprising elements of Group IV of the Periodic Table
    • H01L21/28518—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers on semiconductor bodies comprising elements of Group IV of the Periodic Table the conductive layers comprising silicides
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/665—Unipolar field-effect transistors with an insulated gate, i.e. MISFET using self aligned silicidation, i.e. salicide
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/49—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET
    • H01L29/4916—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET the conductor material next to the insulator being a silicon layer, e.g. polysilicon doped with boron, phosphorus or nitrogen
    • H01L29/4925—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET the conductor material next to the insulator being a silicon layer, e.g. polysilicon doped with boron, phosphorus or nitrogen with a multiple layer structure, e.g. several silicon layers with different crystal structure or grain arrangement
    • H01L29/4933—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET the conductor material next to the insulator being a silicon layer, e.g. polysilicon doped with boron, phosphorus or nitrogen with a multiple layer structure, e.g. several silicon layers with different crystal structure or grain arrangement with a silicide layer contacting the silicon layer, e.g. Polycide gate

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Manufacturing & Machinery (AREA)
  • Ceramic Engineering (AREA)
  • Chemical & Material Sciences (AREA)
  • Chemical Kinetics & Catalysis (AREA)
  • Insulated Gate Type Field-Effect Transistor (AREA)

Abstract

This invention is about manufacturing method of metal oxide semiconductor transistor. A layer of plasma enhanced silicon oxide with a low step coverage is formed in between the gate spacer and polysilicon gate. Using the characteristic of plasma enhanced silicon oxide layer for forming the suspending protrusion at the peak corner position of polysilicon gate, an opening with a wide-top and narrow-bottom structure is formed between gate spacer and polysilicon gate after part of plasma enhanced silicon oxide layer is removed. After that, a metal silicide process is performed to form a metal silicide layer on the exposed surface of heavily doped source/drain regions and polysilicon gate.

Description

經濟部智慧財產局員工消費合作社印製 3499g ^ A7 5491twf.doc/008 gy ' 五、發明說明（f ) 本發明是有關於一種半導體元件的製造方法，且特別 是有關於一種金氧半（Metal-Oxide-Semiconductor，MOS) 電晶體的製造方法。 在深次微米的積體電路技術中，由於積集度提高，在 線寬、接觸面積及接面深度等都逐漸縮小的情形下，爲了‘ 能有效地提高元件的工作品質，降低電阻並減少電阻及電 容^ 造因此在製作 M<5s 電晶體時傾向於使用金屬矽化合物（Silicide)，來降 矽閘極與源極/汲極的接觸電阻。由於金屬矽化<物的製程 中不需要微影，故由此類製程製作之金屬矽化物又稱爲自 行對準金屬矽化物（Self-aligned Silicide，Salicide)。常見 的自行對準金屬矽化物例如矽化鈦(TiSix)g矽化勢(Cogix) 等。因矽化鈦具有較低電阻及製^上較易控制等優點，所 以成爲目前最常被採用之金屬矽化物材料。 政化鈦層具有高霞阻介屬態Xmetastable、相巧化 駄(C43^XiSi->)^i£ff|S 熱穩態Xth^rmodynamically stable)之 C54相砭化鈦(C54-TiSi2)兩種結構，而第一段快速加熱製 程主要形成C49相與少部分C54相混合而成的矽化鈦層 (TiSi2)。之後，移除未反應的鈦金屬層。而第二階段的快 速加熱製程則提高溫度，在同樣的環境下快速加熱回火， 使矽化鈦層由高電阻的C49相矽化鈦轉變成低電阻的C54 相矽化鈦。 C49相砂化鈦的阻値較高且其生成(formation)溫度較 低。而C54相矽化鈦的電阻較低，但是其生成溫度較高。 3 (請先閱讀背面之注意事項再填寫本頁) ., · .·、1^ -.裝 *-----—訂---------綠.：'1. _h- _r 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐） A7 B7 434908 5491 twf.doc/008 五、發明說明（7/ > 通常在製程中會以快速加熟製程法，使矽化鈦由高電阻的 C49相轉變成(transformation)低電阻的C54相。爲使金屬 與矽反應產生較厚、品質較均勻之金屬矽化物，必須提高 熱製程溫度或延長熱製程時間 隨著複晶矽閘極尺寸的日漸縮小，C54相矽化鈦的生' 成溫度會受窄線效應(narrow line effect)的影響而上升。所 請的窄線效應就是指線寬（linewidth)與相轉變温度（phase transformation temperature)的關係，線寬愈小，矽化鈦由高 .- — 電阻的祖£5¾相轉變溫度就Printed by the Consumer Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs 3499g ^ A7 5491twf.doc / 008 gy 'V. Description of the Invention (f) The present invention relates to a method for manufacturing a semiconductor device, and in particular to a metal-oxygen half (Metal -Oxide-Semiconductor (MOS) transistor manufacturing method. In the deep sub-micron integrated circuit technology, due to the increase in the accumulation degree, the line width, contact area, and junction depth are gradually reduced. In order to 'effectively improve the working quality of components, reduce resistance and reduce resistance Therefore, in the manufacture of M < 5s transistors, metal silicon compounds (silicides) are used to reduce the contact resistance between the silicon gate and the source / drain. Since lithography is not required in the process of metal silicide < objects, metal silicides produced by such processes are also called self-aligned silicides (Salicide). Common self-aligned metal silicides such as titanium silicide (TiSix) g silicide potential (Cogix) and so on. Titanium silicide has become the most commonly used metal silicide material because of its lower resistance and easier controllability. The political titanium layer has a high-resistance dielectric state Xmetastable, and a coincidence (C43 ^ XiSi- >) ^ i £ ff | S thermally stable Xth ^ rmodynamically stable C54 phase titanium (C54-TiSi2) Two structures, and the first stage of the rapid heating process mainly forms a titanium silicide layer (TiSi2) composed of a mixture of C49 phase and a small amount of C54 phase. After that, the unreacted titanium metal layer is removed. In the second stage, the rapid heating process increases the temperature and rapidly heats and tempers under the same environment, so that the titanium silicide layer is transformed from high-resistance C49 titanium silicide to low-resistance C54 titanium silicide. C49-phase sanded titanium has high resistance and low formation temperature. The C54 titanium silicide has lower resistance, but its temperature is higher. 3 (Please read the precautions on the back before filling out this page)., ···, 1 ^-. Install * -----— Order --------- Green .: '1. _h- _r This paper size applies the Chinese National Standard (CNS) A4 specification (210 X 297 mm) A7 B7 434908 5491 twf.doc / 008 V. Description of the invention (7 / > In the manufacturing process, the fast-cooking process is usually used. The titanium silicide is transformed from the high-resistance C49 phase to the low-resistance C54 phase. In order for the metal to react with silicon to produce a thicker and more uniform metal silicide, the thermal process temperature must be increased or the thermal process time must be extended The size of complex silicon gates is shrinking, and the temperature at which C54 phase titanium silicide is grown will be affected by the narrow line effect. The narrow line effect is the line width and phase transition. The relationship between phase transformation temperature, the smaller the line width, the higher the titanium silicide.

—· - I 愈高。此時若要提高RTP製程的溫度以生成C54相矽化鈦， 又會使得形成的矽化鈦性質不穩定，無法在小尺寸元件中 使用’且反應溫度不易控制，而易有側面生長（lateral growth) 的現象發生，故當元件的積集度增加，尺寸縮小時，側面 生長便容易造成閘極與源極/汲極區之間的橋接(bridge)現 象。爲了避免此橋接的現象，故又導致反應溫度無法提昇， 造成於窄線(narrow line)時複晶矽閘極的阻値容易偏高^ 因此本發明提供一種金氧半電晶體的製造方法，可增 &矽化金屬層的形成面t，鸯爱皇隸效應所導致的弁 高問覊_：同時可以避免閘極與源極/M區之間的槁培 本發明提供一種金氧半電晶體的製造方法，適用於矽 基底。此方法包括於基底上形成複晶矽閘極。接著於複晶 矽閘極兩側之基底中形成輕摻雜源極/汲極區。然後於複 晶矽閘極與基底上覆蓋一層電漿加強氧化矽層。之後於電 漿加強氧化矽層上覆蓋一層間隙壁材料層，如氮化政層。 4 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐） (請先閱讀背面之注意事項再填寫本頁) . , Λ 裝---I I I 丨訂---------綠. 經濟部智慧財產局員工消費合作社印製 434§〇 549 1 twf,doc/008 A7 B7 經濟部智慧財產局員工消費合作社印製 五、發明說明u ) 接著去除部分間隙壁材料層，以形成閘極間隙壁。然後去 除複晶矽閘極與基底上之電漿加強氧化矽層，並且去除部 分在閘極間隙壁與複晶矽閘極之間的電漿加強氧化矽層， 以在閘極間隙壁與複晶矽閘極之間形成缺口，其中缺口上 部的寬度大於缺口下部的寬度。之後在閘極間隙壁兩側之 基底中形成重摻雜源極/汲極區。然後進行矽化金屬製程， 在重摻雜源極/汲極區與複晶矽閘極暴露表面形成一層矽 化金屬層。 依照本發明在閘極間隙壁與g晶g閘極之.趾形成上I 下窄的缺口，'一以增加闊極形成砂化盒屬層 積，避免窄線效應所導致的阻値升高問題，同時可以避¥ -^極與源極/汲福jg之一 爲讓本發明之上述和其他目的、特徵、和優點能更明 顯易懂，下文特舉一較佳實施例，並配合所附圖式，作詳 細說明如下： 圖式之簡單 第1A圖至第是繪示依照本發明一較佳實施例之 金氧半電晶體的面示意圖。 第2圖是繪示^士!：圖中，區域200之局部放大圖。 圖式之標記說明： … 10 :矽基底 12 :淺溝渠隔離 14 =閘極氧化層 16 :閘極複晶矽層 5 (請先閱讀背面之注意事項再填寫本頁) '裴--------訂---------0, 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐） 經濟部智慧財產局員工消費合作社印^ 4'349©g ； 、 A7 5491twf.doc/008 B7 ' 五、發明說明（屮） 18、18a :輕摻雜源極/汲極區 20、20a :電漿加強氧化矽層 22:間隙壁材料層 22a:閘極間隙壁 24:重摻雜源極/汲極區 26 :矽化金屬層 28 :砂化金屬層 50 :懸突 52 :缺口 wl :上部寬度 w2 :下部寬度 較佳實施例 請參照第1A圖，提供一矽基底10。接著在基底1〇中 形成元件隔離結構，如淺溝渠隔離結構12。然後在基底1〇 上製作複晶矽閘極，其包括由下而上堆疊之閘極氧化層14 與閘極複晶矽層16。之後在複晶矽閘極兩側之基底10中 形成輕摻雜源極/汲極區（LDD)18。至於其製作方法皆爲熟 習此技藝者所熟知之技術，故於此不在贅述。 請參照第1B圖，接著利用電漿加強化學氣相沉積法 (PECVD)，在攝氏溫度小於500度，壓力約在大氣壓力 (Atmospheric pressure)下，於基底10與複晶砂閘極上覆蓋 一層厚度韵40£L埃左右跑橥層（PE-oxide)4〇 0 由趁在JlM件下班里成之雷漿加強氣业矽層20具有較差 之I梯覆蓋（step coverage)，並且會在複晶矽閘極^頂角 6 (請先閱讀背面之注意事項再填窝本頁) l·, ! I I I I 1 訂-----ml 綠 本纸張尺度適用中國國家標準（CNS)A4規格（21Q x 297公爱） B7 549 1 twf.doc/008 五、發明說明（) 處形成懸突（〇verhang)50的現象，故而在複晶矽閘極側壁 上所沉積的電漿加強氧化矽層20會有上部寬而下部窄的 情形。 _ 然後在電漿加強氧化矽層20覆蓋一層間隙壁材料層 22，所形成之間隙壁材料層22必須對電漿加強氧化矽層‘ 具有蝕刻選擇性（selectivity)，例如是以低壓化學氣相沉積 法(LPCVD)所形成之氮化矽層。 請參照第1C圖，接著進行間隙壁回蝕刻(etch back)製 程，比如利用反應性離子蝕刻法(RIE)，進行非等向性乾蝕 刻，在複晶矽閘極之側壁上（隔著電漿加強氧化矽層20)形 成閘極間隙壁22a。然後轉變蝕刻條件，使用蝕刻氧化矽 層之蝕刻劑，如氟碳化合物（CFX)，去除在複晶矽閘極與 基底10上之電漿加強氧化矽層20，並且同時去除部分在 閘極間隙壁22a與複晶矽閘極之間的電漿加強氧化矽層 2〇，藉以在閘極間隙壁22a與基底10之間，以及在閘極 間隙壁22a與複晶矽閘極之間，留下部分電漿加強氧化矽 層22a，作爲緩衝層(buffer layer)，並且在蘭極間隙壁22a 與複晶矽閘極之間形成缺口 52,增加閘極複晶矽層16暴 露的面積。 請參照第2圖，其繪示第1C圖中區域200之局部放 大圖。如圖所示，缺口 52係形成於閘極間隙壁22a與閛 極複晶矽層16之間，並且爲上寬下窄的缺口。亦即缺口 52 的上部寬度wl大於缺口 52的下部寬度w2。 接著請參照第1D圖，使用離子植入法，在閘極間隙 本紙張尺度適用中國國家標準（CNS)A4規格（210 κ 297公釐） f請先閲讀背面之注項再填寫本頁) 裝·----!| 訂'---— — — — — 線 經濟部智慧財產局員工消費合作社印製 A7 B7 434f0g 5491twf,doc/008 五、發明說明（t ) 壁22a兩側之基底1〇中形成重摻雜源極/汲極區24。然後 進行矽化金屬製程，藉以在重摻雜源極/汲極區24與複晶 矽閘極(即閘極複晶矽層16)暴露表面分別形成矽化金屬層 26與28。矽化金屬層26與28例如是矽化鈦(TiSix)層或 是矽化鈷（C〇Six)層。以矽化鈦層爲例，其形成方法例如以‘ 濺鍍法（Sputtering)在基底10表面形成一層鈦金屬層，然 後進行第一段快速回火（RTA1)，使接觸介面之鈦金屬與矽 反應形成一層主要爲C49相之矽化鈦層。之後使用溼式蝕 刻，例如使用成份包括氫氧化銨(NH4OH)、過氧化氫(h2o2) 及熱去離子水（Hot De-Ionization Water，HDIW)等的 RCA 落液淸除，去除表面未反應之金屬欽。接著進行第二段快 速回火（RTA2)，使矽化鈦層轉變成具有較低電阻之C54相 結構。 由於本發明在閘極間隙壁22a與閘極複晶矽層16之間 形成缺口 52，增加閘極複晶矽層16暴露的面積，如此即 增加了矽化金屬層28的形成面積，故可避免窄線效應所 導致的阻値升高的問題。另外，由於缺口 52係爲上寬下 窄之輪廓，可以有利於矽化金屬層28的生成，而且所形 成之矽化金屬層28的厚度只要小於缺口 52的上部寬度 wl，砂化金屬層28更不容易長過閘極間隙壁22a，可以 有效地防止側面生長情形發生’故可避免複晶矽閘極與源 極/汲極區之間的橋接。 請參照第1E圖’在基底10上覆蓋一層絕緣層30，作 爲內層介電層。絕緣層30的形成例如是沉積一層氧化矽 8 本紙張尺度適用中國國家標準（CNS)A4規格（210 x 297公愛） (請先閲讀背面之注意事項再填窝本頁) ... '1 '裝！----訂！·--------線 經濟部智慧財產局員工消費合作法印製 五、發明說明Π ) 層，然後再塗佈低介電吊數材料層，如旋塗式玻.璃(S0G) 或是旋塗式聚合物(SOP)等。接著在絕緣層3〇中形成導電 插塞32，電性連接至矽化金屬層26，至於其形成方法例 如先以微影及触刻技術形成插塞開口，然後在塡入導電材 料即可形成導電插塞32。 / 由上述本發明較佳實施例可知，應用本發明可以增加 閘極形成矽化金屬層的面積，避免窄線效應所導致的阻値 升高問題，同時可以避免閘極與源極/汲極區之間的橋接。 雖然本發明已以一較佳實施例揭露如上，然其並非用 以限定本發明，任何熟習此技藝者，在不脫離本發明之精 神和範圍內，當可作各種之更動與潤飾，因此本發明之保 護範圍當視後附之申請專利範圍所界定者爲準。 (請先閲請背面之注意事項再填窝本頁) n n-^_OJ_ mvt n n 經濟部智慧財產局員工消费合作社印製 9 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公芨）— ·-The higher I is. At this time, if the temperature of the RTP process is to be increased to generate C54 phase titanium silicide, the properties of the formed titanium silicide are unstable and cannot be used in small-sized components, and the reaction temperature is not easy to control, and it is easy to have lateral growth. This phenomenon occurs, so when the component accumulation increases and the size shrinks, side growth can easily cause a bridge between the gate and source / drain regions. In order to avoid this bridging phenomenon, the reaction temperature cannot be increased, and the resistance of the polycrystalline silicon gate is likely to be high when the narrow line is high. Therefore, the present invention provides a method for manufacturing a metal-oxide semiconductor transistor. May increase the formation surface of the silicided metal layer t, which is caused by the love effect of the princely effect: at the same time, it is possible to avoid the problem between the gate and the source / M region. Crystal manufacturing method is suitable for silicon substrate. The method includes forming a polycrystalline silicon gate on a substrate. A lightly doped source / drain region is then formed in the substrate on both sides of the polysilicon gate. Then, a layer of plasma is applied to the silicon gate and the substrate to strengthen the silicon oxide layer. A layer of spacer material, such as a nitrided layer, is then overlaid on the plasma-reinforced silicon oxide layer. 4 This paper size is applicable to China National Standard (CNS) A4 specification (210 X 297 mm) (Please read the precautions on the back before filling this page)., Λ Install --- III 丨 Order ----- -Green. Printed by the Consumers ’Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs 434§〇549 1 twf, doc / 008 A7 B7 Printed by the Consumers’ Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs. 5. Description of the invention u) Then remove part of the gap material layer, To form a gate gap. Then, the plasma-enhanced silicon oxide layer on the polycrystalline silicon gate and the substrate is removed, and a part of the plasma-enhanced silicon oxide layer between the gate spacer and the polycrystalline silicon gate is removed, so that the A gap is formed between the crystalline silicon gates, and the width of the upper part of the notch is larger than the width of the lower part of the notch. A heavily doped source / drain region is then formed in the substrate on both sides of the gate gap wall. A silicide metal process is then performed to form a silicide metal layer on the heavily doped source / drain region and the exposed surface of the polycrystalline silicon gate. According to the present invention, a narrow gap is formed between the gate gap wall and the g crystal g gate. The first to increase the wide pole to form a sanding box layer to avoid the increase in resistance caused by the narrow line effect. At the same time, one of the ¥-^ pole and the source / jifu jg can be avoided. In order to make the above and other objects, features, and advantages of the present invention more comprehensible, a preferred embodiment is given below and cooperated with The drawings are described in detail as follows: The drawings are simple. Figures 1A to 1 are schematic diagrams illustrating the surface of a gold-oxygen semi-electric crystal according to a preferred embodiment of the present invention. Fig. 2 is a drawing showing a person !: In the figure, a partial enlarged view of the area 200 is shown. Explanation of the mark of the drawing:… 10: silicon substrate 12: shallow trench isolation 14 = gate oxide layer 16: gate polycrystalline silicon layer 5 (Please read the precautions on the back before filling this page) 'Pei ---- ---- Order --------- 0, This paper size applies to China National Standard (CNS) A4 (210 X 297 mm) Printed by the Consumer Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs ^ 4'349 © g ; A7 5491twf.doc / 008 B7 'V. Description of the invention (屮) 18, 18a: Lightly doped source / drain region 20, 20a: Plasma reinforced silicon oxide layer 22: Spacer material layer 22a: Gate Spacer wall 24: heavily doped source / drain region 26: silicided metal layer 28: sanded metal layer 50: overhang 52: notch wl: upper width w2: lower width For a preferred embodiment, please refer to FIG. 1A, provide One silicon substrate 10. Then, an element isolation structure such as a shallow trench isolation structure 12 is formed in the substrate 10. Then, a polycrystalline silicon gate is fabricated on the substrate 10, which includes a gate oxide layer 14 and a gate polycrystalline silicon layer 16 stacked from bottom to top. A lightly doped source / drain region (LDD) 18 is then formed in the substrate 10 on both sides of the polysilicon gate. As for the production methods, they are all familiar to those skilled in this art, so I will not repeat them here. Please refer to Figure 1B, and then use plasma enhanced chemical vapor deposition (PECVD) to cover the substrate 10 and the complex crystal sand gate with a thickness of less than 500 degrees Celsius and a pressure of about Atmospheric pressure. Yun 40 £ L Angstrom left and right running layer (PE-oxide) 〇0 The gas layer silicon layer 20 strengthened by the thunder slurry formed while working in JMM 20 has a poor I step coverage and will Silicon gate ^ top angle 6 (Please read the precautions on the back before filling in this page) l ·,! IIII 1 order ----- ml Green paper size applies to Chinese National Standard (CNS) A4 specification (21Q x 297 public love) B7 549 1 twf.doc / 008 5. In the description of the invention (), the phenomenon of overhang 50 is formed. Therefore, the plasma deposited on the side wall of the polycrystalline silicon gate strengthens the silicon oxide layer 20 There may be cases where the upper part is wide and the lower part is narrow. _ Then cover the plasma-reinforced silicon oxide layer 20 with a spacer material layer 22, and the formed spacer material layer 22 must have selectivity to the plasma-reinforced silicon oxide layer, for example, a low-pressure chemical vapor phase A silicon nitride layer formed by deposition (LPCVD). Please refer to FIG. 1C, and then perform a etch back process, for example, using reactive ion etching (RIE) to perform anisotropic dry etching. The slurry strengthens the silicon oxide layer 20) to form a gate spacer 22a. Then, the etching conditions are changed, and an etchant such as fluorocarbon (CFX) is used to remove the silicon oxide layer 20 on the polycrystalline silicon gate and the substrate 10 to remove the silicon oxide layer 20 at the same time. The plasma between the wall 22a and the polycrystalline silicon gate strengthens the silicon oxide layer 20 so that between the gate gap wall 22a and the substrate 10 and between the gate gap wall 22a and the polycrystalline silicon gate, The lower part of the plasma reinforces the silicon oxide layer 22a as a buffer layer, and forms a gap 52 between the blue spacer 22a and the polycrystalline silicon gate, thereby increasing the exposed area of the gate polycrystalline silicon layer 16. Please refer to FIG. 2, which shows a partially enlarged view of the area 200 in FIG. 1C. As shown in the figure, the notch 52 is formed between the gate spacer 22a and the ytterbium polycrystalline silicon layer 16 and is a notch with a wide width and a narrow width. That is, the upper width w1 of the notch 52 is larger than the lower width w2 of the notch 52. Then please refer to Figure 1D, using the ion implantation method, the Chinese paper standard (CNS) A4 (210 κ 297 mm) applies to the paper size of the gate gap. F Please read the note on the back before filling this page. · ----! | Order '---— — — — — Printed by the Consumers ’Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs A7 B7 434f0g 5491twf, doc / 008 V. Description of the invention (t) Bases on both sides of wall 22a 1 A heavily doped source / drain region 24 is formed in O. A silicide metal process is then performed to form silicide metal layers 26 and 28 on the exposed surfaces of the heavily doped source / drain region 24 and the polycrystalline silicon gate (ie, the gate polycrystalline silicon layer 16), respectively. The silicide metal layers 26 and 28 are, for example, a titanium silicide (TiSix) layer or a cobalt silicide (CoSix) layer. Taking the titanium silicide layer as an example, a method for forming the titanium silicide layer is, for example, forming a titanium metal layer on the surface of the substrate 10 by using a sputtering method, and then performing a first stage rapid tempering (RTA1) to react the titanium metal on the contact interface with silicon. A layer of titanium silicide, mainly a C49 phase, is formed. Afterwards, wet etching is used, for example, the RCA falling liquid including ammonium hydroxide (NH4OH), hydrogen peroxide (h2o2), and hot de-ionized water (HDIW) is used to remove the unreacted surface. Metal Chin. The second stage of rapid tempering (RTA2) was followed to transform the titanium silicide layer into a C54 phase structure with lower resistance. Since the present invention forms a gap 52 between the gate spacer 22a and the gate polycrystalline silicon layer 16 to increase the exposed area of the gate polycrystalline silicon layer 16, which increases the formation area of the silicide metal layer 28, it can be avoided. The problem of increased resistance caused by the narrow line effect. In addition, because the notch 52 has a wide upper and narrower profile, it can facilitate the generation of the silicided metal layer 28, and the thickness of the formed silicided metal layer 28 is less than the upper width wl of the notch 52, and the sanded metal layer 28 is even less. It is easy to grow over the gate gap wall 22a, which can effectively prevent the side growth condition from occurring, so the bridge between the polycrystalline silicon gate and the source / drain region can be avoided. Referring to FIG. 1E, an insulating layer 30 is covered on the substrate 10 as an inner dielectric layer. The insulation layer 30 is formed, for example, by depositing a layer of silicon oxide. 8 The paper size is applicable to the Chinese National Standard (CNS) A4 specification (210 x 297 public love) (Please read the precautions on the back before filling in this page) ... '1 'Load! ---- Order! · -------- Printed by the Consumer Property Cooperation Law of the Intellectual Property Bureau of the Ministry of Economic Affairs 5. The invention description Π) layer, and then coated with a layer of low dielectric material, such as spin-on-glass.glass (S0G ) Or spin-on polymer (SOP). Then, a conductive plug 32 is formed in the insulating layer 30, and is electrically connected to the silicided metal layer 26. As for the formation method, for example, the plug opening is first formed by lithography and touch-etching technology, and then conductive is formed by injecting a conductive material. Plug 32. / According to the above-mentioned preferred embodiments of the present invention, it can be known that the application of the present invention can increase the area where the silicide metal layer is formed on the gate, avoid the problem of increasing the resistance caused by the narrow line effect, and avoid the gate and source / drain regions. Between the bridges. Although the present invention has been disclosed as above with a preferred embodiment, it is not intended to limit the present invention. Any person skilled in the art can make various modifications and decorations without departing from the spirit and scope of the present invention. The scope of protection of the invention shall be determined by the scope of the attached patent application. (Please read the precautions on the back before filling in this page) n n-^ _ OJ_ mvt nn Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs 9 This paper size applies to China National Standard (CNS) A4 (210 X 297)芨)

Claims (1)

43490a 549 1 twf.doc/008 A8 B8 C8 D8 六 經濟部智慧財產局員工消費合作杜印製 申請專利範圍 1.一種金氧半電晶體的製造方法，適用於一矽基底， 該方法包括下列步驟： 於該基底上形成一複晶矽閘極； 於該複晶矽閘極兩側之該基底中形成一輕摻雜源極/汲 極區； 於該複晶矽閘極與該基底上覆蓋一電漿加強氧化矽 層； 於該電漿加強氧化矽層上覆蓋一間隙壁材料層； 去除部分該間隙壁材料層，以形成一閘極間隙壁； 去除該複晶矽閘極與該基底上之該電漿加強氧化矽 層，並且去除部分在該閘極間隙壁與該複晶矽閘極之間的 該電漿加強氧化矽層，以在該閘極間隙壁與該複晶矽閘極 之間形成一缺口； 在該閘極間隙壁兩側之該基底中形成一重摻雜源極/汲 極區；以及 進行一矽化金屬製程，在該重摻雜源極/汲極區與該複 晶矽閘極暴露表面形成一矽化金屬層。 如申請專利範圍第1項所述之金氧半電晶體的製造 方法，其中該複晶砂聞極包括一閘極氧化層與一閘極複晶 砂層。 . 3_如申請專利範圍第I項所述之金氧半電晶體的製造 方法，其中形成該電漿加強氧化矽層的方法包括電漿加強 化學氣相沉積法。 4·如申請專利範圍第1項所述之金氧半電晶體的製造 (請先閲讀背面之迮意事項再填寫本頁) 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐） 4 34 _5491twfTdoc/0Q8 A8 B8 C8 D8 六、申請專利範圍 方法，其中該間隙壁材料層的材質包括氮化矽。 、5.如申請專利範圍第丨項所述之金氧半電晶體的製造 方法，其中去除部分該電漿加強氧化矽層的方法包括非等 •向性乾蝕刻。 6.如申請卿谦團第丨項所述之金氧半電晶體的製造 方法，其中該缺口的上部寬度係大於該缺口的下部寬度。 、7_如申請專利範圍第1項所述之金氧半電晶體的製造 方法，其中該矽化金屬層包括矽化鈦層。 8. 如申請專利範圍第1項所述之金氧半電晶體的製造 方法其中該破化金屬層包括砂化銘層。 9. -種閘極結構的製造方法，顧於—賴底，該方 法包括下列步驟：_ 於該基底上形成一複晶矽閘極； 於該複晶砂聞極肖該基底上覆蓋—電紫加強氧化政 層， 於該電漿加強氧化矽層上覆蓋一間隙壁材料層； 去除部分該關壁材料層，以形成—閘極間隙壁； 去除該複晶·__底上之__強氧化砂 .層’並且錄部分在_極嶋麵_晶賴極之間的 該電漿加強氧化砂層’以在該閘極間隙壁與該複晶關極 之間形成一缺口； 進行-砂化金屬製程’在該重麵源極/汲極區與該複 晶石夕閘極暴露表面形成一砍化金屬層。 10. 如申請專利範圍第9項所述之閘極結構的製造方 c 閲讀背面之注意事項再填寫本頁> .k--------tr·--'--------線 經濟卽智慧时轰apMKI-肖費&.a乍i.fsi43490a 549 1 twf.doc / 008 A8 B8 C8 D8 Sixth Consumer Consumption Cooperation of Intellectual Property Bureau of the Ministry of Economic Affairs Du printed application patent scope 1. A manufacturing method of gold-oxygen semi-transistor, suitable for a silicon substrate, the method includes the following steps Forming a composite silicon gate on the substrate; forming a lightly doped source / drain region in the substrate on both sides of the composite silicon gate; covering the composite silicon gate and the substrate A plasma-enhanced silicon oxide layer; covering the plasma-enhanced silicon oxide layer with a spacer material layer; removing part of the spacer material layer to form a gate spacer; removing the polycrystalline silicon gate and the substrate The plasma strengthens the silicon oxide layer, and removes part of the plasma strengthened silicon oxide layer between the gate gap wall and the polycrystalline silicon gate, so that the gate gap wall and the polycrystalline silicon gate are removed. A gap is formed between the electrodes; a heavily doped source / drain region is formed in the substrate on both sides of the gate gap; and a silicidation metal process is performed between the heavily doped source / drain region and the Gold silicide is formed on the exposed surface of the polysilicon gate Floor. The method for manufacturing a gold-oxygen semi-transistor as described in item 1 of the scope of patent application, wherein the complex crystal sand electrode includes a gate oxide layer and a gate complex crystal sand layer. 3_ The manufacturing method of gold-oxygen semitransistor as described in item I of the patent application scope, wherein the method for forming the plasma-enhanced silicon oxide layer includes a plasma-enhanced chemical vapor deposition method. 4. Manufacture of metal-oxide-semiconductor as described in item 1 of the scope of patent application (please read the notice on the back before filling this page) This paper size is applicable to China National Standard (CNS) A4 (210 X 297) (Centi) 4 34 _5491twfTdoc / 0Q8 A8 B8 C8 D8 6. Method of applying for a patent, wherein the material of the spacer material layer includes silicon nitride. 5. The manufacturing method of gold-oxygen semitransistor as described in item 丨 of the patent application scope, wherein the method of removing part of the plasma to strengthen the silicon oxide layer includes anisotropic dry etching. 6. The method for manufacturing a metal-oxygen semi-transistor as described in item 丨 of the application, wherein the upper width of the gap is larger than the lower width of the gap. 7_ The method for manufacturing a metal oxysemiconductor as described in item 1 of the scope of the patent application, wherein the silicided metal layer includes a titanium silicide layer. 8. The method for manufacturing a metal-oxygen semi-transistor as described in item 1 of the patent application scope, wherein the broken metal layer comprises a sanded layer. 9.-A method for manufacturing a gate structure, which includes the following steps:-forming a polycrystalline silicon gate electrode on the substrate; covering the substrate with an electric current on the substrate; A violet-enhanced oxide layer is covered with a spacer material layer on the plasma-enhanced silicon oxide layer; a part of the spacer material layer is removed to form a -gate spacer; the complex crystal is removed. __ 上 的 __ Strong oxidized sand. Layer 'and the plasma-enhanced oxidized sand layer' recorded between _pole surface and crystalline pole to form a gap between the gate gap and the complex crystal gate; progress-sand A metallization process' forms a metallization layer on the heavy source / drain region and the exposed surface of the polycrystalline stone gate. 10. As the manufacturer of the gate structure described in item 9 of the scope of patent application c. Read the notes on the back and fill out this page > .k -------- tr · --'----- --- Line economy meets wisdom when apMKI-Shao Fei &. ASB8C8D8 434^00 5491twf.doc/008 六、申請專利範圍 法，其中該複晶取閘極包括一閘極氧化層與一聞極複晶石夕 層。 11. 如申請專利範圍第9項所述之閘極結構的製造方 ‘法，其中形成該電漿加強氧化矽層的方法包括電漿加強化 學氣相沉積法。 12. 如申請專利範圍第9項所述之閘極結構的製造方 法，其中該間隙壁材料層的材質包括氮化矽。 13. 如申請專利範圍第9項所述之閘極結構的製造方 法，其中去除部分該電發加強氧化砂層的方法包括非等向 性乾蝕刻。 14. 如申請專利範圍第9項所述之閘極結構的製造方 法，其中該缺口的上部寬度係大於該缺口的下部寬度。 15. 如申請專利範圍第9項所述之閘極結構的製造方 法，其中該矽化金屬層包括矽化鈦層。 16. 如申請專利範圍第9項所述之閘極結構的製造方 法，其中該矽化金屬層包括矽化鈷層。 <請先閲讀背面之注意事項再填寫本頁) 經齊耶智慧讨轰势護1-肖賢b乍土尸达 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐〉ASB8C8D8 434 ^ 00 5491twf.doc / 008 6. Application for Patent Scope Method, where the polycrystalline gate is composed of a gate oxide layer and a polycrystalline spar stone layer. 11. The method for manufacturing a gate structure according to item 9 of the scope of the patent application, wherein the method of forming the plasma-reinforced silicon oxide layer includes a plasma-enhanced chemical vapor deposition method. 12. The method for manufacturing a gate structure according to item 9 of the scope of the patent application, wherein the material of the spacer material layer includes silicon nitride. 13. The method for manufacturing a gate structure as described in item 9 of the scope of the patent application, wherein the method for removing a part of the electric-reinforced oxidized sand layer includes anisotropic dry etching. 14. The method of manufacturing a gate structure as described in item 9 of the scope of patent application, wherein the upper width of the gap is greater than the lower width of the gap. 15. The method for manufacturing a gate structure according to item 9 of the patent application, wherein the silicide metal layer includes a titanium silicide layer. 16. The method for manufacturing a gate structure according to item 9 of the patent application, wherein the metal silicide layer includes a cobalt silicide layer. < Please read the notes on the back before filling in this page) The Qiye wisdom discusses the protection 1-Xiao Xianb Zhatu Shida This paper size applies to the Chinese National Standard (CNS) A4 (210 X 297 mm)
TW088121807A 1999-12-13 1999-12-13 Manufacturing method of metal oxide semiconductor transistor TW434908B (en)

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US10840105B2 (en) 2015-06-15 2020-11-17 Taiwan Semiconductor Manufacturing Co., Ltd. Gate structure with insulating structure and method for manufacturing the same

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US6509264B1 (en) * 2000-03-30 2003-01-21 Chartered Semiconductor Manufacturing Ltd. Method to form self-aligned silicide with reduced sheet resistance
US7663237B2 (en) * 2005-12-27 2010-02-16 Taiwan Semiconductor Manufacturing Company, Ltd. Butted contact structure

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* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US10840105B2 (en) 2015-06-15 2020-11-17 Taiwan Semiconductor Manufacturing Co., Ltd. Gate structure with insulating structure and method for manufacturing the same

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