CN101072025A - 半导体集成电路及其测试方法 - Google Patents
半导体集成电路及其测试方法 Download PDFInfo
- Publication number
- CN101072025A CN101072025A CNA2007100881911A CN200710088191A CN101072025A CN 101072025 A CN101072025 A CN 101072025A CN A2007100881911 A CNA2007100881911 A CN A2007100881911A CN 200710088191 A CN200710088191 A CN 200710088191A CN 101072025 A CN101072025 A CN 101072025A
- Authority
- CN
- China
- Prior art keywords
- logic circuit
- application
- circuit module
- test
- register
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 238000012360 testing method Methods 0.000 title claims abstract description 181
- 239000004065 semiconductor Substances 0.000 title claims abstract description 64
- 238000012545 processing Methods 0.000 claims description 22
- 238000006243 chemical reaction Methods 0.000 claims description 11
- 238000000034 method Methods 0.000 claims description 11
- 238000001514 detection method Methods 0.000 claims description 9
- 101100041128 Schizosaccharomyces pombe (strain 972 / ATCC 24843) rst2 gene Proteins 0.000 description 14
- 238000004519 manufacturing process Methods 0.000 description 14
- 238000010998 test method Methods 0.000 description 5
- 238000011156 evaluation Methods 0.000 description 3
- 238000004904 shortening Methods 0.000 description 3
- 238000012423 maintenance Methods 0.000 description 2
- 230000015572 biosynthetic process Effects 0.000 description 1
- 238000005520 cutting process Methods 0.000 description 1
- 230000006378 damage Effects 0.000 description 1
- 238000012217 deletion Methods 0.000 description 1
- 230000037430 deletion Effects 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 238000013101 initial test Methods 0.000 description 1
- 238000011835 investigation Methods 0.000 description 1
- 230000009466 transformation Effects 0.000 description 1
Images
Classifications
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
- G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
- G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
- G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
- G11C11/41—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming static cells with positive feedback, i.e. cells not needing refreshing or charge regeneration, e.g. bistable multivibrator or Schmitt trigger
- G11C11/413—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing, timing or power reduction
- G11C11/417—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing, timing or power reduction for memory cells of the field-effect type
-
- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
- G01R31/28—Testing of electronic circuits, e.g. by signal tracer
- G01R31/317—Testing of digital circuits
- G01R31/3181—Functional testing
- G01R31/3183—Generation of test inputs, e.g. test vectors, patterns or sequences
- G01R31/318342—Generation of test inputs, e.g. test vectors, patterns or sequences by preliminary fault modelling, e.g. analysis, simulation
- G01R31/318357—Simulation
-
- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
- G01R31/28—Testing of electronic circuits, e.g. by signal tracer
- G01R31/317—Testing of digital circuits
- G01R31/3181—Functional testing
- G01R31/3183—Generation of test inputs, e.g. test vectors, patterns or sequences
- G01R31/318385—Random or pseudo-random test pattern
Landscapes
- Engineering & Computer Science (AREA)
- General Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Tests Of Electronic Circuits (AREA)
- Semiconductor Integrated Circuits (AREA)
Abstract
Description
Claims (11)
Applications Claiming Priority (3)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2006-130336 | 2006-05-09 | ||
JP2006130336 | 2006-05-09 | ||
JP2006130336A JP4705880B2 (ja) | 2006-05-09 | 2006-05-09 | 半導体集積回路とそのテスト方法 |
Publications (2)
Publication Number | Publication Date |
---|---|
CN101072025A true CN101072025A (zh) | 2007-11-14 |
CN101072025B CN101072025B (zh) | 2011-09-07 |
Family
ID=38837922
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
CN2007100881911A Active CN101072025B (zh) | 2006-05-09 | 2007-03-20 | 半导体集成电路及其测试方法 |
Country Status (4)
Country | Link |
---|---|
US (2) | US7564265B2 (zh) |
JP (1) | JP4705880B2 (zh) |
KR (1) | KR101279524B1 (zh) |
CN (1) | CN101072025B (zh) |
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN101592703B (zh) * | 2008-05-27 | 2011-10-26 | 华邦电子股份有限公司 | 电路群组及其测试方法与测试机台 |
CN112948189A (zh) * | 2021-02-25 | 2021-06-11 | 山东英信计算机技术有限公司 | 一种裕度测试方法、裕度测试系统及相关装置 |
Families Citing this family (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN106935273B (zh) * | 2015-12-30 | 2020-03-24 | 北京京存技术有限公司 | eMMC测试系统及方法 |
US11043488B2 (en) | 2019-01-24 | 2021-06-22 | Western Digital Technologies, Inc. | High voltage protection for high-speed data interface |
Family Cites Families (14)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS5420680A (en) * | 1977-07-18 | 1979-02-16 | Hitachi Ltd | Large scale integrated circuit |
JP3226293B2 (ja) * | 1991-04-24 | 2001-11-05 | 株式会社日立製作所 | 半導体集積回路 |
JPH08203974A (ja) * | 1995-01-27 | 1996-08-09 | Advantest Corp | 半導体試験装置の電源供給回路 |
US6404228B1 (en) * | 1998-01-09 | 2002-06-11 | Ralph T. Luna | Apparatus for translating digital signals |
JP3727838B2 (ja) * | 2000-09-27 | 2005-12-21 | 株式会社東芝 | 半導体集積回路 |
JP2002111470A (ja) * | 2000-10-03 | 2002-04-12 | Hitachi Ltd | 半導体装置 |
JP2002168914A (ja) * | 2000-11-29 | 2002-06-14 | Ricoh Co Ltd | 安定化電源装置 |
US6977528B2 (en) * | 2002-09-03 | 2005-12-20 | The Regents Of The University Of California | Event driven dynamic logic for reducing power consumption |
KR20040098357A (ko) * | 2003-05-14 | 2004-11-20 | 삼성전자주식회사 | 반도체 장치의 테스트 시스템 |
JP4637512B2 (ja) * | 2003-11-13 | 2011-02-23 | ルネサスエレクトロニクス株式会社 | 半導体集積回路装置 |
JP2006071585A (ja) * | 2004-09-06 | 2006-03-16 | Nippon Avionics Co Ltd | バーンインテストボード |
US7215149B1 (en) * | 2004-12-15 | 2007-05-08 | Lattice Semiconductor Corporation | Interface circuitry for electrical systems |
TWI305339B (en) * | 2005-04-28 | 2009-01-11 | Novatek Microelectronics Corp | Source driver and structure of adjusting voltage with speed |
US7373533B2 (en) * | 2005-09-30 | 2008-05-13 | Silicon Laboratories | Programmable I/O cell capable of holding its state in power-down mode |
-
2006
- 2006-05-09 JP JP2006130336A patent/JP4705880B2/ja active Active
-
2007
- 2007-03-20 KR KR1020070026936A patent/KR101279524B1/ko active IP Right Grant
- 2007-03-20 CN CN2007100881911A patent/CN101072025B/zh active Active
- 2007-05-07 US US11/797,698 patent/US7564265B2/en active Active
-
2009
- 2009-06-26 US US12/479,083 patent/US7724024B2/en active Active
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN101592703B (zh) * | 2008-05-27 | 2011-10-26 | 华邦电子股份有限公司 | 电路群组及其测试方法与测试机台 |
CN112948189A (zh) * | 2021-02-25 | 2021-06-11 | 山东英信计算机技术有限公司 | 一种裕度测试方法、裕度测试系统及相关装置 |
Also Published As
Publication number | Publication date |
---|---|
CN101072025B (zh) | 2011-09-07 |
JP2007303868A (ja) | 2007-11-22 |
US7564265B2 (en) | 2009-07-21 |
US20090251170A1 (en) | 2009-10-08 |
KR101279524B1 (ko) | 2013-06-28 |
US7724024B2 (en) | 2010-05-25 |
JP4705880B2 (ja) | 2011-06-22 |
KR20070109809A (ko) | 2007-11-15 |
US20080071486A1 (en) | 2008-03-20 |
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Legal Events
Date | Code | Title | Description |
---|---|---|---|
C06 | Publication | ||
PB01 | Publication | ||
C10 | Entry into substantive examination | ||
SE01 | Entry into force of request for substantive examination | ||
C14 | Grant of patent or utility model | ||
GR01 | Patent grant | ||
ASS | Succession or assignment of patent right |
Owner name: OKI SEMICONDUCTOR CO., LTD. Free format text: FORMER OWNER: OKI ELECTRIC INDUSTRY CO., LTD. Effective date: 20131125 |
|
C41 | Transfer of patent application or patent right or utility model | ||
TR01 | Transfer of patent right |
Effective date of registration: 20131125 Address after: Tokyo, Japan, Japan Patentee after: Lapis Semiconductor Co., Ltd. Address before: Tiger gate, 1, 7, 12, Tokyo harbour, Japan Patentee before: Oki Electric Industry Co., Ltd. |
|
C56 | Change in the name or address of the patentee | ||
CP02 | Change in the address of a patent holder |
Address after: Yokohama City, Kanagawa Prefecture, Japan Patentee after: Lapis Semiconductor Co., Ltd. Address before: Tokyo, Japan, Japan Patentee before: Lapis Semiconductor Co., Ltd. |