CN101030602A - 一种可减小短沟道效应的mos晶体管及其制作方法 - Google Patents

一种可减小短沟道效应的mos晶体管及其制作方法 Download PDF

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CN101030602A
CN101030602A CNA2007100391861A CN200710039186A CN101030602A CN 101030602 A CN101030602 A CN 101030602A CN A2007100391861 A CNA2007100391861 A CN A2007100391861A CN 200710039186 A CN200710039186 A CN 200710039186A CN 101030602 A CN101030602 A CN 101030602A
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CN101030602B (zh
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康晓旭
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Shanghai IC R&D Center Co Ltd
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    • H01L29/1083—Substrate region of field-effect devices of field-effect transistors with insulated gate with an inactive supplementary region, e.g. for preventing punch-through, improving capacity effect or leakage current
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    • H01L29/66613—Lateral single gate silicon transistors with a gate recessing step, e.g. using local oxidation
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    • H01L29/7834—Field effect transistors with field effect produced by an insulated gate with lightly doped drain or source extension, e.g. LDD MOSFET's; DDD MOSFET's with a non-planar structure, e.g. the gate or the source or the drain being non-planar
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    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
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    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
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Abstract

本发明提供一种可减小短沟道效应的MOS晶体管及其制作方法。现有技术采用外延工艺制作抬高的源极和漏极来减小短沟道效应，存在高复杂性和高成本等问题。本发明的可减小短沟道效应的MOS晶体管制作在已制成场隔离区的硅衬底上，其包括栅极堆层、栅极侧墙、源极和漏极，其中，该硅衬底上制作有凹槽，该栅极堆层设置在该凹槽中。本发明的MOS晶体管的制作方法先制作凹槽；然后进行阱注入、防穿通注入和阈值电压调整注入；接着在该凹槽中制作栅极堆层；之后进行轻掺杂漏注入和晕注入，并制作栅极侧墙；然后进行源漏注入，以制成源极和漏极；最后在源极和漏极顶部制作金属硅化物层。采用本发明可有效减小短沟道效应，并可大大降低工艺难度和制作成本。

Description

一种可减小短沟道效应的MOS晶体管及其制作方法
技术领域
本发明涉及半导体制造领域，特别涉及一种可减小短沟道效应的MOS晶体管及其制作方法。
背景技术
半导体器件通过按比例缩小来实现工作速度的提升。MOS晶体管的沟道长度也在不断的按比例缩短，但当MOS晶体管的沟道长度变得非常短时，短沟道效应会使器件性能劣化，甚至无法正常工作。减小栅极绝缘层的厚度或制作浅结的源极和漏极均可有效的减小短沟道效应，但现在栅极绝缘层的厚度已达到极限，当再减小时易导致栅极的漏电流增大或栅极的击穿，故无法通过减小栅极绝缘层的厚度来减小短沟道效应；另外为确保栅、漏极的较小的接触电阻，故需确保栅、漏极表面具一定厚度的金属硅化物层，故也很难通过制作浅结的源极和漏极来减小短沟道效应。
为减小上述短沟道效应，现通常使用外延工艺制作抬高的源极和漏极。但是外延工艺是一种成本很高、难于控制的工艺技术，存在高复杂性、高成本、高缺陷密度等问题。
发明内容
本发明的目的在于提供一种可减小短沟道效应的MOS晶体管及其制作方法，通过所述MOS晶体管及其制作方法可有效的减小短沟道效应，并可降低工艺难度和制作成本。
本发明的目的是这样实现的：一种可减小短沟道效应的MOS晶体管，该MOS晶体管制作在已制成场隔离区的硅衬底上，该MOS晶体管包括栅极堆层、栅极侧墙、源极以及漏极，其中，该栅极堆层包括依次层叠的栅极绝缘层与栅极，该源极和漏极顶部具有金属硅化物层，其中，该硅衬底上制作有凹槽，该栅极堆层设置在该凹槽中。
在上述的可减小短沟道效应的MOS晶体管中，该凹槽的面积不小于该栅极堆层的面积。
在上述的可减小短沟道效应的MOS晶体管中，该MOS晶体管还包括轻掺杂漏结构。
在上述的可减小短沟道效应的MOS晶体管中，该MOS晶体管还包括晕注入结构。
本发明还提供一种可减小短沟道效应的MOS晶体管的制作方法，该MOS晶体管制作在已制成场隔离区的硅衬底上，该方法包括以下步骤：(1)在该硅衬底上制作凹槽；(2)进行阱注入、防穿通注入和阈值电压调整注入；(3)在该凹槽中制作栅极堆层，该栅极堆层包括依次层叠的栅极绝缘层与栅极；(4)进行轻掺杂漏注入和晕注入；(5)制作栅极侧墙；(6)进行源漏注入，以制成源极和漏极；(7)在源极和漏极顶部制作金属硅化物层。
在上述的可减小短沟道效应的MOS晶体管的制作方法中，该步骤(1)包括以下步骤：(10)光刻出对应栅极的凹槽图形；(11)通过刻蚀制成凹槽；(12)去除光刻胶并优化硅衬底的表面。
在上述的可减小短沟道效应的MOS晶体管的制作方法中，在步骤(11)中，通过湿法刻蚀制成该凹槽。
在上述的可减小短沟道效应的MOS晶体管的制作方法中，在步骤(12)中，通过氧化和湿法腐蚀工艺来优化硅衬底的表面。
在上述的可减小短沟道效应的MOS晶体管的制作方法中，该凹槽的面积不小于该栅极堆层的面积。
与现有技术中采用外延工艺制作抬高的源极和漏极来减小短沟道效应相比，本发明的可减小短沟道效应的MOS晶体管及其制作方法将栅极堆层制作在低于源漏极的凹槽中，以达成相对抬高源漏极的目的，从而可有效的减小短沟道效应，另外可降低工艺难度和制作成本，再者，可降低栅极堆层的高度，为后续金属前栅堆层间介质淀积工艺提供更大的工艺窗口。
附图说明
本发明的可减小短沟道效应的MOS晶体管及其制作方法由以下的实施例及附图给出。
图1为本发明的可减小短沟道效应的MOS晶体管的剖视图；
图2为本发明的可减小短沟道效应的MOS晶体管的制作方法的实施例的流程图；
图3为完成图2中步骤S20后的硅衬底的剖视图；
图4为完成图2中步骤S21后的硅衬底的剖视图。
具体实施方式
以下将对本发明的可减小短沟道效应的MOS晶体管及其制作方法作进一步的详细描述。
如图1所示，本发明的可减小短沟道效应的MOS晶体管1制作在硅衬底2上，所述硅衬底2上已制成了场隔离区(未图示)，所述可减小短沟道效应的MOS晶体管1包括栅极堆层10、栅极侧墙11、源极12、漏极13、轻掺杂漏(LDD)结构14、晕注入(halo)结构15。
所述栅极堆层10包括栅极绝缘层100和栅极102。所述硅衬底2上对应栅极堆层10制作有凹槽(未图示)，所述凹槽的面积不小于所述栅极堆层10的面积，所述栅极堆层10设置在所述凹槽中。
所述栅极侧墙11设置在栅极堆层10两侧，用于确保栅极堆层10与源极12和漏极13之间的绝缘。
所述源极12和漏极13设置在硅衬底2内且排布在栅极10两侧，所述源极12和漏极13顶部具有金属硅化物层120和130。
在本实施例中，通过浅沟槽隔离技术制成所述场隔离区，所述栅极绝缘层100为氧化硅层，所述栅极102为多晶硅栅极，所述栅极侧墙11由氧化硅制成。
所述轻掺杂漏结构14和晕注入结构15均可在一定程度上减小短沟道效应，但不能彻底的解决短沟道效应。通过本发明的凹槽使得MOS晶体管1的沟道低于源极12和漏极13的平面，如此可有效减小短沟道效应。
参见图2，配合参见图1，本发明的可减小短沟道效应的MOS晶体管1的制作方法首先进行步骤S20，光刻出对应栅极堆层10的凹槽图形。参见图3，显示了完成步骤S20后硅衬底2的剖视图，如图所示，光阻3覆盖在硅衬底2，且光阻3上已生成有凹槽图形。
接着继续步骤S21，通过刻蚀制成凹槽。在本实施例中，通过湿法刻蚀制成凹槽。参见图4，显示了完成步骤S21后硅衬底2的剖视图，如图所示，硅衬底2上制成了凹槽20。
接着继续步骤S22，去除光刻胶并优化硅衬底2的表面。在本实施例中，通过氧化和湿法腐蚀工艺来优化硅衬底的表面。
接着继续步骤S23，进行阱注入、防穿通注入和阈值电压调整注入。
接着继续步骤S24，在所述凹槽中制作栅极堆层10，所述栅极堆层10包括栅极绝缘层100和栅极102。在本实施例中，首先先沉积栅极绝缘层100，然后再沉积栅极102，最后经光刻和刻蚀制成栅极堆层10。
接着继续步骤S25，进行轻掺杂漏注入和晕注入，以形成轻掺杂漏结构14和晕注入结构15。
接着继续步骤S26，制作栅极侧墙11。
接着继续步骤S27，进行源漏注入，以制成源极12和漏极13。
接着继续步骤S28，在源极12和漏极13顶部制作金属硅化物层120和130。
需说明的是，步骤S20和步骤S24中，一般使用两张光罩形成所需的图形，也可使用相同的光罩但使用极性不同的光刻胶进行光刻，其中，在步骤S20中使用反光刻胶，在步骤S24中使用正光刻胶，如此可大大节约成本。
综上所述，本发明的可减小短沟道效应的MOS晶体管1及其制作方法将栅极堆层制作在低于源漏极的凹槽中，以达成相对抬高源漏极的目的，从而可有效的减小短沟道效应，另外可降低工艺难度和制作成本，再者，可降低栅极堆层的高度，为后续金属前栅堆层间介质淀积工艺提供更大的工艺窗口。

Claims (9)

1、一种可减小短沟道效应的MOS晶体管，该MOS晶体管制作在已制成场隔离区的硅衬底上，该MOS晶体管包括栅极堆层、栅极侧墙、源极以及漏极，其中，该栅极堆层包括依次层叠的栅极绝缘层与栅极，该源极和漏极顶部具有金属硅化物层，其特征在于，该硅衬底上制作有凹槽，该栅极堆层设置在该凹槽中。
2、如权利要求1所述的可减小短沟道效应的MOS晶体管，其特征在于，该凹槽的面积不小于该栅极堆层的面积。
3、如权利要求1所述的可减小短沟道效应的MOS晶体管，其特征在于，该MOS晶体管还包括轻掺杂漏结构。
4、如权利要求1所述的可减小短沟道效应的MOS晶体管，其特征在于，该MOS晶体管还包括晕注入结构。
5、一种可减小短沟道效应的MOS晶体管的制作方法，该MOS晶体管制作在已制成场隔离区的硅衬底上，其特征在于，该方法包括以下步骤：(1)在该硅衬底上制作凹槽；(2)进行阱注入、防穿通注入和阈值电压调整注入；(3)在该凹槽中制作栅极堆层，该栅极堆层包括依次层叠的栅极绝缘层与栅极；(4)进行轻掺杂漏注入和晕注入；(5)制作栅极侧墙；(6)进行源漏注入，以制成源极和漏极；(7)在源极和漏极顶部制作金属硅化物层。
6、如权利要求5所述的可减小短沟道效应的MOS晶体管的制作方法，其特征在于，该步骤(1)包括以下步骤：(10)光刻出对应栅极的凹槽图形；(11)通过刻蚀制成凹槽；(12)去除光刻胶并优化硅衬底的表面。
7、如权利要求6所述的可减小短沟道效应的MOS晶体管的制作方法，其特征在于，在步骤(11)中，通过湿法刻蚀制成该凹槽。
8、如权利要求6所述的可减小短沟道效应的MOS晶体管的制作方法，其特征在于，在步骤(12)中，通过氧化和湿法腐蚀工艺来优化硅衬底的表面。
9、如权利要求5所述的可减小短沟道效应的MOS晶体管的制作方法，其特征在于，该凹槽的面积不小于该栅极堆层的面积。
CN2007100391861A 2007-04-06 2007-04-06 一种可减小短沟道效应的mos晶体管及其制作方法 Active CN101030602B (zh)

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CN2007100391861A CN101030602B (zh) 2007-04-06 2007-04-06 一种可减小短沟道效应的mos晶体管及其制作方法
US12/062,851 US20080246087A1 (en) 2007-04-06 2008-04-04 Mos transistor for reducing short-channel effects and its production
US12/946,162 US8193057B2 (en) 2007-04-06 2010-11-15 MOS transistor for reducing short-channel effects and its production

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