WO2017028546A1 - 具有三维晶体管结构的背照式图像传感器及其形成方法 - Google Patents

具有三维晶体管结构的背照式图像传感器及其形成方法 Download PDF

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WO2017028546A1
WO2017028546A1 PCT/CN2016/078738 CN2016078738W WO2017028546A1 WO 2017028546 A1 WO2017028546 A1 WO 2017028546A1 CN 2016078738 W CN2016078738 W CN 2016078738W WO 2017028546 A1 WO2017028546 A1 WO 2017028546A1
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transistor
image sensor
region
forming
illuminated image
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PCT/CN2016/078738
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English (en)
French (fr)
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赵立新
李文强
王永刚
李�杰
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格科微电子（上海）有限公司
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Priority to US15/752,212 priority Critical patent/US10720463B2/en
Publication of WO2017028546A1 publication Critical patent/WO2017028546A1/zh

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/14—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation
    • H01L27/144—Devices controlled by radiation
    • H01L27/146—Imager structures
    • H01L27/14601—Structural or functional details thereof
    • H01L27/1464—Back illuminated imager structures
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/14—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation
    • H01L27/144—Devices controlled by radiation
    • H01L27/146—Imager structures
    • H01L27/14601—Structural or functional details thereof
    • H01L27/14609—Pixel-elements with integrated switching, control, storage or amplification elements
    • H01L27/14612—Pixel-elements with integrated switching, control, storage or amplification elements involving a transistor
    • H01L27/14614—Pixel-elements with integrated switching, control, storage or amplification elements involving a transistor having a special gate structure
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/14—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation
    • H01L27/144—Devices controlled by radiation
    • H01L27/146—Imager structures
    • H01L27/14601—Structural or functional details thereof
    • H01L27/1463—Pixel isolation structures
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/14—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation
    • H01L27/144—Devices controlled by radiation
    • H01L27/146—Imager structures
    • H01L27/14683—Processes or apparatus peculiar to the manufacture or treatment of these devices or parts thereof
    • H01L27/14689—MOS based technologies
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/762—Charge transfer devices
    • H01L29/765—Charge-coupled devices
    • H01L29/768—Charge-coupled devices with field effect produced by an insulated gate
    • H01L29/76866—Surface Channel CCD
    • H01L29/76883—Three-Phase CCD

Definitions

  • the present invention relates to the field of image sensors, and in particular, to a back-illuminated image sensor having a three-dimensional transistor structure and a method of forming the same.
  • An image sensor is a semiconductor device that converts an optical signal into an electrical signal, and the image sensor has a photoelectric conversion element.
  • the image sensor can be further divided into a complementary metal oxide (CMOS) image sensor and a charge coupled device (CCD) image sensor.
  • CMOS image sensor complementary metal oxide (CMOS) image sensor
  • CCD image sensor charge coupled device
  • the advantage of the CCD image sensor is that the image sensitivity is high and the noise is small, but the integration of the CCD image sensor with other devices is difficult, and the power consumption of the CCD image sensor is high.
  • CMOS image sensors have the advantages of simple process, easy integration with other devices, small size, light weight, low power consumption, and low cost. Therefore, with the development of technology, CMOS image sensors are increasingly replacing CCD image sensors for use in various electronic products. At present, CMOS image sensors have been widely used in static digital cameras, camera phones, digital video cameras, medical imaging devices (such as gastroscopes), and vehicle imaging devices.
  • the core component of the image sensor is a pixel unit (Pixel), which directly affects the image sensor size, dark current level, noise level, imaging permeability, image color saturation and image defects.
  • Image quality factors In order to ensure image quality, especially in order to ensure light sensitivity, color saturation and imaging permeability, sufficient light is required to be incident on the photoelectric conversion elements of the pixel unit (usually using photodiodes). Larger pixel units can receive light with a larger photosensitive area. Therefore, larger pixel units can provide better image quality in principle. In addition, in addition to photoelectric conversion elements, there are quite a few pixels in the pixel unit. Switching devices, such as reset transistors, pass transistors, and amplifier components (such as source follower transistors), which also determine dark current, noise, and image defects. In terms of image quality, in principle, the electrical performance of large devices is better. It helps to form a better quality image; for this reason, it is required that the size of the pixel unit in the image sensor increases due to image quality factors.
  • the existing image sensor there is usually an array of pixels consisting of one pixel unit. From the perspective of the layout, a plurality of pixel units can be combined to form a complete pixel array, and the shape of the pixel unit can be It is a rectangle, a square, a polygon (a triangle, a pentagon, a hexagon) and so on.
  • the structure of the pixel unit can be divided into a photoelectric conversion element plus a 3-transistor structure, a photoelectric conversion element plus a 4-transistor structure or a photoelectric conversion element plus a 5-transistor structure.
  • the photoelectric conversion element plus the 3-transistor structure is specifically that the photoelectric conversion element is directly electrically connected to the floating diffusion region, and the photogenerated electrons generated in the photoelectric conversion element are stored in the floating diffusion region at the reset transistor (RST) and the row gate transistor (SEL). Under the timing control, the photogenerated electrons are converted and output through the source follower (SF).
  • the photoelectric conversion element 115 is generally a photodiode (PD), and the photoelectric conversion element 115 is electrically connected to the floating diffusion region 113 (FD) through the transfer transistor 114, and the lead L3 (leads typically include plugs and interconnects, etc.) electrically connect the gates of transfer transistor 114.
  • the source follower transistor 112 is electrically coupled to the floating diffusion region 113, the source follower transistor 112 is for amplifying the potential signal formed in the floating diffusion region 113, and the lead L2 is electrically connected to the source to follow (amplify) the gate of the transistor 112.
  • One end of the reset transistor 111 is electrically connected to the power supply VDD, and the other end is electrically connected to the floating diffusion region 113 to reset the potential of the floating diffusion region 113, and the lead L1 is electrically connected to the gate of the reset transistor 111.
  • the photoelectric conversion element plus four transistor structure is a photoelectric conversion element added to the 3-transistor structure, and the transfer transistor 114 is added between the photoelectric conversion element 115 and the floating diffusion region 113.
  • the transfer transistor 114 can effectively suppress the noise, and the photoelectric conversion element plus the 4-transistor structure can obtain better image quality, and gradually becomes the leading structure in the industry.
  • a set of 4-transistor devices can be shared by a plurality of photoelectric conversion elements in order to save chip area, and this structure is also considered to be a 4-transistor structure.
  • the pixel unit has defects that are inherently difficult to overcome:
  • all four transistor devices are planar structures. In other words, if the chip area is to be further reduced, it is necessary to reduce these devices (such as transfer transistors, reset transistors, and source followers). size. However, if the size of these devices is reduced, the performance of these devices will be degraded at the same time, which is caused by the decrease of the driving current of the device, the increase of fluctuations in electrical parameters, and the decrease in amplification efficiency. The impact of these issues on image quality is significant. Therefore, although the circuit around the pixel array can further reduce the line width and reduce the size according to Moore's Law, the transistor device in the pixel unit can only be reduced very slowly. The area of the entire image sensor chip is mainly determined by the pixel array. Therefore, the structure of the existing pixel unit limits the chip area to be further reduced, and the cost of the image sensor is high.
  • all of the four transistor devices are planar structures.
  • the size can be further reduced, resulting in the photoelectric conversion component of the photosensitive portion occupying the pixel unit.
  • the ratio is limited.
  • the smaller the proportion of the photoelectric conversion element the less light is collected per unit area, the less transparent the image, the worse the image layering, the more dry the color, in short, the transistor
  • the planar structure of the piece limits the further improvement in image quality.
  • the image quality under the dark field is very critical, and its key indicators are dark current, noise, white and dark spots. These dark currents, noise, white and dark spots are derived from the frequency noise and thermal noise of the transistor device, as well as the surface recombination current of the photoelectric conversion element.
  • the process limit has been reached, the desired effect cannot be obtained. Therefore, a new image sensor and a corresponding process are urgently needed to further reduce dark current and noise.
  • the level of indicators such as white and dark spots.
  • each transistor since each transistor has a planar structure, the parasitic capacitance between the transfer transistor, the reset transistor, and the source follower transistor cannot be further reduced as the size is reduced, and the parasitic capacitance basically plays a negative role. For example, reducing signal transmission speed, increasing low frequency 1/f noise, reducing dynamic range, etc., are unacceptable to image sensors. Therefore, it is necessary to further reduce the parasitic capacitance and reduce the low frequency 1/f noise in order to increase the signal transmission speed and increase the dynamic range, which is a very difficult and expensive task for the conventional image sensor and its forming process.
  • the Chinese invention patent: "Image sensor and its forming method” application number: 201410193016.9 discloses an image sensor and a forming method thereof, and proposes a stereoscopic image sensor structure.
  • the channel region region of the source follower transistor has a beam structure
  • the beam structure has a top surface and two side surfaces
  • the gate of the source follower transistor covers at least one of the top surface and the two side surfaces.
  • the process steps of forming the gate region of the source follower transistor are more difficult to achieve and affect the goodness of the semiconductor interface. Therefore, how to form a gate region with a good interface in forming a 3D image sensor, and improving the performance of the image sensor is an urgent problem to be solved.
  • the present invention provides a method for forming a back-illuminated image sensor having a three-dimensional transistor structure, the three-dimensional transistor gate
  • the step of forming the structure includes: forming a source follower transistor and/or a reset crystal having a three-dimensional transistor structure a body tube, the source follower transistor and/or a reset transistor corresponding to a convex structure; an insulating sidewall is formed around the bump structure, and the insulating sidewall wall forms a groove between the channel region of the transistor corresponding to the bump structure,
  • the transistor gate region is formed in the recess and is isolated by the insulating spacer.
  • the floating diffusion region of the back-illuminated image sensor is formed in the convex semiconductor surface; and the floating diffusion region sidewall is formed while forming the insulating sidewall wall, the floating The diffusion region is isolated from the gate region of the transfer transistor by the sidewall of the floating diffusion region to reduce parasitic capacitance.
  • the photodiode region of the back-illuminated image sensor corresponds to a semiconductor surface that is lower than a surface of the semiconductor corresponding to the floating diffusion region by 100 nm or more.
  • a shallow trench isolation structure is formed, the photodiode region is located at the bottom of the shallow trench isolation structure, and the convex structure defined between the shallow trench isolation structures corresponds to the source follower transistor, reset At least one of a transistor and a floating diffusion region; forming an insulating layer filling the shallow trench isolation structure; etching a portion of the insulating layer to form a recess in a corresponding region of the source follower transistor and/or the reset transistor channel region.
  • silicon nitride is further formed on the bump region to serve as a hard mask for self-aligned etching during trench formation.
  • the insulating layer is etched away, the photodiode region is exposed, and an insulating sidewall is formed; the gate oxide layer and the polysilicon layer are formed to cover; and the polysilicon layer is formed by etching A gate region of the three-dimensional transistor, wherein the insulating sidewall spacer has a self-alignment effect in etching, and isolates a gate region formed after etching to reduce a design size.
  • the method further comprises: forming an anti-reflection layer and a photoresist layer.
  • the present invention also provides a back-illuminated image sensor having a three-dimensional transistor structure, comprising: a source follower transistor and/or a reset transistor having a three-dimensional transistor structure; the source follower transistor and/or a reset transistor corresponding to a bump structure; Around the raised structure
  • the insulating sidewall wall has a groove between the channel region of the transistor corresponding to the protruding structure, and the gate region of the transistor is located in the groove and is isolated by the insulating sidewall.
  • the floating diffusion region of the back-illuminated image sensor is located in the convex semiconductor surface; the floating diffusion region passes through the floating diffusion region sidewall and the gate of the transfer transistor Polar region isolation reduces parasitic capacitance.
  • the photodiode region of the back-illuminated image sensor corresponds to a semiconductor surface that is lower than a surface of the semiconductor corresponding to the floating diffusion region by 100 nm or more.
  • the invention reduces the additional area required in the conventional device due to the existence of shallow trench isolation, increases the filling ratio of the photosensitive device and increases the ratio of available light in the same pixel size; due to the floating diffusion region and the photodiode Not in the same plane, compared with the conventional planar structure, the junction capacitance of the floating diffusion region of the present invention and the parasitic capacitance between the transfer transistor and the transfer transistor are small, and the conversion gain (Conversion Gain) is improved; the Finfet transistor structure can maintain the effective channel length of the transistor.
  • the effective size is larger in the case of the same area, especially the channel width, and the Finfet structure can greatly improve the transconductance of the transistor, which theoretically reduces the 1/f noise.
  • the channel current tends to flow in the bulk silicon, away from the gate oxide interface, thereby avoiding noise caused by defects in the gate oxide interface.
  • the invention adopts two photolithography to form an insulating sidewall having a groove inside, and better control the process process in forming the gate structure of the transistor, and the shape and interface of the gate structure are better.
  • FIG. 1 is a schematic cross-sectional structural view of a pixel unit in a conventional image sensor
  • FIG. 2 to FIG. 9 are schematic diagrams showing the steps of a method for forming a back-illuminated image sensor having a three-dimensional transistor structure according to an embodiment of the present invention.
  • FIG. 10 is a flow chart showing a method of forming a back-illuminated image sensor having a three-dimensional transistor structure according to the present invention.
  • each transistor for example, a source follower transistor, a transfer transistor, a reset transistor, etc.
  • the corresponding pixel unit has many defects, for example, the chip area of the image sensor is difficult to be further reduced, and the image sensor The cost is high, the image quality formed by the image sensor is difficult to further improve, the noise level of the image sensor is difficult to reduce, and the area occupancy of the photoelectric conversion element in the pixel unit is difficult to increase.
  • the present invention provides a method of forming a back-illuminated image sensor having a three-dimensional transistor structure, the step of forming a three-dimensional transistor gate structure comprising: forming a source follower transistor and/or a reset transistor having a three-dimensional transistor structure, the source follower transistor and And a resetting transistor corresponding to the protruding structure; forming an insulating sidewall around the protruding structure, the insulating sidewall forming a groove between the channel region of the transistor corresponding to the protruding structure, and forming a gate region of the transistor in the groove It is isolated by insulated side walls.
  • FIG. 2 to FIG. 9 are schematic diagrams showing the steps of a method for forming a back-illuminated image sensor having a three-dimensional transistor structure according to an embodiment of the present invention.
  • a semiconductor substrate 200 is provided, which is a carrier for fabricating an image sensor, which may be a silicon wafer; defining a pixel region and a logic region, forming silicon nitride 220 on the surface of the semiconductor substrate, and photolithography
  • the glue 230 is etched to form a plurality of shallow trench isolation structures (STI) 210 having a plurality of raised structures 240 between the shallow trench isolations 210.
  • STI shallow trench isolation structures
  • a fill dielectric layer 250 is deposited in a shallow trench isolation structure 210 for chemical mechanical polishing (CMP).
  • CMP chemical mechanical polishing
  • photolithography is performed to expose areas where a reset transistor and/or a source follower transistor are required. It should be noted that the reset transistor and the source follower transistor may be disposed around the bump structure 240 or alternatively selected one; after photolithography, the dielectric layer may be selectively etched by using the silicon nitride 220 as a hard mask.
  • the dielectric layer 250 is an insulating dielectric layer such as silicon oxide or silicon oxynitride; after the etching, the silicon nitride 210 is removed, and a recess 260 is formed in a surrounding area of the convex structure 240, and the silicon nitride 220 is formed in the process of forming the recess 220.
  • a hard mask for self-aligned etching A portion of the dielectric layer 250 is again etched in FIG. 5 to remove the dielectric layer over the subsequently formed photodiode 270 (PhotoDiode), exposing the semiconductor surface, remaining around the raised structure of the subsequently formed floating diffusion region 280.
  • an insulating sidewall 290 is formed around the bump structure corresponding to the source follower transistor and/or the reset transistor, and the recess 260 is formed between the insulating channel spacer 290 and the transistor channel region corresponding to the bump structure 240 to form an insulating side
  • the wall 290 forms a floating diffusion side wall 300 at the same time.
  • a gate oxide layer (not labeled) is formed on the surface of the interface, and a polysilicon layer 310 is formed on the gate oxide layer (not labeled). In FIG. 7, the polysilicon layer 310 is etched.
  • an anti-reflection layer (BARC) 320 is formed on the polysilicon layer 310.
  • the anti-reflection layer 320 serves as a flat pixel region, and a photoresist layer 330 is formed on the surface of the anti-reflection layer 320, and the anti-reflection layer 320 is formed.
  • a portion of the photodiode 270 region adjacent to the insulating sidewall 290 is controlled to form a thicker anti-reflective layer 320.
  • polysilicon etching is performed such that the transistor gate region 340 is formed in the recess 260 and is isolated by the insulating spacer 290.
  • the insulating spacer 290 has self-alignment during etching and is formed after etching.
  • the gate region 340 is isolated and can further reduce the design size.
  • the floating diffusion region is formed in a region corresponding to a convex region, and the semiconductor surface corresponding to the floating diffusion region 280 is at least 100 nanometers higher than the semiconductor surface corresponding to the photodiode 330.
  • a device for forming an image sensor by an existing process finally forms a back-illuminated image sensor having a three-dimensional transistor structure.
  • FIG. 10 is a flowchart of a method for forming a back-illuminated image sensor having a three-dimensional transistor structure according to the present invention.
  • the forming method includes: S101 forming a source follower transistor and/or a reset transistor having a three-dimensional transistor structure, Source follower transistor And/or a reset transistor corresponding to the protruding structure; an insulating sidewall is formed around the protruding structure of S103, the insulating sidewall wall forms a groove between the channel region of the transistor corresponding to the protruding structure, and the gate region of the transistor is formed in the concave
  • the tank is isolated by insulated side walls.
  • the invention reduces the additional area required in the conventional device due to the existence of shallow trench isolation, increases the filling ratio of the photosensitive device and increases the ratio of available light in the same pixel size; due to the floating diffusion region and the photodiode Not in the same plane, compared with the conventional planar structure, the junction capacitance of the floating diffusion region of the present invention and the parasitic capacitance between the transfer transistor and the transfer transistor are small, and the conversion gain (Conversion Gain) is improved; the Finfet transistor structure can maintain the effective channel length of the transistor.
  • the effective size is larger in the case of the same area, especially the channel width, and the Finfet structure can greatly improve the transconductance of the transistor, which theoretically reduces the 1/f noise.
  • the channel current tends to flow in the bulk silicon, away from the gate oxide interface, thereby avoiding noise caused by defects in the gate oxide interface.
  • the invention adopts two photolithography to form an insulating sidewall having a groove inside, and better control the process process in forming the gate structure of the transistor, and the shape and interface of the gate structure are better.

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Abstract

提供一种具有三维晶体管结构的背照式图像传感器及其形成方法，三维晶体管栅极结构的形成步骤包括：形成具有三维晶体管结构的源跟随晶体管和/或复位晶体管，源跟随晶体管和/或复位晶体管对应凸起结构（240）；凸起结构（240）周围形成绝缘侧墙（290），绝缘侧墙（290）与凸起结构（240）对应的晶体管沟道区之间形成凹槽（260），晶体管栅极区域（340）形成于凹槽（260）内并由绝缘侧墙（290）隔离。

Description

具有三维晶体管结构的背照式图像传感器及其形成方法
本申请要求2015年08月18日提交中国专利局、申请号为201510505877.0、发明名称为“具有三维晶体管结构的背照式图像传感器及其形成方法”的中国专利申请的优先权，其全部内容通过引用结合在本申请中。
技术领域
本发明涉及图像传感器领域，尤其涉及一种具有三维晶体管结构的背照式图像传感器及其形成方法。
背景技术
图像传感器是将光信号转化为电信号的半导体器件，图像传感器具有光电转换元件。
图像传感器按又可分为互补金属氧化物(CMOS)图像传感器和电荷耦合器件(CCD)图像传感器。CCD图像传感器的优点是对图像敏感度较高且噪声小，但是CCD图像传感器与其他器件的集成比较困难，而且CCD图像传感器的功耗较高。相比之下，CMOS图像传感器具有工艺简单、易与其他器件集成、体积小、重量轻、功耗小、成本低等优点。因此，随着技术发展，CMOS图像传感器越来越多地取代CCD图像传感器应用于各类电子产品中。目前CMOS图像传感器已经广泛应用于静态数码相机、照相手机、数码摄像机、医疗用摄像装置(例如胃镜)、车用摄像装置等。
图像传感器的核心元件是像素单元(Pixel)，像素单元直接影响图像传感器的尺寸大小、暗电流水平、噪声水平、成像通透性、图像色彩饱和度和图像缺陷等等因素。
一直以来，一对矛盾的因素一起推动图像传感器向前发展：
1.经济因素：一个晶圆可产出的图像传感器芯片越多，则图像传 感器芯片的成本越低，而像素单元占据整个图像传感器芯片的大部分面积，因此，为了节省成本，要求像素单元的尺寸制作得较小，也就是说，出于经济因素考虑，要求图像传感器中像素单元的尺寸缩小。
2.图像质量因素：为了保证图像质量，特别是为了保证光线敏感度、色彩饱和度和成像通透性等指标，需要有足够的光线入射到像素单元的光电转换元件(通常采用光电二极管)中，而较大的像素单元能够有较大的感光面积接受光线，因此，较大的像素单元原则上可以提供较好的图像质量；此外，像素单元中除了光电转换元件外，还有相当部分的开关器件，例如重置晶体管、传输晶体管和放大器件(如源跟随晶体管)，这些器件同样决定着暗电流、噪声和图像缺陷等，从图像质量角度考虑，原则上大器件的电学性能更好，有助于形成质量更好的图像；为此可知，出于图像质量因素考虑，要求图像传感器中像素单元的尺寸增大。
可以明显得看到，如何协调上述矛盾以取得最优化的选择，是图像传感器业界一直面临的问题。
现有图像传感器中，通常具有由一个一个像素单元组成的像素阵列(array)，从版图层面看，多个像素单元可以拼在一起组合成一个完整的像素阵列，并且根据需要像素单元的形状可以是矩形，正方形，多边形(三角形，五边形，六边形)等等。
现有图像传感器中，像素单元的结构可以分为光电转换元件加3晶体管结构，光电转换元件加4晶体管结构或者光电转换元件加5晶体管结构。光电转换元件加3晶体管结构具体是光电转换元件直接电连接浮置扩散区，光电转换元件中产生的光生电子储存于浮置扩散区中，在复位晶体管(RST)和行选通晶体管(SEL)的时序控制下，将光生电子通过源跟随器(SF)转换输出。
请参考图1，示出了光电转换元件加4晶体管结构的剖面示意图。光电转换元件115通常为光电二极管(Photo diode，PD)，光电转换元件115通过转移晶体管114电连接浮置扩散区113(FD)，引线 L3(引线通常包括插塞和互连线等)电连接转移晶体管114的栅极。源跟随晶体管112电连接浮置扩散区113，源跟随晶体管112用于将浮置扩散区113中形成的电位信号放大，引线L2电连接源跟随(放大)晶体管112的栅极。复位晶体管111一端电连接电源VDD，另一端电连接浮置扩散区113，以对浮置扩散区113的电位进行复位，引线L1电连接复位晶体管111的栅极。从中可知，光电转换元件加4晶体管结构是光电转换元件加在3晶体管结构基础上，在光电转换元件115和浮置扩散区113之间增加传输晶体管114。传输晶体管114可以有效地抑止杂讯，光电转换元件加4晶体管结构可以得到更好的图像质量，逐渐成为业界的主导结构。此外，可以多个光电转换元件共享一套4晶体管器件，以便节省芯片面积，这种结构也被认为是4晶体管结构。
然而，现有图像传感器中，像素单元有其先天难以克服的缺陷：
1.现有像素单元中，4个晶体管器件全部都是平面结构，换而言之，如果要进一步缩小芯片面积，必须要减小这些器件(如传输晶体管、复位晶体管和源跟随晶体管等)的尺寸。但是如果缩小这些器件的尺寸，会同时导致这些器件的性能下降，具体表现为器件的驱动电流下降、电学参数波动增加和放大效率下降等问题。这些问题对于图像质量的影响十分重大。因此，虽然像素阵列周边的电路可以按照摩尔定律进一步缩小线宽，减小尺寸，但是像素单元中的晶体管器件却只能非常缓慢地缩小。而整个图像传感器芯片的面积主要由像素阵列决定，因此，现有像素单元的结构限制了芯片面积进一步缩小，使图像传感器的成本高居不下。
2.现有像素单元中，4个晶体管器件全部都是平面结构，对于一定大小的像素单元，其容纳4个晶体管器件后，大小很能进一步缩小，导致感光部分的光电转换元件占像素单元的比例被限制。而对于像素单元性能来讲，光电转换元件占比例越小，单位面积内收集的光线越少，图像越不通透，图像层次感越差，色彩越干涩，总之，晶体管器 件的平面结构限制了图像质量的进一步提高。
3.现有像素单元中，在暗场下的图像质量十分关键，其关键指标是暗电流、噪声、白点和暗点等。这些暗电流、噪声、白点和暗点来源于晶体管器件频率噪声和热噪声，以及光电转换元件的表面复合电流。在传统的现有工艺中，即使花费很大的努力在这些方面，但是由于已经到达工艺极限，仍然无法取得理想的效果，因此，急需新的图像传感器和相应的工艺来进一步降低暗电流、噪声、白点和暗点等指标的水平。
4.现有像素单元中，由于各晶体管均为平面结构，因此，转移晶体管、复位晶体管和源跟随晶体管之间的寄生电容不能随着尺寸缩小进一步降低，寄生电容基本上起到负面的作用，例如降低信号传输速度，增大低频1/f噪声，减小动态范围等等，这些都是图像传感器所不能接受的。所以，必须要进一步减小寄生电容，降低低频1/f噪声，以便提高信号传输速度，增大动态范围，而这对于传统图像传感器及其形成工艺而言，是一个非常艰巨而且昂贵任务。
现有技术中，中国发明专利：《图像传感器及其形成方法》申请号：201410193016.9公开了一种图像传感器及其形成方法，提出了一种立体的图像传感器结构。其中，源跟随晶体管的沟道区区域呈横梁结构，横梁结构具有顶面和两个侧面，所述源跟随晶体管的栅极覆盖所述顶面和两个侧面的至少其中一面。在该发明专利申请中，形成源跟随晶体管的栅极区域的工艺步骤较难以实现，会影响半导体界面的良好性。因此，如何在形成3D的图像传感器中，形成界面良好的栅极区域，提高图像传感器的性能为亟待解决的课题。
发明内容
为了提高图像传感器的性能，特别解决3D图像传感器制作过程中晶体管栅极结构制作难的问题，本发明提供一种：具有三维晶体管结构的背照式图像传感器的形成方法，所述三维晶体管栅极结构的形成步骤包括：形成具有三维晶体管结构的源跟随晶体管和/或复位晶 体管，所述源跟随晶体管和/或复位晶体管对应凸起结构；所述凸起结构周围形成绝缘侧墙,所述绝缘侧墙与凸起结构对应的晶体管沟道区之间形成凹槽，晶体管栅极区域形成于凹槽内并由绝缘侧墙隔离。
特别的，在本发明一实施例中，所述背照式图像传感器的浮置扩散区形成于凸起的半导体表面内；于形成绝缘侧墙的同时形成浮置扩散区侧墙，所述浮置扩散区通过浮置扩散区侧墙与转移晶体管栅极区域隔离，降低寄生电容。
特别的，在本发明一实施例中，所述背照式图像传感器的光电二极管区域对应的半导体表面低于所述浮置扩散区对应的半导体表面大于等于100纳米。
特别的，在本发明一实施例中，形成浅沟槽隔离结构，所述光电二极管区域位于浅沟槽隔离结构底部，定义浅沟槽隔离结构之间的凸起结构对应于源跟随晶体管、复位晶体管、浮置扩散区中的至少一个；形成绝缘层，填充浅沟槽隔离结构；于源跟随晶体管和/或复位晶体管沟道区的对应区域刻蚀部分绝缘层形成凹槽。
特别的，在本发明一实施例中，所述凸起区域上还形成有氮化硅，以作为形成凹槽过程中自对准刻蚀的硬掩膜。
特别的，在本发明一实施例中，于形成凹槽之后，刻蚀去除绝缘层，暴露出光电二极管区域，并形成绝缘侧墙；覆盖形成栅极氧化层、多晶硅层；刻蚀多晶硅层形成三维晶体管的栅极区域，其中所述绝缘侧墙在刻蚀中具有自对准作用，并对刻蚀后形成栅极区域进行隔离，降低设计尺寸。
特别的，在本发明一实施例中，于覆盖形成栅极氧化层、多晶硅层的步骤后还包括：形成防反射层、光阻层。
本发明还提供一种具有三维晶体管结构的背照式图像传感器，包括：具有三维晶体管结构的源跟随晶体管和/或复位晶体管；所述源跟随晶体管和/或复位晶体管对应凸起结构；所述凸起结构周围具有 绝缘侧墙,所述绝缘侧墙与凸起结构对应的晶体管沟道区之间具有凹槽，晶体管栅极区域位于凹槽内并由绝缘侧墙隔离。
特别的，在本发明一实施例中，所述背照式图像传感器的浮置扩散区为位于凸起的半导体表面内；所述浮置扩散区通过浮置扩散区侧墙与转移晶体管的栅极区域隔离，降低寄生电容。
特别的，在本发明一实施例中，所述背照式图像传感器的光电二极管区域对应的半导体表面低于所述浮置扩散区对应的半导体表面大于等于100纳米。
本发明减少了原来传统的器件中由于浅槽隔离存在而需要的额外面积，在同样像素大小情况下，增加了感光器件填充率，提高了可用光的比例；由于浮置扩散区区域和光电二极管不在同一平面，与传统平面结构相比，本发明的浮置扩散区的结电容以及与转移晶体管之间寄生电容较小，转换增益(Conversion Gain)提高；Finfet晶体管结构可以保持晶体管有效沟道长度和宽度在同样面积的情况下有效尺寸更大，尤其是沟道宽度,同时Finfet结构可以大幅提高晶体管的跨导,从理论上，可以降低1/f噪声。而且，随着凸起结构宽度的缩小，沟道电流趋向于在体硅中流动，远离栅氧界面，从而避免了栅氧界面中的缺陷导致的噪声。本发明采用两次光刻形成内部具有凹槽的绝缘侧墙，在形成晶体管的栅极结构中更好控制工艺制程，形成栅极结构形状、界面更好。
附图说明
通过说明书附图以及随后与说明书附图一起用于说明本发明某些原理的具体实施方式，本发明所具有的其它特征和优点将变得清楚或得以更为具体地阐明。其中：
图1为现有图像传感器中像素单元的剖面结构示意图；
图2至图9为本发明一实施例中具有三维晶体管结构的背照式图像传感器的形成方法的各步骤结构示意图；
图10为本发明具有三维晶体管结构的背照式图像传感器的形成方法的流程图。
具体实施方式
现有图像传感器中，各晶体管(例如源跟随晶体管、转移晶体管和复位晶体管等)通常均为平面结构，因此，对应的像素单元具有诸多缺陷，例如：图像传感器的芯片面积难以进一步缩小，图像传感器的成本高居不下，图像传感器所形成的图像质量难以进一步提高，图像传感器的噪声水平难以降低，以及像素单元中光电转换元件的面积占有率难以提高等。
在现有图像传感器中，或采用3D晶体管应用于图像传感器的工艺设计中，但是晶体管的栅极区域的形成过程中，形成栅极区域的多晶硅刻蚀难以控制，导致形成的栅极区域的性能不好，界面良好性较差。
本发明提供一种具有三维晶体管结构的背照式图像传感器的形成方法，三维晶体管栅极结构的形成步骤包括：形成具有三维晶体管结构的源跟随晶体管和/或复位晶体管，所述源跟随晶体管和/或复位晶体管对应凸起结构；所述凸起结构周围形成绝缘侧墙,所述绝缘侧墙与凸起结构对应的晶体管沟道区之间形成凹槽，晶体管栅极区域形成于凹槽内并由绝缘侧墙隔离。
下面结合具体实施例，对本发明的技术方案进行详细说明。请参考图2至图9，图2至图9为本发明一实施例中具有三维晶体管结构的背照式图像传感器的形成方法的各步骤结构示意图。图2中，提供半导体衬底200，该半导体衬底200为制作图像传感器的载体，可以为硅晶圆；定义像素区和逻辑区，通过在半导体衬底表面铺设形成氮化硅220、光刻胶230刻蚀形成若干浅沟槽隔离结构(STI)210，浅沟槽隔离210之间具有若干凸起结构240。图3中，填充介质层250于浅沟槽隔离结构210中，进行化学机械抛光(CMP)。图4中，进行光刻，暴露出需要形成复位晶体管和/或源跟随晶体管的区域，需 要指出的是，复位晶体管和源跟随晶体管可以均设置于凸起结构240周围或可选的选择其一；在光刻后，可选择的由氮化硅220作为硬掩膜进行介质层刻蚀，介质层250为氧化硅、氮氧化硅等绝缘介质层；刻蚀后，去除氮化硅210，于凸起结构240的周围区域形成凹槽260，氮化硅220在形成凹槽220过程中为自对准刻蚀的硬掩膜。图5中再次对介质层250的部分区域进行刻蚀，去除后续形成的光电二极管270(PhotoDiode)上方的介质层，暴露出半导体表面，在后续形成的浮置扩散区280的凸起结构周围保留部分介质层；于源跟随晶体管和/或复位晶体管对应的凸起结构周围形成绝缘侧墙290，绝缘侧墙290与凸起结构240对应的晶体管沟道区之间为凹槽260，形成绝缘侧墙290的同时形成浮置扩散区侧墙300。图6于定义的各个区域进行离子注入或扩散完成后，在界面表面形成栅氧化层(未标注)，在栅氧化层(未标注)上铺设形成多晶硅层310。图7中，对多晶硅层310刻蚀。可选择的于多晶硅层310上形成一层防反射层(BARC)320，防反射层320起到平坦像素区区域的目的，在防反射层320表面形成光阻层330,在形成防反射层320的过程中：于光电二极管270区域靠近绝缘侧墙290的部分区域控制防反射层320形成的较厚。图8中，进行多晶硅刻蚀，使得晶体管栅极区域340形成于凹槽260内并由绝缘侧墙290隔离，绝缘侧墙290在刻蚀过程中具有自对准作用，并对刻蚀后形成栅极区域340进行隔离，并可以进一步降低设计尺寸。通过浮置扩散区侧墙300使得浮置扩散区280与转移晶体管栅极区域(未标注)隔离，可降低寄生电阻，提高图像传感器的性能。在本实施例中，浮置扩散区形成于一凸起区域对应的区域内，浮置扩散区280对应的半导体表面至少高于光电二极管330对应的半导体表面100纳米。图9中，采用现有工艺形成图像传感器的器件，最终形成具有三维晶体管结构的背照式图像传感器。
请继续参考图10，图10为本发明具有三维晶体管结构的背照式图像传感器的形成方法的流程图，形成方法包括：S101形成具有三维晶体管结构的源跟随晶体管和/或复位晶体管，所述源跟随晶体管 和/或复位晶体管对应凸起结构；S103所述凸起结构周围形成绝缘侧墙,所述绝缘侧墙与凸起结构对应的晶体管沟道区之间形成凹槽，晶体管栅极区域形成于凹槽内并由绝缘侧墙隔离。
本发明减少了原来传统的器件中由于浅槽隔离存在而需要的额外面积，在同样像素大小情况下，增加了感光器件填充率，提高了可用光的比例；由于浮置扩散区区域和光电二极管不在同一平面，与传统平面结构相比，本发明的浮置扩散区的结电容以及与转移晶体管之间寄生电容较小，转换增益(Conversion Gain)提高；Finfet晶体管结构可以保持晶体管有效沟道长度和宽度在同样面积的情况下有效尺寸更大，尤其是沟道宽度,同时Finfet结构可以大幅提高晶体管的跨导,从理论上，可以降低1/f噪声。而且，随着凸起结构宽度的缩小，沟道电流趋向于在体硅中流动，远离栅氧界面，从而避免了栅氧界面中的缺陷导致的噪声。本发明采用两次光刻形成内部具有凹槽的绝缘侧墙，在形成晶体管的栅极结构中更好控制工艺制程，形成栅极结构形状、界面更好。
虽然本发明披露如上，但本发明并非限定于此。任何本领域技术人员，在不脱离本发明的精神和范围内，均可作各种更动与修改，因此本发明的保护范围应当以权利要求所限定的范围为准。

Claims (10)

  1. 一种具有三维晶体管结构的背照式图像传感器的形成方法，其特征在于，所述三维晶体管栅极结构的形成步骤包括：
    形成具有三维晶体管结构的源跟随晶体管和/或复位晶体管，所述源跟随晶体管和/或复位晶体管对应凸起结构；
    所述凸起结构周围形成绝缘侧墙,所述绝缘侧墙与凸起结构对应的晶体管沟道区之间形成凹槽，晶体管栅极区域形成于凹槽内并由绝缘侧墙隔离。
  2. 根据权利要求1所述的具有三维晶体管结构的背照式图像传感器的形成方法，其特征在于，所述背照式图像传感器的浮置扩散区形成于凸起的半导体表面内；
    于形成绝缘侧墙的同时形成浮置扩散区侧墙，所述浮置扩散区通过浮置扩散区侧墙与转移晶体管栅极区域隔离，降低寄生电容。
  3. 根据权利要求2所述的具有三维晶体管结构的背照式图像传感器的形成方法，其特征在于，所述背照式图像传感器的光电二极管区域对应的半导体表面低于所述浮置扩散区对应的半导体表面大于等于100纳米。
  4. 根据权利要求3所述的具有三维晶体管结构的背照式图像传感器的形成方法，其特征在于，
    形成浅沟槽隔离结构，所述光电二极管区域位于浅沟槽隔离结构底部，定义浅沟槽隔离结构之间的凸起结构对应于源跟随晶体管、复位晶体管、浮置扩散区中的至少一个；
    形成绝缘层，填充浅沟槽隔离结构；
    于源跟随晶体管和/或复位晶体管沟道区的对应区域刻蚀部分绝缘层形成凹槽。
  5. 根据权利要求4所述的具有三维晶体管结构的背照式图像传感器的形成方法，其特征在于，所述凸起区域上还形成有氮化硅，以作为形成凹槽过程中自对准刻蚀的硬掩膜。
  6. 根据权利要求4所述的具有三维晶体管结构的背照式图像传感器的形成方法，其特征在于，于形成凹槽之后，刻蚀去除绝缘层，暴露出光电二极管区域，并形成绝缘侧墙；
    覆盖形成栅极氧化层、多晶硅层；
    刻蚀多晶硅层形成三维晶体管的栅极区域，其中所述绝缘侧墙在刻蚀中具有自对准作用，并对刻蚀后形成栅极区域进行隔离，降低设计尺寸。
  7. 根据权利要求6所述的具有三维晶体管结构的背照式图像传感器的形成方法，于覆盖形成栅极氧化层、多晶硅层的步骤后还包括：形成防反射层、光阻层。
  8. 一种具有三维晶体管结构的背照式图像传感器，其特征在 于，包括：
    具有三维晶体管结构的源跟随晶体管和/或复位晶体管；所述源跟随晶体管和/或复位晶体管对应凸起结构；
    所述凸起结构周围具有绝缘侧墙,所述绝缘侧墙与凸起结构对应的晶体管沟道区之间具有凹槽，晶体管栅极区域位于凹槽内并由绝缘侧墙隔离。
  9. 根据权利要求8所述的具有三维晶体管结构的背照式图像传感器，其特征在于，所述背照式图像传感器的浮置扩散区为位于凸起的半导体表面内；所述浮置扩散区通过浮置扩散区侧墙与转移晶体管的栅极区域隔离，降低寄生电容。
  10. 根据权利要求9所述的具有三维晶体管结构的背照式图像传感器，其特征在于，所述背照式图像传感器的光电二极管区域对应的半导体表面低于所述浮置扩散区对应的半导体表面大于等于100纳米。
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Families Citing this family (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN105185799A (zh) * 2015-08-18 2015-12-23 格科微电子（上海）有限公司 具有三维晶体管结构的背照式图像传感器及其形成方法
CN110164886B (zh) * 2019-04-28 2022-03-15 芯盟科技有限公司 图像传感器及其制作方法
CN110112166B (zh) * 2019-05-23 2021-07-13 德淮半导体有限公司 一种倾斜栅极背照式cmos图像传感器
CN112151557A (zh) * 2019-06-26 2020-12-29 格科微电子（上海）有限公司 Cmos图像传感器的实现方法
CN114334828A (zh) * 2020-10-10 2022-04-12 长鑫存储技术有限公司 半导体器件制造方法、半导体器件及存储器

Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20070108514A1 (en) * 2003-04-28 2007-05-17 Akira Inoue Semiconductor device and method of fabricating the same
CN101030602A (zh) * 2007-04-06 2007-09-05 上海集成电路研发中心有限公司 一种可减小短沟道效应的mos晶体管及其制作方法
CN102130171A (zh) * 2009-12-28 2011-07-20 索尼公司 半导体元件和用于制造半导体元件的方法
CN104022036A (zh) * 2013-02-28 2014-09-03 中芯国际集成电路制造(上海)有限公司 鳍式场效应晶体管的形成方法
CN105185799A (zh) * 2015-08-18 2015-12-23 格科微电子（上海）有限公司 具有三维晶体管结构的背照式图像传感器及其形成方法

Family Cites Families (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2002151688A (ja) * 2000-08-28 2002-05-24 Mitsubishi Electric Corp Ｍｏｓ型半導体装置およびその製造方法
KR100630704B1 (ko) * 2004-10-20 2006-10-02 삼성전자주식회사 비평면 구조의 트랜지스터를 구비한 ｃｍｏｓ 이미지 센서및 그 제조 방법
KR100644019B1 (ko) * 2005-06-17 2006-11-10 매그나칩 반도체 유한회사 씨모스 이미지센서 및 그 제조 방법
KR100712524B1 (ko) * 2005-08-09 2007-04-30 삼성전자주식회사 확장된 게이트 표면적을 갖는 드라이브 트랜지스터를구비한 ｃｍｏｓ 이미지 센서 및 그 제조방법
KR20080062052A (ko) * 2006-12-29 2008-07-03 동부일렉트로닉스 주식회사 씨모스 이미지 센서 및 그 제조방법
KR20140111492A (ko) * 2013-03-11 2014-09-19 삼성전자주식회사 반도체 장치
CN103928487B (zh) * 2014-05-08 2016-11-16 格科微电子（上海）有限公司 背照式图像传感器及其形成方法
US9443900B2 (en) * 2014-08-25 2016-09-13 Taiwan Semiconductor Manufacturing Co., Ltd. Pixel with multigate structure for charge storage or charge transfer

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20070108514A1 (en) * 2003-04-28 2007-05-17 Akira Inoue Semiconductor device and method of fabricating the same
CN101030602A (zh) * 2007-04-06 2007-09-05 上海集成电路研发中心有限公司 一种可减小短沟道效应的mos晶体管及其制作方法
CN102130171A (zh) * 2009-12-28 2011-07-20 索尼公司 半导体元件和用于制造半导体元件的方法
CN104022036A (zh) * 2013-02-28 2014-09-03 中芯国际集成电路制造(上海)有限公司 鳍式场效应晶体管的形成方法
CN105185799A (zh) * 2015-08-18 2015-12-23 格科微电子（上海）有限公司 具有三维晶体管结构的背照式图像传感器及其形成方法

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