CN100583448C - 场效应晶体管,特别是双扩散场效应晶体管,及其制造方法 - Google Patents
场效应晶体管,特别是双扩散场效应晶体管,及其制造方法 Download PDFInfo
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- 230000005669 field effect Effects 0.000 title claims abstract description 63
- 238000000034 method Methods 0.000 title claims description 23
- 238000004519 manufacturing process Methods 0.000 title description 8
- 239000011810 insulating material Substances 0.000 claims description 20
- 239000000758 substrate Substances 0.000 claims description 16
- 238000009792 diffusion process Methods 0.000 claims description 15
- 230000002146 bilateral effect Effects 0.000 claims description 10
- 239000000463 material Substances 0.000 claims description 10
- 239000004020 conductor Substances 0.000 claims description 7
- 239000004065 semiconductor Substances 0.000 claims description 7
- 239000013078 crystal Substances 0.000 claims description 6
- 230000015572 biosynthetic process Effects 0.000 claims description 5
- 229910021421 monocrystalline silicon Inorganic materials 0.000 claims description 2
- 238000009413 insulation Methods 0.000 abstract description 9
- 239000000203 mixture Substances 0.000 description 8
- 238000001259 photo etching Methods 0.000 description 8
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 7
- 238000005516 engineering process Methods 0.000 description 5
- 230000008569 process Effects 0.000 description 5
- 238000005530 etching Methods 0.000 description 4
- 238000002347 injection Methods 0.000 description 4
- 239000007924 injection Substances 0.000 description 4
- 230000003647 oxidation Effects 0.000 description 4
- 238000007254 oxidation reaction Methods 0.000 description 4
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 4
- 229920005591 polysilicon Polymers 0.000 description 4
- 230000008859 change Effects 0.000 description 3
- 239000000377 silicon dioxide Substances 0.000 description 3
- 235000012239 silicon dioxide Nutrition 0.000 description 3
- 239000002019 doping agent Substances 0.000 description 2
- 238000002955 isolation Methods 0.000 description 2
- 230000003071 parasitic effect Effects 0.000 description 2
- 229910052710 silicon Inorganic materials 0.000 description 2
- 239000010703 silicon Substances 0.000 description 2
- 230000004888 barrier function Effects 0.000 description 1
- 238000005452 bending Methods 0.000 description 1
- 239000003990 capacitor Substances 0.000 description 1
- 230000001413 cellular effect Effects 0.000 description 1
- 230000000295 complement effect Effects 0.000 description 1
- 238000009434 installation Methods 0.000 description 1
- 239000012774 insulation material Substances 0.000 description 1
- 238000001459 lithography Methods 0.000 description 1
- 229910052751 metal Inorganic materials 0.000 description 1
- 239000002184 metal Substances 0.000 description 1
- 229910044991 metal oxide Inorganic materials 0.000 description 1
- 150000004706 metal oxides Chemical class 0.000 description 1
- 238000001465 metallisation Methods 0.000 description 1
- 150000002739 metals Chemical class 0.000 description 1
- 230000005012 migration Effects 0.000 description 1
- 238000013508 migration Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 238000001020 plasma etching Methods 0.000 description 1
- 238000005498 polishing Methods 0.000 description 1
- 230000009183 running Effects 0.000 description 1
- 239000000126 substance Substances 0.000 description 1
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- H01L29/66712—Vertical DMOS transistors, i.e. VDMOS transistors
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Abstract
本发明主要涉及场效应晶体管(10),其中控制区(36)和连接区(40)被安置在其绝缘沟槽(134)内。利用这种装置可提供具有极佳电特性的场效应晶体管(10)。
Description
技术领域
本发明涉及场效应晶体管,它主要包含以下元素:
漂移区,
连接漂移区的沟槽,它包含一个沟槽边缘,一些侧壁和沟槽底。
场效应晶体管控制区,也叫做栅,它被安置在沟槽内。
两个场效应晶体管连接区,也称为源漏区,其中有电流流通,此电流也流过倒置沟道和漂移区,以及
形成场效应晶体管倒置沟道的本体区,它被电介质与控制区绝缘开。
背景技术
本发明涉及具有漂移路径的MOS晶体管或DMOS(双扩散金属氧化物半导体)晶体管,其中控制区和连接区的接点处在一个平面内,结果可以构成一个集成电路装置。例如在DMOS晶体管中,连接区和本体区是通过扩散产生的。漏区与漂移区相连接。源区与本体区相连接。
发明内容
本发明的一个目的是详细说明一种场效应晶体管,它的制造简单而且体积小,尤其是具有优良的电气特性。此外,还要详细说明一种制造场效应晶体管的方法。
此有关场效应晶体管的目的可以利用本发明的一种场效应晶体管来达到。
除了在上面引言中谈到的特征之外,本发明的场效应晶体管还包含以下特征:
在沟槽外安置一个连接区,最好按照连接形成场效应晶体管倒置沟道的区域的方式,以及
另一个连接区或其一部分安置在沟槽内,在沟槽内还有场效应晶体管的控制区,此另一个连接区最好是连接漂移区的连接区。
这意味着在本发明的场效应晶体管的情况下,控制区和连接区中的一个都是安置在同一个沟槽内。通过这种安置可以减少实际所需的芯片面积。尤其是当为了绝缘的目的而要求有沟槽时更是如此。让沟槽有一定深度还可以使漂移路径的长度可以承受例如小于30伏或小于40伏的漏-源极电压,或大于30伏或40伏,特别是小于100伏的电压。
按照本发明的装置还可获得具有低起始电阻率RON乘以面积和高单位面积饱和电流ISAT的场效应晶体管。控制区和连接区在沟槽内的安置使得生产方法中只需要不多的几个步骤。此外,实现不同的场效应晶体管电子特性也有多种途径。
按本发明的场效应晶体管的一种形式中,绝缘材料被安置在控制区下的沟槽底与控制区之间。控制区和绝缘材料间的边界处在包含控制区的沟槽上半部分或包含控制区的沟槽上1/3部分内。在一种改进形式中,两个区域间的边界与深沟槽底平行。带绝缘材料的区域用来设定漂移路径的长度。因此控制区只向下伸至例如500nm的深度。但是,沟槽内填充绝缘材料的最深位置还是到达例如1μm以上甚至8μm的深度。长的绝缘区域使得不需要额外的芯片面积就可得到高的介电强度。不过,绝缘区域也可以用在各边电绝缘的导电材料来填充。
在另一种形式中,沟槽伸到控制区下比伸到内连接区下更深一些。在一种改进的形式中,沟槽伸到控制区下比伸到内连接区下深一倍或两倍。此时漂移区处在深绝缘材料两侧,结果在相同的沟槽深度下漂移区的长度几乎加倍。
在另一种形式中,沟槽在内连接区下比在控制区下深。这种情况产生在浅沟槽的场合,即沟槽的深度小于1μm,特别是小于500nm的场合。在这种场合下,内连接区必须穿过浅沟槽的底部,才能与漂移区可靠地接触。
在另一种形式中,沟槽不含单晶半导体材料。沟槽可以简单方式用多晶半导体材料和电绝缘材料填充。
控制区按第一掺杂类型掺杂,最好是n型掺杂。在一种改进形式中,连接区同样也按第一掺杂类型掺杂,即n型掺杂,最好让连接区作重度的掺杂,例如每立方厘米有1019或1020掺杂原子。
形成倒置沟道的区域建议用P型掺杂。漂移区最好按第一掺杂类型尤其是n型掺杂。为产生较大的电压降,漂移区的掺杂比较轻。例如,掺杂区域每立方厘米有1015掺杂原子。
在另一个改进形式中,内连接区的掺杂比漂移区的掺杂更重。还有一种改进形式中,外连接区,漂移区和倒置沟道的连接区域被安置在单晶半导体材料(最好是单晶硅)内。
在另一种形式中,场效应晶体管被集成在一个集成电路内,在此集成电路内还装有其它用互连线连接的元件,例如用来驱动场效应晶体管的控制电路元件。但是,也可以把本发明的场效应晶体管或它的一种形式做成分离元件。
在一种形式中,此场效应晶体管包含一个比漂移区更重度掺杂的层,它将场效应晶体管与衬底绝缘,衬底则按与此重度掺杂层不同的掺杂类型掺杂。这种形式用在带双极晶体管和场效应晶体管的两种电路内,例如BiCMOS电路,以及当场效应晶体管是产生在这样一种集成电路内,其中只有场效应晶体管,而且除寄生晶体管外没有什么双极晶体管。
在另一种形式中,沟槽正好伸到重度掺杂层,使得重度掺杂层还用作漂移区的一个连接区。在还有一种形式中,沟槽被安置在离开重度掺杂层一个距离。利用这种结构,也可将沟槽和重度掺杂层间的区域用作漂移路径。
在另一种形式中,沟槽有两个末端,另一个控制区最好安置在沟槽内。在这种形式中,最好把沟槽做成直线形式。这种形式特别适合于一些特定的金属,此时由于电徙动过程只能携带特定的电流密度。
在另一种形式中,沟槽形成一个环,环形控制区最好围绕内连接区。利用这种环形沟槽可以在小的芯片面积上产生场效应晶体管。
本发明还涉及一种生产场效应晶体管的方法,特别是按本发明的场效应晶体管或其一种形式,使得上述技术措施可用于这种方法。在此方法中可以实施以下步骤,但对所列顺序没有任何限制:
在漂移区内引入沟槽,
用绝缘材料填充该沟槽,
将绝缘材料作成一定图形,由此在场效应晶体管的控制区产生切口,并在场效应晶体管的连接区产生切口,后一切口与前一切口是分开的,
最好在沟槽内至少一个连接区将栅氧化并开口,这可通过光刻步骤并将连接区内的栅氧化物刻蚀掉而实现,
将导电材料或可以转化为导电材料的材料引入两个切口内;导电材料一方面可用作栅,另一方面可用作单晶区域的漏极接点。
形成安置在沟槽外面的连接区,并在形成沟槽之前或之后形成构成场效应晶体管倒置沟道区的区域。
在一种形式中,沟槽至少在一个局部区域被加深而在至少另一个局部区域保持此沟槽深度,从而产生具有互不相同的沟槽深度的许多沟槽区域。这种形式不经额外的处理步骤就能实现,尤其是当包含场效应晶体管的集成电路内必须有深绝缘沟槽和浅绝缘沟槽时更是如此。
在本方法的一个形式中,各切口被一直刻蚀到沟槽底部,绝缘材料被移到控制区切口的沟槽壁区内。此后,借助热氧化,在控制区的切口内未被覆盖的沟槽壁区域上产生高质量氧化物,即栅氧化物,接着在加入导电材料之前再将此氧化物移到连接区的切口内。
在本方法的另一个实施例中,切口不一直开到沟槽底部,而让切口底部离开沟槽底部一个例如100nm以上的距离。但是,绝缘材料被移到控制区切口的一个沟槽壁区内。然后,借助于热氧化,在控制区切口内产生高质量的电介质。接着将连接区的切口一直加深到沟槽底部。
在本方法的另一个实施例中,连接区以连接沟槽边缘的方式产生在沟槽外面,此连接区最好具有单独的注入范围,其掺杂比连接区更轻。
附图说明
下面参照附图说明本发明的一些典型实施例,其中:
图1表示一个浅绝缘沟槽DMOS晶体管;
图2表示一个深绝缘沟槽DMOS晶体管;
图3表示一个具有变化沟槽深度的绝缘沟槽的DMOS晶体管;
图4表示一个环形DMOS晶体管;
图5表示一个条形DMOS晶体管。
具体实施方式
图1是一个DMOS晶体管10,它是一个集成电路的一部分。此集成电路做在衬底12上,后者由例如轻度P型掺杂硅构成。在衬底12的表面上是一个掺杂外延层14,其厚度大于1.5μm或大于2.0μm。
在n型外延层14内,随着衬底12距离的增加形成:
n型掺杂阱16,
P型掺杂沟道形成区18,20,和
在外延层14表面上重度n型掺杂的源连接区22,24,分别用于沟道连接区18和20的重度P型掺杂连接区26,28,以及分别用于源连接区22和24的轻度n型掺杂加长区域30,32。加长区域30,32可按需要选择,在另一个典型实施例中可以不用。
晶体管10的中心部分包含浅沟槽34,在此沟槽内有两个重度n型掺杂栅区域36,38安置在边缘区域,重度n型掺杂漏区40安置在中心部分。漏区40被绝缘区域42与栅区36隔离,并被绝缘区域44与栅区38隔离。绝缘区域42和44类似地处于沟槽34内。在沟槽34的沟槽壁和沟槽34的栅区36和38下面的沟槽底部上是一个薄绝缘层,它使栅区36和38与n型掺杂阱16隔离,并分别与沟道形成区18,20隔离,而且分别与加长区30和32隔离。作为例子,二氧化硅或某些其它材料适合用作绝缘材料。
还有另一些绝缘沟槽46至52与沟槽34一块形成,它们具有相同的深度,如0.5μm。晶体管10通过两个连接绝缘沟槽48和50以及下面将进一步说明的一些绝缘阱与集成电路装置的其它元件电绝缘。在一个典型实施例中,这两个绝缘沟槽48和50也是一个环形绝缘沟槽的一些区域(参见下面对图4的说明)。
在参照图1所作说明的典型实施例中,本体连接区26,源连接区22,和加长区30都处在绝缘沟槽48和沟槽34之间。加长区32,源连接区24,和本体连接区28都处在绝缘沟槽34和50之间。
和场效应工作的晶体管10并排,在它的右边和左边集成电路装置还有一些npn和pnp双极晶体管。在晶体管10的左边,有一个P型掺杂埋藏层54处于衬底12的区域和外延层14的区域内,此埋藏层用作绝缘双极晶体管。在晶体管10的右边,同样用作绝缘双极晶体管的埋藏层56和埋藏层54处在相同的高度上。埋藏层54通过外延层14表面上的P型掺杂连接区58和重度P型掺杂连接区60相连接。埋藏层56通过外延层14表面上的P型掺杂连接区62和重度P型掺杂连接区64相连接。连接区60处于绝缘沟槽46和58之间。与此相反,连接区64处于绝缘沟槽50和52之间。
位于场效应晶体管10下面的是一个重度n型掺杂的埋藏层70,它的一小部分处于外延层14内,而大部分处于p型掺杂衬底12内。埋藏层用来将晶体管10与衬底12绝缘。在另一个实施例中,不存在埋藏层。
没有外延层14也可制成晶体管10,例如在专门制作CMOS晶体管的工艺中就是这样。那时n型阱16延伸至p型掺杂衬底12内或者是n型衬底的p型阱内。
图1还显示了一些金属接点,即:
左侧本体接点72,通至本体连接区26,
左侧源接点74,通向源区22,
左侧栅接点76,通向栅区域36,
漏接点78,导电连至漏区40,
右侧栅接点80,连至栅区域38,
右侧源接点82,连至源区24,及
右侧本体接点84,连至连接区28。
如图1所示,左侧本体接点72和左侧源接点74彼此导电相连。另外,右侧源接点82和右侧本体接点84彼此导电相连。通常左侧源接点74也是导电连至右侧源接点82。同样左侧栅接点76和右侧栅接点80也彼此导电相连。在另一个典型实施例中,两个栅接点是彼此分别驱动的,因此不相连。这对两个源接点也同样适用。
漏区40穿过沟槽34并终止于n型阱16内,因而在晶体管10运行过程中,沿左侧沟道区86的方向从漏区40的下底部形成一个漂移路径,同时沿右侧沟道区88的方向从漏区40的下底部形成另一个漂移路径。沟道区的形成分别由栅区76和80上的电压控制。
在另一个典型实施例中,若用别的措施来防止寄生npn晶体管的产生,则在本体接点72,84和源接点74,82之间没有导电连接。n型阱16的掺杂取决于所需的晶体管10的介电强度。
图2是一个DMOS场效应晶体管110,除了下面说明的差别之外,它的结构和生产与场效应晶体管10类似,因此对上面图1已说明的那些元件不再作说明,这些元件在图2中具有相同的参考符号,不过在前面加个1。因此,晶体管110的n型阱116相当于晶体管10的n型阱16。
在晶体管110的情况下,沟槽134伸至埋藏层170。在图2所示的典型实施例情况下,沟槽134是一个深绝缘沟槽,其深度大于1μm,例如具有1.2μm的深度。与此相反,在另一个典型实施例中,沟槽134是一个浅绝缘沟槽。
栅区136和138仅伸至沟槽134的上部,例如从n型外延层114表面延伸0.5μm的深度。在栅区136下面远至沟槽底部的区域由绝缘区域142的绝缘材料填充,这种绝缘材料还进一步将栅区136与漏区140隔离。在栅区138下面远至沟槽底部的区域同样由绝缘区域144的绝缘材料填充,这种绝缘材料还进一步将栅区138与漏区140隔离。此漏区140穿过沟槽134的沟槽底部并终止于埋藏层170内。
在图2所示晶体管110的情况下,由于沟槽134的深度比沟槽34大(虽然它没有处在沟槽底部下面的一部分),在n型阱116内的漂移路径加长了,因此漏-源极电压可以较高。
在按图2所作改变的情况下,漂移电流还沿直线路径流动,因而不可能在弯折处形成峰值场,而按图1所作的改变则仍是这种情况,可看见沟槽34下部沟槽边缘处的弯折点。
在还有一种典型实施例中,晶体管110没有外延层,因而n型阱116伸至衬底112内。另一种带或不带外延层114的典型实施例中,不存在埋藏层170。
图3是一个DMOS 场效应晶体管210,除了下面谈到的差别外,它的结构和产生与场效应晶体管10类似,因此对上面图1已说明的那些元件不再作说明,这些元件在图3中具有相同的参考符号,不过在前面加个2。因此,晶体管210的n型阱216相当于晶体管10的n型阱16。
与晶体管10不同,对于晶体管210的情况不存在下面的元件:
外延层14,故n型阱216处在衬底212内,
埋藏层54和56,以及连接这些层的连接区。
晶体管210的中心沟槽234有一个中间浅沟槽区300,和两个处在栅区236和238下面的外深沟槽区302和304。深沟槽区242和244是电绝缘的并接纳绝缘区域242和244的下部。深沟槽区242和244伸至例如6μm甚至20μm的深度。漏连接区240处在沟槽234浅沟槽部分内,且终止于n型阱216内比浅沟槽区域300更深处,例如深100nm或200nm以上(如500nm)。由于有深沟槽区域302和304,漂移路径306和308的长度约比深沟槽区域的深度长一倍。当深沟槽区域的深度为5μm时,漂移路径306和308的长度将例如分别大于10μm。不需要增加芯片在横向方向的面积就可以获得这些长漂移路径。
晶体管210也可以有一个重度掺杂埋藏绝缘层。但是在另一个典型实施例中,深沟槽区域302和304未达到绝缘层那么远。但也可以采用外延层。
图4是一些环形DMOS晶体管400至410,它们的结构都象第一典型实施例中的晶体管10。在另一些典型实施例中,晶体管400至410的结构都与晶体管110或晶体管210类似。晶体管400至410是并联的,所以若把50或100个晶体管400至410并联,则可开关高达3A(安培)的电流。这么大的电流在驱动计算机硬盘等控制电路中是需要的。对于如图4所示的装置,所需的面积很小。
图5是一种条形DM0S晶体管420,其结构象第一典型实施例中的晶体管10,但在漏区440上面有两行漏接点478,479。根据要开关的电流可以自由选择晶体管420的长度L。此外,也可以将许多条形晶体管420互相并联。条形晶体管420特别适合于漏接点478,479的金属化只允许有限的电流流过的场合。
在另一些典型实施例中,如图4所示的一些变型配备着一些六角形(即蜂窝状)晶体管。
下面说明制造晶体管10的生产步骤。这时依次进行下列方法步骤:
在生长于衬底12上的外延层14上产生n型阱16,
借助于光刻技术并用硬掩模,刻蚀沟槽34和安装沟槽46至52,并接着用二氧化硅填充。然后采用CMP(化学机械抛光)工艺即普通STI(浅沟槽绝缘)等工艺,将二氧化硅平坦化。
借助另一层的光刻技术制造栅区36和38及漏区40等区域。然后,在这些区域刻蚀二氧化硅,使其停止于n型阱16的硅上。
借助于热氧化等在沟槽壁区域和未复盖的沟槽34的底部区域产生薄的电介质。
借助另一光刻技术选择漏区78的切口。然后,例如利用反应离子刻蚀或湿化学刻蚀再次清除在漏区78切口底部的薄绝缘层。
在下一个步骤中,将多晶硅淀积在栅区36,38及漏区40的切口内。多晶硅就地掺杂或利用后续的扩散或注入来掺杂。
借助CMP等方法使得重度n型掺杂的多晶硅平坦化。合适的话,也可以利用光刻把多晶硅移至沟槽34的外面。
利用光刻确定本体区18,20的位置。然后主要借助于扩散或注入将本体区作P型掺杂(或对于P沟道DMOS是n型掺杂)。此后或此前还可以产生互补场效应晶体管的n型阱。
借助光刻法界定连接区30,32,并利用扩散或注入等进行轻度n型掺杂。
借助另一光刻工艺界定源区22,24,接着例如利用扩散或注入等进行重度n型掺杂。以及
借助光刻法界定本体区18,20的连接区26,28,并接着进行重度P型掺杂。
外延层14,埋藏层70,以及如适合的话还有一些埋藏层,在进行上述各步骤之前产生,特别是当进行BiCMOS方法时,也就是说用这种方法来产生双极晶体管和场效应晶体管两种晶体管时。
生产晶体管110的方法基本采用相同的步骤。不过,首先是将连接区的切口只刻蚀到与栅区136,138的切口相同的深度,也即到小于沟槽134的沟槽深度一半的深度。然后产生薄栅氧化物层。只有在这之后才把漏区140的切口延长至沟槽134的沟槽底之外,正好进入埋藏层170或正好进入n型阱116。
当生产晶体管210时也采用类似的步骤。但是,深绝缘沟槽的沟槽刻蚀是在浅绝缘沟槽248,250和沟槽234浅部的刻蚀之后进行。在此过程中产生沟槽234的深沟槽区域302和304。另外,在此步骤中可以在集成电路(如所谓的沟槽电容器的存储单元阵列内)的其它位置产生深绝缘沟槽。
在另一个典型实施例中,借助同样的生产步骤,生产P型DMOS晶体管而非n型DMOS晶体管,不过是采用相反的掺杂。
将漏极和栅极合并安置在一个绝缘沟槽区域内,减少了实际需要的芯片面积。因而使起始电阻率RON降低。此外,比饱和电流ISAT增加。通过改变沟槽的深度或沟槽区域的深度,可以方便地建立能用于较大漏电压的漂移路径。
根据上述各典型实施例,每个沟槽有一个围绕它的沟槽边缘。该沟槽边缘是一条在外延层14或衬底14那个表面上围绕沟槽的闭合线,安置在沟槽外面的源连接区也处在此表面上。
Claims (10)
1.一种双扩散场效应晶体管(210),具有:
漂移区(216),
连接漂移区(216)的沟槽(234),所述沟槽包含沟槽边缘、一些侧壁和沟槽底,
场效应晶体管(210)的控制区(236),所述控制区被安置在所述沟槽(234)内,
所述场效应晶体管(210)的源连接区(222)和漏区(240),
形成场效应晶体管(210)的倒置沟道(286)的区域(218),所述区域通过电介质与所述控制区(236)隔离,
其中,所述源连接区(222)是安置在沟槽(234)的外面,而所述漏区(240)是安置在沟槽(234)内,
其中,所述沟槽(234)在至少一部分具有与另一个绝缘沟槽(248,250)相同的深度,所述另一个绝缘沟槽用于将场效应晶体管(210)与其它元件隔开,
其中,所述绝缘材料(242)被安置在所述控制区(236)下的沟槽底和所述控制区(236)之间;所述控制区(236)和所述绝缘材料(242)之间的最深边界被安置在包含所述控制区(236)的沟槽上半部分内,或在包含所述控制区(236)的沟槽上1/3部分内;以及
其中,所述沟槽(234)在所述控制区(236)下比在安置于所述沟槽(234)内的所述漏区(240)下深一些。
2.如权利要求1所述的双扩散场效应晶体管(210),其特征在于:边界平行于深沟槽底部。
3.如权利要求1所述的双扩散场效应晶体管(210),其特征在于:所述沟槽(234)在所述控制区(236)下比安置在所述沟槽(234)内的连接区(240)下深一倍或两倍。
4.如权利要求1所述的双扩散场效应晶体管(210),其特征在于:所述沟槽(234)不含单晶半导体材料,而且所述漂移区(216)按照第一掺杂类型掺杂,是n型掺杂;而且控制区(236)按照第一掺杂类型掺杂;而且所述源连接区(222,224)按照第一掺杂类型掺杂;而且形成倒置沟道(286)的区域(218)是按照一种不同类型掺杂,是P型掺杂;而且安置在沟槽(234)内的漏区(240)掺杂比所述漂移区(216)更重;而且未安置在沟槽(234)内的所述源连接区(222,224)、所述漂移区(216)和形成倒置沟道(286)的区域(218)被安置在单晶半导体材料内;而且所述场效应晶体管(210)被集成为包含多个互不相同的元件的集成电路装置。
5.如权利要求4所述的双扩散场效应晶体管(210),其特征在于:所述单晶半导体材料是单晶硅。
6.如权利要求1所述的双扩散场效应晶体管(10),其特征在于:比漂移区(16)更重度掺杂的一层(70)将场效应晶体管(10)与衬底(12)隔开,所述衬底(12)是按与该重度掺杂层不同的掺杂类型掺杂的。
7.如权利要求5所述的双扩散场效应晶体管(10),其特征在于:沟槽(34)和/或安置在沟槽(34)内的连接区(40)正好伸至重度掺杂层(70)内,或者所述沟槽(34)和/或者安置在沟槽(34)内的连接区(40)安置在离重度掺杂层(70)一定距离处。
8.如权利要求1所述的双扩散场效应晶体管(210),其特征在于:所述沟槽(234)有两个沟槽端,另一个控制区(238)安置在沟槽内,或者所述沟槽形成一环,环形控制区(236,238)是围绕安置在沟槽(34)内的漏区(240)。
9.一种生产双扩散场效应晶体管(210)的方法,包括以下各步骤,其实施不受所列顺序的任何限制:
在漂移区(216)内或安置漂移区(216)的区内引入沟槽(234),所述沟槽包含沟槽边缘、一些沟槽壁和沟槽底,
用绝缘材料(242,244)填充所述沟槽(234),
将绝缘材料(242,244)作成图形,由此为场效应晶体管(210)的控制区(36)产生切口,并为场效应晶体管(210)的连接区(240)产生切口,后一切口与前一切口通过绝缘材料(242,244)相隔离,该连接区与漂移区(216)相连接,
将导电材料(236,240)或可转变成导电材料(236,240)的材料引入两个切口内,
在产生沟槽(234)之前或之后,形成安置在沟槽(234)外面的源连接区(222),以及形成产生场效应晶体管(210)的倒置沟道区(286)的区域(218);
形成沟槽(234),使其在至少一部分具有与另一个绝缘沟槽(248,250)相同的深度,所述另一绝缘沟槽用于将场效应晶体管(210)与其它元件隔开,
在至少一个局部区域(302,304)内加深所述沟槽(234),
并在至少另一个局部区域保持此沟槽深度,产生具有相互不同的沟槽深度的沟槽区域。
10.如权利要求9所述的方法,其特征在于下面的步骤:
将切口一直开至沟槽底部,所述绝缘材料(242,244)被移至控制区(236)切口的至少一个沟槽壁区域内,
在所述控制区(236)的切口内和所述漏区(240)的切口内产生薄绝缘层,
在将材料(236,240)引进各切口之前,把连接区(240)的切口内的薄绝缘层移去,
其特征在于下面的步骤:
产生离沟槽底部一定距离的切口,所述绝缘材料(242,244)被移入所述控制区(236)的切口的至少一个沟槽壁区域内,
在控制区(236)的切口内产生薄绝缘层,
加深连接区(240)的切口,在产生薄绝缘层之后进行。
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DE10326523A DE10326523A1 (de) | 2003-06-12 | 2003-06-12 | Feldeffekttransistor, insbesondere doppelt diffundierter Feldeffekttransistor, sowie Herstellungsverfahren |
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CN101410987A (zh) * | 2006-03-28 | 2009-04-15 | Nxp股份有限公司 | 用于集成电路的功率半导体器件结构及其制造方法 |
DE102006027382A1 (de) * | 2006-06-13 | 2007-12-27 | Austriamicrosystems Ag | MOS Transistor mit modularem Layout |
US7595523B2 (en) | 2007-02-16 | 2009-09-29 | Power Integrations, Inc. | Gate pullback at ends of high-voltage vertical transistor structure |
US7859037B2 (en) | 2007-02-16 | 2010-12-28 | Power Integrations, Inc. | Checkerboarded high-voltage vertical transistor layout |
US20110084332A1 (en) * | 2009-10-08 | 2011-04-14 | Vishay General Semiconductor, Llc. | Trench termination structure |
JP5455801B2 (ja) * | 2010-06-10 | 2014-03-26 | 株式会社東芝 | 半導体装置 |
US8878295B2 (en) * | 2011-04-13 | 2014-11-04 | National Semiconductor Corporation | DMOS transistor with a slanted super junction drift structure |
CN102891170B (zh) * | 2011-07-19 | 2015-04-01 | 中芯国际集成电路制造(上海)有限公司 | Ldmos晶体管结构及其制造方法 |
CN103489904B (zh) * | 2012-06-11 | 2016-03-16 | 旺宏电子股份有限公司 | 半导体元件、其制造方法及其操作方法 |
US9006080B2 (en) * | 2013-03-12 | 2015-04-14 | Taiwan Semiconductor Manufacturing Company, Ltd. | Varied STI liners for isolation structures in image sensing devices |
US9437470B2 (en) | 2013-10-08 | 2016-09-06 | Cypress Semiconductor Corporation | Self-aligned trench isolation in integrated circuits |
US9543396B2 (en) | 2013-12-13 | 2017-01-10 | Power Integrations, Inc. | Vertical transistor device structure with cylindrically-shaped regions |
US10325988B2 (en) | 2013-12-13 | 2019-06-18 | Power Integrations, Inc. | Vertical transistor device structure with cylindrically-shaped field plates |
JP6413467B2 (ja) * | 2014-08-19 | 2018-10-31 | 富士電機株式会社 | 半導体装置 |
DE102015102115B3 (de) | 2015-02-13 | 2016-06-09 | Infineon Technologies Ag | Halbleitervorrichtung mit einem transistorarray und einem abschlussbereich und verfahren zum herstellen einer solchen halbleitervorrichtung |
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JPH02249276A (ja) | 1989-03-23 | 1990-10-05 | Seiko Epson Corp | 半導体装置 |
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JP2748072B2 (ja) * | 1992-07-03 | 1998-05-06 | 三菱電機株式会社 | 半導体装置およびその製造方法 |
JPH06104446A (ja) | 1992-09-22 | 1994-04-15 | Toshiba Corp | 半導体装置 |
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DE10223822A1 (de) * | 2001-05-30 | 2002-12-05 | Fuji Electric Co Ltd | Halbleiterbauteil und Verfahren zu seiner Herstellung |
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US20060125000A1 (en) | 2006-06-15 |
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