CN100570892C - 半导体器件及其制造方法 - Google Patents

半导体器件及其制造方法 Download PDF

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CN100570892C
CN100570892C CNB2007103056066A CN200710305606A CN100570892C CN 100570892 C CN100570892 C CN 100570892C CN B2007103056066 A CNB2007103056066 A CN B2007103056066A CN 200710305606 A CN200710305606 A CN 200710305606A CN 100570892 C CN100570892 C CN 100570892C
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drain electrode
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CN101211982A (zh
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张炳琸
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DB HiTek Co Ltd
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Abstract

提供了一种半导体器件及其制造方法。半导体器件包括在半导体衬底中的第一导电阱区和所述第一导电阱区上或其中的第二导电阱区。栅电极在所述第一沟槽中的栅极绝缘层上，所述沟槽在所述第二导电区域和所述第一导电阱区中。漏极包括漏极绝缘层、(多晶硅)屏蔽层、和漏极塞。漏极绝缘层在第二导电区域和第一导电阱区中的沟槽中。屏蔽层包围漏极塞。漏极塞的下部接触第二导电阱区。第一导电源极区在所述栅电极的侧面。

Description

半导体器件及其制造方法
技术领域
本发明的实施方案涉及半导体器件及其制造方法。
背景技术
沟槽金属氧化物半导体(MOS)晶体管与MOS晶体管的不同在于沟槽MOS晶体管的沟道形成在垂直方向。更常规的MOS晶体管的沟道形成在水平方向。沟槽MOS晶体管包含垂直沟道和形成在晶片背部中作为输出区域的漏极。
与更常规的MOS晶体管相比较，沟槽MOS晶体管适合于使用小面积的大电流和高电压操作。为了将高压施加于沟槽MOS晶体管，必须形成足够大长度的轻掺杂的漏极区(漂移区)。
因为电子在沟槽MOS晶体管中垂直地移动，所以通过调节垂直的掺杂分布(doping profile)，可以垂直地形成轻掺杂的漏极区以增加耐压，而不增加芯片的面积。因此，使用小面积可能实现高的耐压和大电流操作。然而，沟槽MOS晶体管的结构可以改变以在芯片上形成沟槽MOS晶体管作为CMOS晶体管。
发明内容
本发明的实施方案提供沟槽金属氧化物半导体(MOS)晶体管。
实施方案还提供可以以低成本在与互补金属氧化物半导体(CMOS)晶体管同样的芯片中形成的沟槽MOS晶体管。
在一个实施方案中，半导体器件(例如，沟槽MOS晶体管)包括：在半导体衬底中的第一导电阱区；第一导电阱区上(或第一导电阱区中)的第二导电阱区；在栅极绝缘层(也在第一沟槽中)上第一沟槽中的栅电极，所述沟槽在第二导电区域和(至少部分)第一导电阱区中；包括漏极绝缘层、(多晶硅)屏蔽层和漏极塞的漏极，所述漏极绝缘层在第二导电区域和(至少部分)第一导电阱区中的第二沟槽中，所述多晶硅层包围所述漏极塞，漏极塞的下部与第二导电阱区接触；和在栅电极侧面的第一导电的源极区。
在另一个实施方案中，提供制造半导体器件(例如沟槽MOS晶体管)的方法，所述方法包括：在半导体衬底中形成第一和第二导电阱区，所述第二导电阱区形成在第一导电阱区上或其中；除去第一导电区域和第二导电阱区的一部分以形成第一和第二沟槽；在第一沟槽中形成栅极氧化物层和在第二沟槽中形成漏极绝缘层；在沟槽中形成多晶硅层，其中多晶硅层填充第一沟槽和覆盖第二沟槽的侧壁；将第一导电掺杂剂离子注入栅极绝缘层上的多晶硅层中，以形成栅电极；除去漏极绝缘层的一部分并且通过用导电材料(例如重掺杂第一导电掺杂剂离子的多晶硅)填充第二沟槽形成漏极塞；和在栅电极的侧面形成第一导电源极区。
在附图和下文的说明中，阐述一个或多个实施方案的细节。其他特征将从说明书、附图和权利要求中显而易见。
附图说明
图1是说明根据一个示例性实施方案的半导体器件的视图。
图2～9是解释根据本发明实施方案的制造半导体器件的方法的视图。
图10显示根据图1的示例性半导体器件实施方案的示例性布局视图。
具体实施方式
现在将参考根据实施方案的附图来说明半导体器件和制造该半导体器件的方法。
图1是说明根据一个实施方案的半导体器件的视图。
参考图1，在半导体衬底10上的P-型外延层11中形成N-型埋层(NBL)13。外延层11可包含外延生长硅和/或硅-锗或基本上由其组成。在半导体衬底10中形成器件隔离层17以将半导体衬底10分为各区域。器件隔离层17可包含通过硅的局部氧化(LOCOS)或浅沟槽隔离(STI)形成的场氧化物层。水平互补金属氧化物半导体(CMOS)晶体管可以形成在由器件隔离层17所隔离的其他区域中。
在P-外延层11中的NBL 13上形成深N阱14，并且在p-外延层11中的深N阱14中或上面形成浅P阱16。
在半导体衬底10中形成沟槽，用于在半导体衬底10中形成一个或多个栅极30和漏极40。在图1中显示的示例性实施方案中，在两个栅极30之间形成单一漏极40。然而，栅极结构30也可以围绕漏极40形成单一环(unitary ring)，如图10中的示例性布局视图所示。
在栅极绝缘层18上形成栅电极20。在沟槽中形成氧化物层以形成栅极绝缘层18和漏极绝缘层19，通过化学气相沉积(CVD)在沟槽中沉积导体比如未掺杂的多晶硅。导体可包含其他材料，例如钨、硅化钨、铝、铜等，其可在导体与氧化物18和/或绝缘体19之间具有一个或多个粘合性层和/或阻挡衬垫层(例如，Ti、TiN、Ta、TaN、诸如Ti上TiN或Ta上TaN的双层等)。然后，在形成栅电极20时，将N型掺杂剂离子(例如P、As或Sb)注入未掺杂的多晶硅中，热处理所述多晶硅(例如通过退火)以形成栅电极20。
如下所述形成漏极40。在沟槽中形成氧化物层作为漏极绝缘层19(通常与栅极氧化物层18同时形成)，并顺序地形成未掺杂的多晶硅层21和二氧化硅22。类似栅电极20的情况，通过CVD在沟槽中沉积未掺杂的多晶硅或其他的导体(任选地与栅极20同时进行)以形成漏极塞23。漏极塞23包含多晶硅时，N型掺杂剂离子注入(未掺杂的)多晶硅(任选地与栅极20同时进行，当多晶硅在沟槽中的时候)。其后，热处理多晶硅(例如，通过退火，任选地与多晶硅栅极20同时进行)以形成漏极多晶硅层23。
在半导体衬底10的表面(例如浅P-阱16的暴露的或最上面的表面)中形成p+掺杂的体区25和N+掺杂的源极区24。
在形成漏极塞23之前，在N-阱14中形成深N区15，以便于电子从源极区24运动到漏极塞23。
在示例性半导体器件中，在中心部分中形成漏极40，在漏极40的侧面形成栅极30。因为在半导体器件中仅形成一个漏极40，所以可以减小半导体器件的尺寸。
因为电子在示例性半导体器件中垂直地移动，所以通过调节垂直的掺杂分布，可以垂直地形成低浓度漏极区以增加耐压，而不增加半导体器件的尺寸。因此，使用小面积可能实现高的耐压和大电流操作。
图2～9是解释根据本发明实施方案的制造半导体器件的方法的视图。
参考图2，通过注入N型掺杂剂离子到半导体衬底10的P-外延层11中形成NBL 13。然后，通过注入N型掺杂剂离子到p-外延层11中在NBL 13上形成深N阱14，通过注入p型掺杂剂离子(例如B)到p-外延层11中，在深N阱14中形成浅p阱16。在一个实施方案中，各每个相继在后面的注入的掺杂剂的剂量或浓度比之前注入的大。例如，深N阱14可具有比NBL 13更大的剂量或浓度，浅p阱16可具有比深N阱14更大的剂量或浓度。
然后，在半导体衬底10上形成器件隔离层17，以隔离示例性半导体器件(例如垂直MOS晶体管)与其中形成水平CMOS晶体管的半导体衬底10的区域。
参考图3，选择性地(例如通过光刻掩蔽和后续蚀刻)除去半导体衬底10的一部分以形成沟槽(边侧和中央的沟槽31和41)。边侧沟槽31用于形成栅极，中央沟槽41用于形成漏极。中央沟槽41的宽度可以为例如边侧沟槽31宽度的3到5倍。
参考图4，在沟槽31和41中形成氧化物层以形成栅极绝缘层18和漏极绝缘层19。氧化物层可以为热氧化物层(例如，通过湿或干热氧化生长的)或CVD氧化物(例如，通过化学气相沉积从硅和氧的前体比如硅烷气体或原硅酸四乙酯，和氧和/或臭氧分别地沉积)。
参考图5，通过CVD在半导体衬底10的整个表面上形成(例如通过共形沉积)未掺杂的多晶硅(或其他导体，比如钨、铝、氮化钛等)，然后通过各向异性刻蚀(例如反应性离子刻蚀)选择性地除去导体。结果，残留的导体(例如未掺杂的多晶硅)填充边侧沟槽31并覆盖中央沟槽41的侧壁。
然后，在导体是未掺杂的多晶硅时，通过注入N型掺杂剂离子到边侧沟槽31中的未掺杂多晶硅，然后热处理(例如退火)多晶硅以驱动掺杂剂，形成一个或多个栅电极20。
参考图6，在半导体衬底10的整个表面上形成氧化硅22(例如通过CVD或其它的共形沉积工艺)，然后通过各向异性刻蚀(例如反应性离子刻蚀)选择性地除去。结果，氧化硅22仅保持在沟槽41中，并且可以除去深阱14和浅阱16的水平表面上的暴露的热氧化物18/19。例如，在蚀刻期间，从沟槽41除去漏极绝缘层19的底部。
氧化硅22减少了漏极塞23(参考图8)和体区25(参考图8)之间的寄生电容，并增加了绝缘电压。
参考图7，N型掺杂剂离子通过沟槽41和漏极绝缘层19的被除去底部注入半导体衬底10(尤其是深的p阱16)中，以形成深的N区15。
参考图8，通过CVD或溅射将导电材料例如高浓度的N型多晶硅、钨、硅化钨、铝等沉积到沟槽41中，以形成漏极塞23。可以通过平坦化(例如，毯覆式干蚀刻和/或等离子蚀刻[例如，回蚀刻]，机械抛光或化学机械抛光[CMP])除去漏极塞23的多余沉积材料。
参考图9，在对将不被注入的区域(未显示)进行适当光刻掩蔽之后，将P型掺杂剂离子注入半导体衬底10以在半导体衬底10的表面部分中形成体区25，并(在随后除去体区掩模和将不注入的其他区域的光刻掩蔽之后)将N型掺杂剂离子注入半导体衬底10以在半导体衬底10的表面部分中形成源极区24。
在示例性实施方案中，可以与在CMOS晶体管中形成阱的过程一起实施形成NBL 13和深的N区15的过程。另外，在形成边侧和中央沟槽31和41之后，可以与形成CMOS晶体管的过程一起实施形成半导体器件的剩余过程(例如，可以同时生长CMOS晶体管栅极氧化物和垂直晶体管栅极氧化物层18，可以同时沉积栅极多晶硅和栅极或漏极导体20或23，可以同时对CMOS晶体管源极/漏极区和源极区24和体区25进行注入等)。因此，形成示例性半导体器件(例如，垂直CMOS晶体管)的大部分过程可以与形成CMOS晶体管的过程一起进行。因此，可以用更少的附加过程形成沟槽MOS晶体管。
在另一个实施方案中，可通过将不同的注入区中的离子杂质类型切换为互补类型来制备互补垂直CMOS晶体管(例如NBL 13可以为T-型而不是N-型，阱14可以为p-阱，浅阱16可以为N-阱等)。
根据所述半导体器件及其制造方法，可以以较低成本在与CMOS晶体管同样的芯片中形成沟槽MOS晶体管。
该说明书中，对于“任何实施方案”，“实施方案”，“示例性实施方案”等的任何引用表示关于所述“实施方案”记载的具体特征、结构或性能包含于根据本发明的至少任何实施方案中。这些表述在本说明书中不同地方的出现不必全部涉及相同的实施方案。另外，关于任何实施方案记载的具体特征、结构或性能，认为在本领域技术人员的范围内，能够将这些特征、结构或性能在其它的实施方案中实现。
尽管已经参考其许多说明性的实施方案说明了实施方案，应该理解本领域技术人员能够作出很多其它的改变和实施方案，这在本发明公开的原理的精神和范围内。更特别地，在所附权利要求的范围内的本发明组合排列的组合部件和/或排列中可能有各种的变化和改变。除组合部件和/或排列中的变化和改变之外，替代的用途对本领域技术人员也是显而易见的。

Claims (19)

1.一种半导体器件，包括：
在半导体衬底中的第一导电阱区；
所述第一导电阱区上的第二导电阱区；
在第一沟槽中的栅极绝缘层上的所述第一沟槽中的栅电极，所述第一沟槽在所述第二导电阱区和至少部分所述第一导电阱区中；
包括导电屏蔽层、漏极绝缘层、和漏极塞的漏极，所述漏极绝缘层在所述第二导电阱区和至少部分所述第一导电阱区中的第二沟槽中，所述导电屏蔽层包围所述漏极塞，所述漏极塞与所述第二导电阱区接触；和
在所述栅电极的侧面的第一导电源极区。
2.权利要求1的半导体器件，其中所述漏极还包括在所述漏极塞和所述导电屏蔽层之间的氧化硅层。
3.权利要求1的半导体器件，还包括在所述漏极塞和所述第一导电阱区之间的第一导电高浓度杂质区域。
4.权利要求1的半导体器件，其中所述漏极绝缘层在所述导电屏蔽层的侧面和底部上。
5.权利要求1的半导体器件，其中所述漏极绝缘层包括氧化物层。
6.权利要求1的半导体器件，还包括在所述第一导电阱区下的第一导电埋层。
7.权利要求1的半导体器件，其中所述第一导电源极区在所述栅电极的相对侧。
8.权利要求1的半导体器件，还包括在所述第一导电源极区侧面的第二导电的体区。
9.一种制造半导体器件的方法，所述方法包括：
在半导体衬底中形成第一和第二导电阱区，所述第二导电阱区形成在所述第一导电阱区上；
通过除去所述第二导电阱区和所述第一导电阱区的一部分形成第一和第二沟槽；
在所述第一沟槽中形成栅极绝缘层，在所述第二沟槽中形成漏极绝缘层；
形成导电层填充所述第一沟槽并覆盖所述第二沟槽的侧壁；
除去所述漏极绝缘层的一部分，并通过利用导电塞材料填充所述第二沟槽形成漏极塞；和
在所述第一沟槽中填充的所述导电层的侧面形成第一导电源极区。
10.权利要求9的方法，还包括在形成所述漏极塞之前在所述第二沟槽中的所述导电层的侧面上形成绝缘体。
11.权利要求9的方法，其中在利用导电塞材料填充所述第二沟槽形成漏极塞之前，所述方法还包括在所述第二沟槽之下的所述第一导电阱区的一部分中形成第一导电高浓度区域。
12.权利要求9的方法，还包括在形成所述第一导电阱区之前，形成第一导电埋层。
13.权利要求9的方法，还包括在除去所述漏极绝缘层的所述一部分之前，除去所述漏极绝缘层的底部。
14.权利要求9的方法，其中所述源极区形成在所述栅电极的相对侧。
15.权利要求9的方法，还包括在所述源极区的侧面形成第二导电的体区。
16.如权利要求9的方法，其中所述导电层包含多晶硅。
17.权利要求16的方法，还包括将第一导电类型的掺杂剂离子注入所述多晶硅以在所述第一沟槽中形成栅电极。
18.权利要求9的方法，其中所述导电塞材料包括重掺杂有第一导电类型掺杂剂离子的多晶硅。
19.如权利要求10的方法，其中所述绝缘体包括氧化硅。
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