CN205282482U - 集成电路晶体管器件和集成电路 - Google Patents

集成电路晶体管器件和集成电路 Download PDF

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CN205282482U
CN205282482U CN201521130324.3U CN201521130324U CN205282482U CN 205282482 U CN205282482 U CN 205282482U CN 201521130324 U CN201521130324 U CN 201521130324U CN 205282482 U CN205282482 U CN 205282482U
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semiconductor material
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柳青
J·H·张
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STMicroelectronics lnc USA
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Abstract

本申请涉及集成电路晶体管器件和集成电路。一种竖直结型场效应晶体管(JFET)由半导体衬底所支撑，该半导体衬底包括在该半导体衬底之内的掺杂有第一导电类型掺杂物的源极区。掺杂有该第一导电类型掺杂物的半导体材料鳍具有与该源极区接触的第一端、并且进一步包括第二端以及在该第一端和该第二端之间的多个侧壁。漏极区由从该鳍的第二端生长的第一外延材料形成并且掺杂有该第一导电类型掺杂物。栅极结构由从该鳍的这些侧壁生长的第二外延材料形成并且掺杂有第二导电类型掺杂物。根据本申请的方案，可以提供配置和操作改善的集成电路晶体管器件和集成电路。

Description

集成电路晶体管器件和集成电路
技术领域
本实用新型涉及集成电路并且具体地涉及使用具有竖直结的鳍制造的结型场效应晶体管(JFET)器件。
背景技术
现有技术教导了利用一个或多个结型场效应晶体管(JFET)器件形成集成电路。该JFET器件包括在栅极导体下方形成的结。由充当栅极的结施加场，而不是如常规的MOSFET型器件那样使用绝缘栅极。电流在位于栅极下方的掺杂半导体区中的栅极区和漏极区之间流动。通过将电压施加到栅极导体，耗尽电荷的区在掺杂半导体区中形成，以夹断导电路径并限制电流的流动。由于缺乏可用的移动电荷，耗尽区表现为绝缘结构。
常规的JFET器件针对在模拟设计中的使用是有吸引力的电路。该器件容易形成和操作。然而，这样的JFET器件受制于难以控制短沟道效应这一显著的缺点。此外，JFET器件的典型制造与主流CMOS制造技术不相容。因此在本领域中需要解决前述和其他问题以提供配置和操作改善的JFET器件，其中，该器件的制造与CMOS技术兼容。
实用新型内容
根据本申请实施例的一个方面，提供一种集成电路晶体管器件，其特征在于，包括：半导体衬底；在所述半导体衬底之内的掺杂有第一导电类型掺杂物的区；半导体材料鳍，所述半导体材料鳍具有与在所述半导体衬底之内的所述区接触的第一端并且具有第二端并且具有在所述第一端和所述第二端之间的多个侧壁，所述鳍掺杂有所述第一导电类型掺杂物；与所述半导体材料鳍的所述第二端接触的第一外延区，所述第一外延区掺杂有所述第一导电类型掺杂物；以及与所述半导体材料鳍的多个侧壁接触的第二外延区，所述第二外延区掺杂有第二导电类型掺杂物。
在一个实施例中，所述第一导电类型掺杂物为n型并且所述第二导电类型掺杂物为p型。
在一个实施例中，所述第一导电类型掺杂物为p型并且所述第二导电类型掺杂物为n型。
在一个实施例中，在所述半导体衬底之内的所述区的掺杂浓度超过了所述半导体材料鳍的掺杂浓度。
在一个实施例中，所述第二外延区的掺杂浓度超过了所述半导体材料鳍的掺杂浓度。
在一个实施例中，集成电路晶体管器件进一步包括在所述半导体衬底之内的所述区顶部的绝缘材料层，所述绝缘材料层将多个相邻的鳍的底部部分彼此隔离开。
在一个实施例中，所述集成电路晶体管器件是结型场效应晶体管器件，其中所述第二外延区包括栅极结构，在所述半导体衬底之内的所述区包括源极区并且所述第一外延区包括漏极区。
在一个实施例中，所述第一外延区由选自由以下各项组成的组的第一半导体材料形成：硅、硅锗和碳化硅。
在一个实施例中，所述第二外延区由选自由以下各项组成的组的第二半导体材料形成：硅、硅锗和碳化硅。
根据本申请实施例的另一方面，提供一种集成电路，其特征在于，包括：半导体衬底；在所述半导体衬底之内的掺杂有第一导电类型掺杂物的第一区；在所述半导体衬底之内的掺杂有第二导电类型掺杂物的第二区；第一半导体材料鳍，所述第一半导体材料鳍具有与在所述半导体衬底之内的所述第一区接触的第一端并且具有第二端并且具有在所述第一端和所述第二端之间的多个侧壁，所述鳍掺杂有所述第一导电类型掺杂物；第二半导体材料鳍，所述第二半导体材料鳍具有与在所述半导体衬底之内的所述第二区接触的第一端并且具有第二端并且具有在所述第一端和所述第二端之间的多个侧壁，所述鳍掺杂有所述第二导电类型掺杂物；与所述第一半导体材料鳍的所述第二端接触的第一外延区，所述第一外延区掺杂有所述第一导电类型掺杂物；与所述第二半导体材料鳍的所述第二端接触的第二外延区，所述第二外延区掺杂有所述第二导电类型掺杂物；与所述第一半导体材料鳍的多个侧壁接触的第三外延区，所述第三外延区掺杂有所述第二导电类型掺杂物；以及与所述第二半导体材料鳍的多个侧壁接触的第四外延区，所述第四外延区掺杂有所述第一导电类型掺杂物。
在一个实施例中，所述第一区、所述第一鳍、所述第一外延区和所述第三外延区形成第一极性型的第一竖直结型场效应晶体管，并且其中，所述第二区、所述第二鳍、所述第二外延区和所述第四外延区形成与所述第一极性型互补的第二极性型的第二竖直结型场效应晶体管。
在一个实施例中，在所述半导体衬底之内的所述第一区的掺杂浓度超过了所述第一半导体材料鳍的掺杂浓度，并且在所述半导体衬底之内的所述第二区的掺杂浓度超过了所述第二半导体材料鳍的掺杂浓度。
在一个实施例中，所述第一外延区的掺杂浓度超过了所述第一半导体材料鳍的掺杂浓度，并且所述第二外延区的掺杂浓度超过了所述第二半导体材料鳍的掺杂浓度。
在一个实施例中，所述第一、第二、第三和第四外延区各自由选自由以下各项组成的组的半导体材料形成：硅、硅锗和碳化硅。
根据本申请的方案，可以提供配置和操作改善的集成电路晶体管器件和集成电路。
附图说明
为了更好地理解实施例，现在将仅以示例方式参考附图，在附图中：
图1至图15C展示了形成竖直结型鳍式FET器件并且具体地在CMOS实现方式中的多个此类器件的多个工艺步骤。
具体实施方式
现在参考图1至图15C，其展示了形成竖直结型鳍式FET器件的工艺步骤。将理解的是，这些附图无需示出按比例绘制的特征。
图1示出了常规的体半导体衬底10，该体半导体衬底包括被保留以形成第一极性(n沟道)器件(NFET)的区域12和被保留以形成相反的第二极性(p沟道)器件(PFET)的区域14。例如，使用化学气相沉积(CVD)工艺在衬底10上沉积具有例如大约3nm厚度的二氧化硅(SiO2)层16。使用本领域的技术人员熟知的光刻技术，利用注入掩模封堵区域14并且在区域12中注入n型掺杂物(如，例如，砷或磷)以限定n型区18。此注入可以例如提供具有1×1018at/cm3至5×1018at/cm3的掺杂浓度的区18。使用本领域的技术人员熟知的光刻技术，利用注入掩模封堵区域12并且在区域14中注入p型掺杂物(如，例如，硼)以限定p型区20。此注入可以例如提供具有1×1018at/cm3至5×1018at/cm3的掺杂浓度的区20。区18和区20具有例如50-80nm的深度。
图2示出了在二氧化硅层16之上沉积氮化硅(SiN)层22。例如，可以使用化学气相沉积(CVD)工艺进行此沉积以提供具有30-50nm厚度的层22。此氮化硅层22形成硬掩模。
在本领域中已知的光刻工艺然后被用于从区18和区20的掺杂材料限定多个鳍40。对该硬掩模进行图案化，以在这些鳍40的期望位置处留下掩模材料24。然后穿过该掩模执行蚀刻操作，以在衬底10的区18和区20中在每个鳍40的每一侧上开出多个孔42。该蚀刻工艺的结果被展示在图3中，其中，每个鳍40具有在衬底处的第一端以及远端第二端。每个鳍40可以具有50nm至80nm的高度(h)。在优选实施例中，限定了这些鳍40的蚀刻延伸至区18和区20的全深度。在区域12和区域14的每个区中，这些鳍40可以具有6至15nm的宽度(w)和20nm至50nm的间距(p)。
接下来，封堵区域14(参考号50)并且在衬底10的区域12中注入(52)n型掺杂物(如，例如，砷或磷)以限定与在区域12中的这些鳍40的第一端接触的n型源极区54。此注入52可以例如提供具有1×1020at/cm3至5×1020at/cm3的掺杂浓度的源极区54，其超过了位于源极区54上方的这些鳍40中的每一个鳍中的掺杂浓度。结果在图4中示出。该遮蔽掩模(参考号50)然后被去除。
接着，封堵区域12(参考号60)并且在衬底10的区域14中注入(62)p型掺杂物(如，例如，硼)以限定与在区域14中的这些鳍40的第一端接触的p型源极区64。此注入62可以例如提供具有1×1020at/cm3至5×1020at/cm3的掺杂浓度的源极区64，其超过了位于源极区64之上的这些鳍40中的每一个鳍中的掺杂浓度。结果在图5中示出。该遮蔽掩模(参考号60)然后被去除。
然后在衬底10中形成浅沟槽隔离(STI)结构70，以将区域12和区域14分离开。STI结构70可以例如包括填充了在衬底10中形成的沟槽的二氧化硅材料。此绝缘材料进一步以层72覆盖了源极区54和64，以局部地将这些鳍40的底部部分彼此绝缘。局部绝缘层72可以例如具有20nm至30nm的厚度(因此，使每个鳍40的大约35nm至50nm被暴露)。STI结构70可以具有大约200nm的深度。
然后沉积氮化硅内衬80，以覆盖这些鳍40。例如，可以使用原子层沉积(ALD)工艺进行该沉积。内衬80可以例如具有2nm至6nm的厚度。结果在图7中示出。
接着，封堵区域14(参考号90)，在区域12中将内衬80从这些鳍40处去除(使用任何合适的湿法蚀刻或干法蚀刻技术)以暴露这些鳍40的这些侧壁，并且执行在本领域中已知的外延生长工艺以从并且接触每个鳍40的这些暴露的侧壁表面而生长硅或硅锗(SiGe)栅极结构92。因为在区域12中的这些鳍40是n型的，这些外延地生长的栅极结构92是p型的，以在这些鳍侧壁处形成p-n结。优选地，该外延生长被原位地掺杂有合适的p型掺杂物，如，例如，硼。栅极结构92可以例如具有1×1020at/cm3至5×1020at/cm3的掺杂浓度。外延生长工艺的结果在图8中示出。该遮蔽掩模(参考号90)然后被去除。
接下来，封堵区域12(参考号94，包括在这些栅极结构92上的新的氮化硅内衬(未明显地示出))，在区域14中将内衬80从这些鳍40处去除(使用任何合适的湿法蚀刻或干法蚀刻技术)以暴露这些鳍40的这些侧壁，并且执行在本领域中已知的外延生长工艺以从并且接触每个鳍40的这些暴露的侧壁表面而生长硅或碳化硅(SiC)栅极结构96。因为在区域14中的这些鳍40是p型的，这些外延地生长的栅极结构96是n型的，以在这些鳍侧壁处形成p-n结。优选地，该外延生长被原位地掺杂有合适的n型掺杂物，如，例如，砷。栅极结构96可以例如具有1×1020at/cm3至5×1020at/cm3的掺杂浓度。外延生长工艺的结果在图9中示出。该遮蔽掩模(参考号94，具有内藏的氮化硅内衬)然后被去除。
然后在衬底上沉积绝缘材料层100达到某个高度，该高度至少超过在每个鳍40的顶部上存在的掩模材料24的高度。该沉积工艺可以例如包括二氧化硅的化学气相沉积(CVD)。然后执行化学机械抛光，以使层100的顶表面平坦化达到与掩模材料24的顶部共面的水平。结果在图10中示出。
针对在区域12中的这些鳍40，掩模材料24(层16和层22的剩余图案化部分)被有选择地去除以形成多个开口102，这些开口暴露了在每个鳍40的远端第二端处的顶表面。在去除之前，可以在区域14中使用原子层沉积(ALD)工艺沉积氮化硅内衬(未明显地示出)。可以使用选择性蚀刻(如，例如，热磷酸蚀刻)来完成去除在区域12中的掩模材料24。结果在图11中示出。
然后执行在本领域中已知的外延生长工艺，以从并且接触每个鳍40的暴露顶表面而生长硅或碳化硅(SiC)漏极结构110。因为在区域12中的这些鳍40是n型的，这些外延地生长的漏极结构110也是n型的。优选地，该外延生长被原位地掺杂有合适的n型掺杂物，如，例如，磷。这些漏极结构110可以例如提供具有1×1020at/cm3至5×1020at/cm3的掺杂浓度，其超过了针对在区域12中的这些鳍40的掺杂浓度。外延生长工艺的结果在图12中示出。
针对在区域14中的这些鳍40，掩模材料24(层16和层22的剩余图案化部分)被有选择地去除以形成多个开口104，这些开口暴露了在每个鳍40的远端第二端处的顶表面。在去除之前，可以在区域12中使用原子层沉积(ALD)工艺沉积氮化硅内衬(未明显地示出)。可以使用选择性蚀刻(如，例如，热磷酸蚀刻)来完成去除在区域14中的掩模材料24。结果在图13中示出。
然后执行在本领域中已知的外延生长工艺，以从并且接触每个鳍40的暴露顶表面而生长硅或硅锗(SiGe)漏极结构112。因为在区域14中的这些鳍40是p型的，这些外延地生长的漏极结构112也是p型的。优选地，该外延生长被原位地掺杂有合适的p型掺杂物，如，例如，硼。这些漏极结构112可以例如提供具有1×1020at/cm3至5×1020at/cm3的掺杂浓度，其超过了针对在区域14中的这些鳍40的掺杂浓度。外延生长工艺的结果在图14中示出。
然后在绝缘材料层120的顶部上沉积预金属电介质(PDM)层。层120可以例如包括使用化学气相沉积工艺沉积达到50nm至500nm厚度的二氧化硅。然后使用本领域的技术人员已知的常规的蚀刻和填充技术形成到栅极结构92和94、源极区54和64以及漏极区110和112的多个电接触122。用于这些接触122的金属可以例如包括钨。如在图15A至图15C中所示，针对栅极结构92和94的这些接触122可能偏离于针对源极区54和64以及漏极区110和112的这些接触122。
前述的描述已经通过示例性且非限制性的示例，提供了对本实用新型的示例性实施例的全面且翔实的描述。然而，对于相关领域的技术人员而言，鉴于前述的描述，当结合附图和所附权利要求书来阅读本说明书时，各种修改和适配会变得明显。然而，对本实用新型教导的所有此类和类似的修改将仍然落入如所附权利要求书所确定的本实用新型的范围之内。

Claims (14)

1.一种集成电路晶体管器件，其特征在于，包括：
半导体衬底；
在所述半导体衬底之内的掺杂有第一导电类型掺杂物的区；
半导体材料鳍，所述半导体材料鳍具有与在所述半导体衬底之内的所述区接触的第一端并且具有第二端并且具有在所述第一端和所述第二端之间的多个侧壁，所述鳍掺杂有所述第一导电类型掺杂物；
与所述半导体材料鳍的所述第二端接触的第一外延区，所述第一外延区掺杂有所述第一导电类型掺杂物；以及
与所述半导体材料鳍的多个侧壁接触的第二外延区，所述第二外延区掺杂有第二导电类型掺杂物。
2.如权利要求1所述的集成电路晶体管器件，其特征在于，所述第一导电类型掺杂物为n型并且所述第二导电类型掺杂物为p型。
3.如权利要求1所述的集成电路晶体管器件，其特征在于，所述第一导电类型掺杂物为p型并且所述第二导电类型掺杂物为n型。
4.如权利要求1所述的集成电路晶体管器件，其特征在于，在所述半导体衬底之内的所述区的掺杂浓度超过了所述半导体材料鳍的掺杂浓度。
5.如权利要求1所述的集成电路晶体管器件，其特征在于，所述第二外延区的掺杂浓度超过了所述半导体材料鳍的掺杂浓度。
6.如权利要求1所述的集成电路晶体管器件，其特征在于，进一步包括在所述半导体衬底之内的所述区顶部的绝缘材料层，所述绝缘材料层将多个相邻的鳍的底部部分彼此隔离开。
7.如权利要求1所述的集成电路晶体管器件，其特征在于，所述集成电路晶体管器件是结型场效应晶体管器件，其中所述第二外延区包括栅极结构，在所述半导体衬底之内的所述区包括源极区并且所述第一外延区包括漏极区。
8.如权利要求1所述的集成电路晶体管器件，其特征在于，所述第一外延区由选自由以下各项组成的组的第一半导体材料形成：硅、硅锗和碳化硅。
9.如权利要求1所述的集成电路晶体管器件，其特征在于，所述第二外延区由选自由以下各项组成的组的第二半导体材料形成：硅、硅锗和碳化硅。
10.一种集成电路，其特征在于，包括：
半导体衬底；
在所述半导体衬底之内的掺杂有第一导电类型掺杂物的第一区；
在所述半导体衬底之内的掺杂有第二导电类型掺杂物的第二区；
第一半导体材料鳍，所述第一半导体材料鳍具有与在所述半导体衬底之内的所述第一区接触的第一端并且具有第二端并且具有在所述第一端和所述第二端之间的多个侧壁，所述鳍掺杂有所述第一导电类型掺杂物；
第二半导体材料鳍，所述第二半导体材料鳍具有与在所述半导体衬底之内的所述第二区接触的第一端并且具有第二端并且具有在所述第一端和所述第二端之间的多个侧壁，所述鳍掺杂有所述第二导电类型掺杂物；
与所述第一半导体材料鳍的所述第二端接触的第一外延区，所述第一外延区掺杂有所述第一导电类型掺杂物；
与所述第二半导体材料鳍的所述第二端接触的第二外延区，所述第二外延区掺杂有所述第二导电类型掺杂物；
与所述第一半导体材料鳍的多个侧壁接触的第三外延区，所述第三外延区掺杂有所述第二导电类型掺杂物；以及
与所述第二半导体材料鳍的多个侧壁接触的第四外延区，所述第四外延区掺杂有所述第一导电类型掺杂物。
11.如权利要求10所述的集成电路，其特征在于，所述第一区、所述第一鳍、所述第一外延区和所述第三外延区形成第一极性型的第一竖直结型场效应晶体管，并且其中，所述第二区、所述第二鳍、所述第二外延区和所述第四外延区形成与所述第一极性型互补的第二极性型的第二竖直结型场效应晶体管。
12.如权利要求10所述的集成电路，其特征在于，在所述半导体衬底之内的所述第一区的掺杂浓度超过了所述第一半导体材料鳍的掺杂浓度，并且在所述半导体衬底之内的所述第二区的掺杂浓度超过了所述第二半导体材料鳍的掺杂浓度。
13.如权利要求10所述的集成电路，其特征在于，所述第一外延区的掺杂浓度超过了所述第一半导体材料鳍的掺杂浓度，并且所述第二外延区的掺杂浓度超过了所述第二半导体材料鳍的掺杂浓度。
14.如权利要求10所述的集成电路，其特征在于，所述第一、第二、第三和第四外延区各自由选自由以下各项组成的组的半导体材料形成：硅、硅锗和碳化硅。
CN201521130324.3U 2015-04-02 2015-12-30 集成电路晶体管器件和集成电路 Active CN205282482U (zh)

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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN106057806A (zh) * 2015-04-02 2016-10-26 意法半导体公司 竖直结型鳍式fet器件及制造方法

Families Citing this family (13)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN107516649B (zh) * 2016-06-15 2020-05-05 中芯国际集成电路制造(上海)有限公司 半导体装置及其制造方法
US10008414B2 (en) * 2016-06-28 2018-06-26 Taiwan Semiconductor Manufacturing Co., Ltd. System and method for widening Fin widths for small pitch FinFET devices
US9799749B1 (en) * 2016-08-18 2017-10-24 International Business Machines Corporation Vertical transport FET devices with uniform bottom spacer
US9837553B1 (en) * 2016-09-30 2017-12-05 Globalfoundries Inc. Vertical field effect transistor
US10535652B2 (en) * 2016-10-27 2020-01-14 International Business Machines Corporation Fabrication of vertical fin field effect transistors having top air spacers and a self-aligned top junction
CN108695374B (zh) * 2017-04-10 2021-07-13 中芯国际集成电路制造(上海)有限公司 双极型晶体管及其形成方法
US10056379B1 (en) 2017-07-28 2018-08-21 International Business Machines Corporation Low voltage (power) junction FET with all-around junction gate
US10497796B1 (en) 2018-05-31 2019-12-03 International Business Machines Corporation Vertical transistor with reduced gate length variation
US10679993B2 (en) 2018-11-06 2020-06-09 International Business Machines Corporation Vertical fin field effect transistor devices with a replacement metal gate
CN111463173B (zh) * 2019-01-18 2023-04-28 中芯国际集成电路制造(上海)有限公司 半导体结构及其形成方法
US11637209B2 (en) * 2019-12-23 2023-04-25 Nexgen Power Systems, Inc. JFET with implant isolation
US11271108B2 (en) * 2020-04-08 2022-03-08 International Business Machines Corporation Low-noise gate-all-around junction field effect transistor
US11316064B2 (en) * 2020-05-29 2022-04-26 Globalfoundries U.S. Inc. Photodiode and/or PIN diode structures

Family Cites Families (23)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0715018A (ja) * 1993-06-15 1995-01-17 Toshiba Corp 電界効果トランジスタ
FR2776832B1 (fr) 1998-03-31 2000-06-16 Sgs Thomson Microelectronics Procede de fabrication de transistors jfet
US6943407B2 (en) * 2003-06-17 2005-09-13 International Business Machines Corporation Low leakage heterojunction vertical transistors and high performance devices thereof
KR100487567B1 (ko) * 2003-07-24 2005-05-03 삼성전자주식회사 핀 전계효과 트랜지스터 형성 방법
ATE546837T1 (de) * 2004-01-22 2012-03-15 Ibm Vertikal fin-fet-mos-vorrichtungen
US7485520B2 (en) * 2007-07-05 2009-02-03 International Business Machines Corporation Method of manufacturing a body-contacted finfet
US7927938B2 (en) * 2007-11-19 2011-04-19 Micron Technology, Inc. Fin-JFET
US7808042B2 (en) * 2008-03-20 2010-10-05 Micron Technology, Inc. Systems and devices including multi-gate transistors and methods of using, making, and operating the same
US7838913B2 (en) * 2008-05-28 2010-11-23 International Business Machines Corporation Hybrid FET incorporating a finFET and a planar FET
US8729627B2 (en) * 2010-05-14 2014-05-20 Taiwan Semiconductor Manufacturing Company, Ltd. Strained channel integrated circuit devices
US8207032B2 (en) * 2010-08-31 2012-06-26 Micron Technology, Inc. Methods of forming pluralities of vertical transistors, and methods of forming memory arrays
US8785285B2 (en) * 2012-03-08 2014-07-22 Taiwan Semiconductor Manufacturing Company, Ltd. Semiconductor devices and methods of manufacture thereof
US8716078B2 (en) * 2012-05-10 2014-05-06 Avogy, Inc. Method and system for a gallium nitride vertical JFET with self-aligned gate metallization
US8823065B2 (en) * 2012-11-08 2014-09-02 Taiwan Semiconductor Manufacturing Company, Ltd. Contact structure of semiconductor device
US8969963B2 (en) * 2012-10-12 2015-03-03 International Business Machines Corporation Vertical source/drain junctions for a finFET including a plurality of fins
US9029226B2 (en) * 2013-03-13 2015-05-12 Taiwan Semiconductor Manufacturing Company, Ltd. Mechanisms for doping lightly-doped-drain (LDD) regions of finFET devices
US9685380B2 (en) * 2013-05-31 2017-06-20 Stmicroelectronics, Inc. Method to co-integrate SiGe and Si channels for finFET devices
JP6138619B2 (ja) * 2013-07-30 2017-05-31 ルネサスエレクトロニクス株式会社 半導体装置の製造方法および半導体装置
US9406804B2 (en) * 2014-04-11 2016-08-02 Taiwan Semiconductor Manufacturing Company, Ltd. FinFETs with contact-all-around
US9391200B2 (en) * 2014-06-18 2016-07-12 Stmicroelectronics, Inc. FinFETs having strained channels, and methods of fabricating finFETs having strained channels
US9564518B2 (en) * 2014-09-24 2017-02-07 Qualcomm Incorporated Method and apparatus for source-drain junction formation in a FinFET with in-situ doping
US9543304B2 (en) * 2015-04-02 2017-01-10 Stmicroelectronics, Inc. Vertical junction FinFET device and method for manufacture
US9837553B1 (en) * 2016-09-30 2017-12-05 Globalfoundries Inc. Vertical field effect transistor

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN106057806A (zh) * 2015-04-02 2016-10-26 意法半导体公司 竖直结型鳍式fet器件及制造方法
CN106057806B (zh) * 2015-04-02 2020-05-05 意法半导体公司 竖直结型鳍式fet器件及制造方法

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