CN100565932C - 带有均匀掺杂沟道的低压高密度沟槽栅极功率器件及其边缘终止技术 - Google Patents

带有均匀掺杂沟道的低压高密度沟槽栅极功率器件及其边缘终止技术 Download PDF

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CN100565932C
CN100565932C CNB038100193A CN03810019A CN100565932C CN 100565932 C CN100565932 C CN 100565932C CN B038100193 A CNB038100193 A CN B038100193A CN 03810019 A CN03810019 A CN 03810019A CN 100565932 C CN100565932 C CN 100565932C
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曾军
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Abstract

本发明通过向沟槽底部注入掺杂剂，将低压沟槽MOSFET器件中的漂移区合并在一起，从而允许采用非常小的单元间距，从而实现非常高的沟道密度和均匀掺杂的沟道，并最终极大地降低沟道的电阻。通过选择适当的掺杂剂量和漂移区的退火参数，器件的沟道长度可以受到严格控制，并且沟道的掺杂可以进行的非常一致，与常规器件相比，本发明的域值电压被降低，其沟道电阻被减小，其漂移区的导通电阻也被减小。为了实现合并的漂移区，本发明融入了一种新的边缘终止设计，因此由P外延层和N+衬底形成的PN结能够在单元片的边缘处被终止。

Description

带有均匀掺杂沟道的低压高密度沟槽栅极功率器件及其边缘终止技术
技术领域
本发明涉及半导体功率器件及其制造方法，更具体地说，涉及低压垂直的金属氧化物半导体场效应晶体管(MOSFET)功率器件。
背景技术
近年来，在便携式个人电子产品领域，包括移动电话和笔记本电脑等产品呈现出爆炸式的增长。有计划有步骤地降低电源的电压，相应地缩小器件的尺寸和提高系统的性能，成为研发更先进的功率器件中的首要重点。整个系统电压的升降，要求功率管理电路中使用的功率MOSFET能够以较低的栅极驱动电压进行有效的开启和关闭。为了达到这一需要，功率半导体开关应具有较低的域值电压(1.0伏以下)。参见图1。为了降低域值电压，现有技术采用的是在P阱30中使用较低的注入剂量，加上使用更薄的栅极氧化物40。这种方法达到了降低的栅极额定值的目的，但这也有可能导致沟道泄漏电流的升高以及高温下工作性能的降低。由于该阱总的净电荷较低，这种方法还使该器件容易受到穿透性击穿的损害。此外，沟道内的掺杂是不均匀的。
另一项近期公开的现有技术(如图2所示)采用P型外延层(epi-layer)70来形成器件的沟道区。该器件的漂移区25是通过向沟槽(trench)底部55注入相反类型的掺杂剂，然后再经过一个退火步骤来形成的。因此，沟道区内的掺杂浓度是由外延层70的掺杂浓度所决定的，并且沿着器件沟道的掺杂分布是均匀的。对于特定的域值电压而言，这就产生了更高的总净电荷。因此，预计该器件的性能和关闭状态下的抗击穿特性将得到改进。在这项现有技术中，显然不允许相邻的漂移区25合并。该区域保持隔离状态以提供所谓的“bulkresurf”，因此该器件漂移区25的导通电阻就会被极大地降低[1]-[3]。
在本领域中众所周知的是，就低压功率器件而言(比如说30伏以下)，由漂移区25产生的导通电阻只占总导通电阻的极小部分。该器件的导通电阻的最主要的成分是该器件沟道区的电阻，为了降低沟道电阻，最有效的方法是减少器件的单位单元间距并加大沟道的密度。但不幸的是，像现有技术那样给漂移区25施用不予合并的条件，限制了在器件上实现单元间距的最小化和沟道密度的最大化。从而导致在使用低压产品时，现有技术的导通电阻居高不下。此外，从图2中可以明显看出，现有技术导致器件体二极管的PN结面积更大的，从而导致更高的输出电容。另外，体二极管的寄生BJT有着非常不统一的基底宽度，这就会降低体二极管的正向传导性和反向恢复特性。[4]
发明内容
本发明通过向沟槽底部注入掺杂剂来使低压沟槽MOSFET器件中的漂移区合并在一起，这种合并后的漂移区允许采用非常小的单元间距，从而实现了非常高的沟道密度并最终极大地降低了沟道的电阻。通过选择适当的掺杂剂量和漂移区的退火参数，器件的沟道长度可以受到严格控制，并且沟道的掺杂可以做的非常均匀，与常规器件相比，本发明的域值电压被降低，其沟道电阻被减小，而它的漂移区的导通电阻也被减小。为了实现合并的漂移区，本发明结合了一种新的边缘终止设计，因此由P外延层和N+衬底形成的PN结能够在单元品的边缘处终止。
与图1中的现有技术的器件相比，图2中更重度的P型外延层降低了导通电阻。此外，图2中隔离的漂移区提供了耗尽区来维持整个器件各处的反向电压更高。然而，要求漂移区隔离自然会降低器件中单元的密度。本发明通过采用更高度掺杂的P型外延层来提供较低的导通电阻，并通过允许漂移区合并来实现较高的单元密度。即使有了合并后的漂移区，仍然有足够的耗尽来支持较高的反向偏压。有了这项发明，沟道中的P掺杂就会比现有技术中带有外延层和隔离的漂移区的沟道更加恒定。本发明所提供的器件，比采用隔离的resurf区制成的器件具有更大的单元密度和更低的结电容。
本发明提供一种制造功率MOSFET的方法，包括下列步骤：在半导体衬底的表面形成带有开放区和闭合区的栅沟槽掩模；去除所述沟槽掩模的开放区暴露部位的半导体材料以形成多个栅沟槽；在所述沟槽的侧壁上形成牺牲栅极氧化物层；给衬底注入漂移区注入剂，所述注入剂穿透沟槽底板上的氧化物并被剩余的沟槽掩模阻止在衬底的表面；对衬底退火以扩散漂移注入剂，从而形成连续的漂移层并限定栅极的长度；去除沟槽掩模和牺牲氧化物并在沟槽的表面形成栅极氧化物；在衬底的表面和沟槽中积淀一层多晶硅；从半导体衬底的表面去除所述多晶硅并在栅极沟槽内留下足够的多晶硅，从而在沟槽内形成栅极；给衬底注入源掺杂剂从而在半导体衬底的表面形成源区，并提高沟槽内的多晶硅的导电性，以便在沟槽内形成栅极区；在衬底上沉积一层BPSG；去除至少部分该BPSG层以暴露具有源注入剂的部分表面；以及在衬底表面沉积一个导电层并形成图案以形成与源区的电接触。
根据本发明的上述方法，进一步包括下列步骤：在单元片的边缘蚀刻一个具有垂直面和水平凸缘的台阶，同时蚀刻沟槽；在靠近垂直面的上表面形成一个栅极滑道；在单元片边缘的水平凸缘内形成一个重掺杂的沟道阻止区，掺杂剂与源区具有相同极性；以及形成一个金属接触层在沟道阻止区之上并与之接触。
附图说明
图1显示的是采用低注入剂量和更薄的栅极氧化物的典型的现有技术器件。
图2显示的是采用外延层形成器件沟道区的典型现有技术器件。
图3表明本发明在第一实施例中大幅降低了沟道电阻。
图4表明本发明在第二实施例中沟道电阻有了更大幅度的降低。
图5表明本发明在第三实施例中沟道电阻有了幅度还要大的降低。
图5a显示的是图3、4、5中的三个实施例之间的对比。
图6至10表明本发明在制造过程中的重要步骤。
图11显示的是本发明沿着沟槽侧壁的掺杂分布。
图12显示的是现有技术的器件沿沟槽侧壁的掺杂分布。
图13显示的是本发明中掺杂浓度图表。
图14显示的是现有技术中最常用的边缘终止。
图15显示的是本发明所采用的边缘终止。
具体实施方式
本发明针对并解决现有技术器件中存在的上述问题。本发明的器件包括一个N+型衬底10，N型漂移区27，一个P型外延层72，沟槽80，栅极氧化物40，多晶硅50，BPSG 60，N+型源极区37，以及P+型主体区75。所描述的传导类型当然可以根据需要设置为反型。与现有技术形成对照的是，本发明将注入的漂移区27合并在一起。图2中的现有技术让各区保持隔离以提供bulk resurf效果，该效果降低了导通电阻并增加了反向电压条件下的耗尽，从而抬高了持续反向电压的限制。取代图2所示的P型外延层70和漂移区25之间的长而倾斜的边界90，本发明在P型外延层72和漂移区25之间产生如图3所示的更多级边界90a。在效果上，本发明极大地减少了外延层和漂移区之间的表面积，并将外延层与衬底完全隔离开来。合并漂移区就能允许采用极小的单元间距，从而导致极高的沟道密度。因此，本发明实现了沟道电阻的大幅降低。另外，器件的沟道长度可以通过优选地选择一个或多个参数来加以控制，这些参数包括但不仅限于注入剂量和注入剂类型，还有为施加掺杂剂的注入所进行的退火步骤的温度和时间。
举例来说，更短的沟道可以通过在漂移区注入后延长施加的时间来实现。更短的沟道长度实现了沟道电阻的极大降低。这一点在图3、4和5中已经做了描述，其中施加的时间从10分钟(图3)变为20分钟(图4)，再变为30分钟。注意到漂移区27的厚度逐渐增加，并且在漂移区和上面的外延层72之间的边界90a，90b和90c变平。此外，该器件在漂移区内的正向电流扩散，由于扩散的面积的加宽，随着施加时间的延长而变得更有效(顺序地参见图3至图5)。最终，漂移区的导通电阻被降低了。为了有助于让差别更明显，图5a用一个图表来说明三种不同的情况。
图3、图4和图5中的器件的正向导电性可以采用有限元方法来模拟。作为样本的器件导通电阻可以从模拟结果中提炼。图3、图4和图5中的器件的单位面积导通电阻分别为0.22Ω/cm2、0.18Ω/cm2和0.15Ω/cm2。所有器件的单元间距为2.0微米。此外，与图2所示的现有技术相比，新的器件的体二极管表明，如图3、4、5和5a所述，本发明具有小得多的PN结面积。另外，新器件的体二极管的寄生BJT的基础宽度变得更均匀。本发明器件的体二极管提供了改进的正向导电性和反向恢复特性。
在接下来的段落中描述的制造程序中，以一个30伏N沟道沟槽栅极(trench-gated)功率MOSFET为例，来展示如何实现本发明所公开的原理。这里只对重要的加工步骤做描述。
如图6至10所描述的那样，包含本发明的器件是采用创新工艺制造的。该工艺最初是选用由硅或其他适当的半导体材料制成N+衬底10，P型外延层72，以一种在本领域公知的方式在该衬底10上面生长，通过用适当的掩模覆盖外延层72，以使支持栅极结构的沟槽110打开。在一个实施例中，一个二氧化硅的硬掩模100在外延层72之上积淀或热生长。一层光致抗蚀剂被积淀在氧化物100之上，而后形成图案来暴露该氧化物的一些部分。氧化物100的暴露部分被适当的蚀刻剂去掉，来暴露外延层72上将要形成沟槽100的部分。随后衬底10被蚀刻以便从该衬底上去除外延材料并形成沟槽110。
下一步，一个相对薄的栅极氧化层120热生长在该沟槽暴露着的侧壁和底板表面上。然后该衬底被注入N型掺杂剂130，如磷或砷。遗留在外延层72上的氧化物掩模100阻止N型掺杂剂进入该层的上表面。在该沟槽侧壁和底板表面上的更薄的氧化物层120允许注入的N型离子130进入沟槽底板最近区域中的外延层72。
转向图9，硬掩模100从表面上被去掉，而注入的离子130通过退火作业被施加导入。施加导入的步骤使N型离子按垂直方向扩散，足以达到N+衬底，朝横向扩展到外延层72的较低部分，并且沿着外延层72的底部形成了未断裂的N型漂移区27。本领域技术人员将能够理解，N型区27的高度依赖于多种因素，包括但不仅限于所采用的掺杂剂的类型、注入时的能量、浓度以及退火或导入时间(drive-intime)。可以通过调整一种或一种以上的因素来实现区域27所需的净浓度和高度。
参见图10。剩下的步骤都是标准的，包括向沟槽内注入掺杂多晶硅，而后在多晶硅上蚀刻凹道，积淀层间r电解质层(例如BPSG)填充物60并蚀刻背面以形成自隔离埋置多晶硅栅。可以采用标准的程序来产生P+体75和N+源37，接着是前面和背面的金属化处理。
在前面的段落中详细描述的工序已经通过了模拟和验证。图1所示的现有技术也被模拟以便进行对比。图11给出了本发明公开的器件沿沟道侧壁的掺杂分布，表明该分布通过N+源区237，P型外延层272(沟道)，N型飘移区227以及N+衬底210。图12给出了现有技术器件沿着同样位置的掺杂分布，表明该分布通过N+源区237，P阱230(沟道)，外延层220以及N+衬底210。沟道的长度和沟道掺杂浓度已被理想地设计好，从而两种器件表现出了未被穿透的击穿特性。图11的新器件和图12的标准器件的漏源击穿电压分别为35伏和34伏。然而，新器件的域值电压为大约0.7伏，而标准型器件为2.0伏。图13显示出新型器件内部的掺杂浓度示意图，通过N+源区237，P+体区275，P型外延层272(沟道)以及N型飘移区227。栅极氧化物40、多晶硅50以及BPSG 60也在此显示以便清楚地说明。显然，掺杂浓度在沟道区272中几乎是恒定不变的。
最后必须指出的是，在新型器件中，由P外延层和N+衬底形成的PN结并不在硅的表面终止。其结果是，图1的常规器件中所使用的边缘终止不能被应用在本发明所公开的新型器件或图2的现有技术中。当前在常规的低压MOSFET中最常用的边缘终止在图14中做了描述，包括源金属337，栅极滑道金属(gate runner metal)350，PBSG360，场氧化物340，沟道阻止金属380，N+沟道阻止338，外延层20，以及衬底10。为了解决这一问题，本发明提供了一种新的边缘终止技术，如图15所示。单元片(die)的边缘被蚀刻掉，并且场氧化物340在蚀刻的边缘上生长。一层掺杂的多晶硅370形成在场氧化物之上，随后是绝缘的BPSG层360。在该层上制作有开口，以便金属栅极滑道350可以接触到多晶硅板层370。N+漂移接触区338形成在单元片的下外侧边缘，用以同边缘漂移区27接触。沟道阻止金属层380通过场氧化物340、多晶硅层370和BPSG层360上的适当开口与区域338相接触。这种新的边缘终止是通过采用与现行器件相同的工艺流程生产的。由于多晶硅场板370的部分(partials)和金属条350和380之间的金属空隙位于沿沟槽侧壁，新的边缘终止技术更有效地利用了硅的面积。此外，由于P外延层的掺杂浓度比图1中的标准器件的P阱的浓度更低，电场就会更多地扩散到P外延层。结果，对特定的击穿电压来说，新的边缘终止比常规的边缘终止呈现更小的横向维度。
参考文献
[1]科，美国专利US 4754310，1988年
[2]陈，美国专利US 5216275，1993年
[3]提汉伊，美国专利US 5438215，1995年
[4]《对功率MOSFET的体二极管进行优化以提高同步校验的效率》，作者：曾军，弗兰克·惠特利、里克·斯托克斯、克里斯·科肯、斯坦·本茨科斯基，2000年ISPSD，第145-148页。
本发明的结论、类型和范围
通过上述描述、附图和说明，本发明在提供一种低压高密度沟槽栅极的功率MOSFET器件方面的优势可谓清晰明了。
尽管上述描述、操作和说明材料存在许多具体特性，但这些具体特性不应被看作是对本发明的范围的限制，而只能被当作是对本发明的一些优选的实施例的描述和举例说明。
因此，本发明的范围是由附后的权利要求书及其法律等同物来决定的，而不是由上述实例所决定的。

Claims (2)

1.一种制造功率MOSFET的方法，包括下列步骤：
在半导体衬底的表面形成带有开放区和闭合区的栅沟槽掩模；
去除所述沟槽掩模的开放区暴露部位的半导体材料以形成多个栅沟槽；
在所述沟槽的侧壁上形成牺牲栅极氧化物层；
给衬底注入漂移区注入剂，所述注入剂穿透沟槽底板上的氧化物并被剩余的沟槽掩模阻止在衬底的表面；
对衬底退火以扩散漂移注入剂，从而形成连续的漂移层并限定栅极的长度；
去除沟槽掩模和牺牲氧化物并在沟槽的表面形成栅极氧化物；
在衬底的表面和沟槽中积淀一层多晶硅；
从半导体衬底的表面去除所述多晶硅并在栅极沟槽内留下足够的多晶硅，从而在沟槽内形成栅极；
给衬底注入源掺杂剂从而在半导体衬底的表面形成源区，并提高沟槽内的多晶硅的导电性，以便在沟槽内形成栅极区；
在衬底上沉积一层BPSG；
去除至少部分该BPSG层以暴露具有源注入剂的部分表面；以及
在衬底表面沉积一个导电层并形成图案以形成与源区的电接触。
2.根据权利要求1的方法，进一步包括下列步骤：
在单元片的边缘蚀刻一个具有垂直面和水平凸缘的台阶，同时蚀刻沟槽；
在靠近垂直面的上表面形成一个栅极滑道；
在单元片边缘的水平凸缘内形成一个重掺杂的沟道阻止区，掺杂剂与源区具有相同极性；以及
形成一个金属接触层在沟道阻止区之上并与之接触。
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US20040171198A1 (en) 2004-09-02
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US20080023759A1 (en) 2008-01-31
US6946348B2 (en) 2005-09-20
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US7633102B2 (en) 2009-12-15
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AU2003228499A1 (en) 2003-11-17
CN101071826A (zh) 2007-11-14
TWI225285B (en) 2004-12-11
US20050272208A1 (en) 2005-12-08
US20030205758A1 (en) 2003-11-06
CN100547808C (zh) 2009-10-07
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