WO2005088722A2 - Trench field effect transistor and method of making it - Google Patents

Trench field effect transistor and method of making it Download PDF

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Publication number
WO2005088722A2
WO2005088722A2 PCT/IB2005/050651 IB2005050651W WO2005088722A2 WO 2005088722 A2 WO2005088722 A2 WO 2005088722A2 IB 2005050651 W IB2005050651 W IB 2005050651W WO 2005088722 A2 WO2005088722 A2 WO 2005088722A2
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WO
WIPO (PCT)
Prior art keywords
trench
region
conductivity type
pillars
implant
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PCT/IB2005/050651
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French (fr)
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WO2005088722A3 (en
Inventor
Philip Rutter
Steven T. Peake
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Koninklijke Philips Electronics N.V.
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Priority to GBGB0404747.8A priority patent/GB0404747D0/en
Application filed by Koninklijke Philips Electronics N.V. filed Critical Koninklijke Philips Electronics N.V.
Publication of WO2005088722A2 publication Critical patent/WO2005088722A2/en
Publication of WO2005088722A3 publication Critical patent/WO2005088722A3/en

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    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L29/00Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof; Multistep manufacturing processes therefor
    • H01L29/02Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/08Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
    • H01L29/0843Source or drain regions of field-effect devices
    • H01L29/0847Source or drain regions of field-effect devices of field-effect transistors with insulated gate
    • H01L29/0852Source or drain regions of field-effect devices of field-effect transistors with insulated gate of DMOS transistors
    • H01L29/0873Drain regions
    • H01L29/0878Impurity concentration or distribution
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L29/00Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof; Multistep manufacturing processes therefor
    • H01L29/02Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/10Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode not carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
    • H01L29/1095Body region, i.e. base region, of DMOS transistors or IGBTs
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L29/00Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof; Multistep manufacturing processes therefor
    • H01L29/66Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76Unipolar devices, e.g. field effect transistors
    • H01L29/772Field effect transistors
    • H01L29/78Field effect transistors with field effect produced by an insulated gate
    • H01L29/7801DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
    • H01L29/7802Vertical DMOS transistors, i.e. VDMOS transistors
    • H01L29/7813Vertical DMOS transistors, i.e. VDMOS transistors with trench gate electrode, e.g. UMOS transistors
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L29/00Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof; Multistep manufacturing processes therefor
    • H01L29/02Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/08Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
    • H01L29/0843Source or drain regions of field-effect devices
    • H01L29/0847Source or drain regions of field-effect devices of field-effect transistors with insulated gate
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L29/00Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof; Multistep manufacturing processes therefor
    • H01L29/40Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/417Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions carrying the current to be rectified, amplified or switched
    • H01L29/41725Source or drain electrodes for field effect devices
    • H01L29/41766Source or drain electrodes for field effect devices with at least part of the source or drain electrode having contact below the semiconductor surface, e.g. the source or drain electrode formed at least partially in a groove or with inclusions of conductor inside the semiconductor
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L29/00Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof; Multistep manufacturing processes therefor
    • H01L29/40Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/423Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
    • H01L29/42312Gate electrodes for field effect devices
    • H01L29/42316Gate electrodes for field effect devices for field-effect transistors
    • H01L29/4232Gate electrodes for field effect devices for field-effect transistors with insulated gate
    • H01L29/42364Gate electrodes for field effect devices for field-effect transistors with insulated gate characterised by the insulating layer, e.g. thickness or uniformity
    • H01L29/42368Gate electrodes for field effect devices for field-effect transistors with insulated gate characterised by the insulating layer, e.g. thickness or uniformity the thickness being non-uniform
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L29/00Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof; Multistep manufacturing processes therefor
    • H01L29/66Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76Unipolar devices, e.g. field effect transistors
    • H01L29/772Field effect transistors
    • H01L29/78Field effect transistors with field effect produced by an insulated gate
    • H01L29/7801DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
    • H01L29/7802Vertical DMOS transistors, i.e. VDMOS transistors

Abstract

A trench FET includes drain region (20), source region (18) and body region (22) extending between the source region (18) and the drain region (20). Insulated gate trenches (10) control conduction. Deep pillars (32) of opposite conductivity type to the drain face one another below the bottom of the trench. The pillars (32) extend in the example about 0.6 micron below the bottom of the trench into the drain region (20). The pillars are provided to create depletion regions at the p-n junction between the pillars (32) and drain (20). When a source-drain voltage is applied the depletion regions from the pillars (32) on either side of the trench extend towards one another to shield the trench region from the drain (20).

Description

DESCRIPTION

TRENCH FIELD EFFECT TRANSISTOR AND METHOD OF MAKING IT The invention relates to a trench field effect transistor (Trench FET) and to a method of making it.

Trench FETs are commonly used, for example, in voltage regulator modules (VRMs) in power supplies for electronic equipment such as personal computers. Commonly, a pair of MOSFETs are used, known as a Control FET and a Sync FET. The ideal characteristics of these FETs differ slightly. For the Sync FET the conduction power loss should be as low as possible. Since the conduction power loss is proportional to the specific on-resistance (Rds.on), i.e. the on-resistance for unit area of substrate, this parameter should be reduced. For the Control FET on the other hand the switching loss should be minimised, which is proportional to the gate-drain charge density (Qgd), i.e. the gate-drain charge per unit area of substrate. A figure of merit (FOM) has been defined as the multiple of Rds.on and Qgd to provide an indication of how suitable a transistor is in for use in VRMs. Note that the smaller the FOM the better. There is a need for structures that provide an improved figure of merit. One way of improving the figure of merit is to achieve a low on-state resistance by increasing the channel width for a fixed area of silicon by decreasing the cell pitch. This however increases the total exposed area between gate and drain for unit surface area. However, this reduction in cell pitch is not necessarily attractive for the Control FET since in a conventional structure the gate drain charge density Qgd increases drastically with reduced size. Thus, simply reducing the size of the structure does not give improvements as large as might be expected. Another way of increasing the figure of merit is by choice of geometry.

A stripe geometry as compared to a hexagonal cell geometry has less gate- drain periphery for unit area, and corresponding lower gate-drain capacitance and switching losses. Although the improvement in switching loss is gained at the expense of on-state resistance the figure of merit is in general, though not always, better using stripes than a hexagonal geometry. A further method is to reduce the gate-drain periphery by etching a narrower trench. The gate-drain capacitance for a cell is determined by the width of the cell plus the length of the two trench sidewalls measured from the body-drain junction to the bottom of the trench. This means that reducing the trench width will reduce the overall gate-drain capacitance. A further possibility is to reduce the trench depth below the body-drain junction, though this is technically difficult. Another approach is to implant an arsenic donor region below the base of the trench to create a heavily doped enhanced conductivity drain region under the trench gate. An example of this approach is described in EP-A- 1041640. The heavily doped drain region allows the body-drain junction to be below the base of the trench, which eliminates the gate-drain capacitance contribution from the trench sidewalls, reducing the overall gate-drain capacitance. Secondly, the deeper body-drain junction results in a reduced depletion capacitance and again a reduced gate-drain capacitance. However, this arsenic doped structure also has downsides. The more heavily doped drain region reduces the breakdown voltage. Further, when the device is turned on, the geometry of the structure can cause severe pinching of the on-state current, leading to a significant increase in the resistance of the transistor in the on state. It would be beneficial to still further improve trench FETs.

According to the invention, there is provided a trench field effect transistor (trench FET), comprising: a semiconductor body defining opposed first and second major surfaces; an insulated gate extending from the first major surface vertically towards the second major surface in a gate trench having trench insulator on the sidewalls and base of the gate trench and a conductive gate electrode in the trench; a source region doped to be of first conductivity type at the first major surface adjacent to the gate trench; a body region under the source region doped to be of second conductivity type opposite to the first conductivity type; and a drain region of first conductivity type under the body region, wherein conductive pillars of second conductivity type are provided on either side of the gate trench and spaced away from the gate trench, the pillars being doped to have a concentration higher than the body region, the pillars extending from the first major surface into the drain region at least 0.2 micron past the bottom of the trench towards the second major surface forming a p-n junction with the drain region so that when a drain-source voltage is applied depletion regions in the drain region extend from the pillars on either side of the trench towards each other to shield the trench from the drain. The inventors have realised that the gate-drain capacitance and the specific on-resistance are not the only relevant criteria in determining the switching losses. The gate-drain charge is often considered to be determined by the gate-drain capacitance, but this is measured at zero voltage applied between drain and source (Vds = 0V). The switching properties however are determined by the charge not just at zero voltage but instead by the charge as the voltage across drain and source switches from the design voltage to zero as the device switches off. Thus, the inventors have realised that it is also benefical to reduce the gate-drain capacitance when the design voltage is applied between source and drain. This is particularly important for devices which operate with high drain-source voltages, such as laptops. Accordingly, the inventors have realised that it is possible to improve switching performance by reducing the gate-drain capacitance with voltage applied. In the arrangement according to the invention the conductive pillars on either side of the trench extend to a sufficient depth so that the depletion region at the p-n junction between the pillar and drain regions can extend toward each other as the device is switched off. Thus, although these pillars have little or no beneficial effect when zero voltage is applied between source and drain, as voltage between source and drain increases the depletion region between the pillars and the drain increases in size. The depletion regions on either side of the trench start to extend towards each other and so provide an increasing measure of shielding of the trench from the drain. This reduces the gate-drain charge. This may create the problem that the effect of the pillars would be to increase the specific on-resistance. Accordingly, in preferred embodiments of the invention there is further provided an sub-trench implant region of first conductivity type doped to have a higher dopant concentration than the drain region under the trench, wherein the pillars extend below the implant of first conductivity type so that when a drain-source voltage is applied depletion regions in the drain region extend from the pillars towards each other under the implant of first conductivity type either side of the trench to shield the trench from the drain. This sub-trench implant region prevents the implants impinging on the bottom of the trench at low bias. In typical embodiments the pillars extend to a depth of at least 0.5 micron deeper than the sub-trench implant region to allow sufficient depth for the depletion regions to be able to extend towards one another beneath the trench. In a preferred embodiment, the trench implant has an implant density in the range of 1016 cm"2 to 1017 cm"2 and the pillar implant has an implant density in the range 1015 cm"2 to 1016 cm"2. In another aspect, the invention relates to a method of making a trench FET, comprising the steps of: providing a substrate having a first major surface and doped to have a first conductivity type; forming gate trenches extending from the first major surface; forming gate insulator on the base and sidewalls of the gate trenches; forming source regions at the first major surface adjacent to the trench; and forming pillars of second conductivity type opposite to the first conductivity type in a region spaced laterally away from the trench to a depth at least 0.2 micron below the depth of the trench to form pillar regions extending below the trench. The step of forming pillars may comprise carrying out a pillar implant of dopants of second conductivity type to a depth of at least 0.2 micron below the depth of the trench. Alternatively, epitaxial techniques may be used. In embodiments, the body region is formed by implanting a body implant of second conductivity type opposite to the first conductivity type in the low- doped regions between the trenches. However, this is not the only means of forming the body region and in alternative embodiments a body region may be formed by carrying out an annealing step to diffuse dopants from the conductive pillars towards the trench. In this way a separate body implant and diffusion step is omitted, simplifying the process. The method may further include implanting dopants of first conductivity type at the base of the trench to form the sub-trench implant region. The1 method may further include carrying out a moat etch to a depth greater than the depth of the source regions from the first major surface, the moat etch being carried out in a region spaced laterally away from the trench. A single patterning step may be used to perform the moat etch and the step of carrying out a pillar implant so that the pillar implant is below the moat and both are spaced laterally away from the trench. In this way the need for separate patterning steps for both steps is obviated.

For a better understanding of the invention, a specific embodiment will now be described with reference to the accompanying Drawings, in which: Figure 1 shows an intermediate step in the manufacture of a first embodiment of the invention; and Figure 2 shows a first embodiment of the invention; Figure 3 shows the depletion boundary as voltage is applied to the first embodiment of the invention; and Figure 4 shows the gate voltage as a function of gate charge for a 25mm2 device. Note that the Figures are schematic and not to scale and that like or similar components are shown with the same reference numeral in different Figures.

Referring to Figure 1 , a 4.6 microns thick epilayer 4 is formed on the first major surface of an n+ (10 9 cm"3) doped silicon substrate 2. The epilayer is dped n type with a doping concentration of 2.77x1016 cm"3. A mask 6 is formed having trench windows 8 formed in stripes laterally across the substrate with a pitch of 2.5 microns. A trench etch step is carried out forming trenches 10, resulting in the structure shown in Figure 1. In the embodiment the trenches have a width of 0.5 micron and a depth of 0.8 micron. An arsenic (n-type) implant is then carried out into the base of the trench 10, through the windows 8 in mask 6 which is still in place. The implant is 4x1016 cm"3 and is carried out at 120keV. Note that where this specification refers to an implant being of n-type or p-type, what is meant is an implant that dopes the semiconductor to be n-type or p-type respectively. As the skilled person will appreciate, the choice of implant will depend on the semiconductor material used. Gate oxide 12 is then formed to a thickness of 38nm. A LOCOS process is then used to form a thick base oxide layer 14 at the bottom of the trench having a thickness of 100nm. The mask 6 is removed. Note that although the thick oxide layer 14 is beneficial, it is not required for the invention and a single uniform oxide thickness on the base and sidewalls of the trench may be used instead if required. A p-type body implant of 1.1x1013 cm"2 at 40keV is then carried out. Next, a p-type pillar implant is carried out again at a dose of 1.1x1013 cm"2 but the pillar implant is implanted at an energy of 220keV to make the pillar doping much deeper. An anneal of 20 minutes at 1050°C carried out. This anneal diffuses the body implant, as well as the pillar implant. The structure is then finished by deposition of a polysilicon gate 16 in the insulated trench, and implantation of a source region 18, as in a conventional trench FET. The source implant may be for example 5x1015 cm"2 at 120keV. In the example, a blanket source implant is carried out, i.e. a source implant over the whole structure, although this is not essential to the invention. A moat etch is then carried out to etch the semiconductor away from the trench to below the depth of the source 18, in the example to a depth of 0.5 micron. A contact implant is then carried out in the body to provide a good contact to the body. Source contact 28 and drain contact 30 are formed on the first and second major surfaces respectively. Source contact 28 contacts both source region 18 and body region 22. The skilled person will be aware of alternative approaches to contact the body and these may be used instead, for example, a masked source implant process. Figure 2 shows the finished result in which drain region 20 extends from the substrate 2, source region 18 is provided adjacent to the trench 10 at the first major surface and body region 22 extends between the source region 18 and the drain region 20. Note that the boundary between body region 22 and drain region 20 is deeper away from the trench owing to doped region 26 beneath the trench doped by the arsenic implant carried out into the trench. The trench is insulated by thin gate oxide 12 on the sidewalls of the trench 10 and thick oxide 14 at the base. A source contact 28 connects to source 18 and body 22 regions and a drain contact 30 connects to drain region 20. In the embodiment this is shown as a back contact but the skilled person will be aware of the possibility of forming a drain contact on the first major surface laterally spaced from the trenches, source and body and this alternative may be adopted if required. Note in particular the deep pillars 32 facing one another below the bottom of the trench. The pillars extend in the example about 0.6 micron below the bottom of the trench. Note however that the pillars 32 do not extend as far as the highly doped substrate 2 to avoid short-circuiting the structure. Figure 2 is somewhat schematic and it will be noted that because of the annealing steps there is no absolute boundary between pillars 32 and the body region 22, instead there is a region of high doping and a region of low doping. The depth of the pillar can be taken to be the depth of the p-n boundary between pillar 32 and drain region 20 at its deepest point. Nor will the pillars created by the method set out above be absolutely rectangular because the dopants implanted will again diffuse somewhat. A particular advantage of the method as set out above is that it is almost entirely compatible with standard manufacturing operations and the only significant difference is the deep p+ implants to form the "pillars". In use, with a voltage applied between source and drain, the depletion boundary 34 between the p-type pillars 32 and the n-type drain 20 starts to extend under the trench as illustrated in Figure 3 and this leads to a reduction in the gate-drain capacitance with voltage applied. Simulations of the properties of this structure have been carried out using a realistic model that takes account of the diffusions of the various dopants during annealing. A specific Rdson value at an applied gate voltage of 10V was calculated to be 27.5mΩ.mm2 which is a good value for this type of structure and demonstrates that the sub-trench implant 26 has succeeded in preventing the pillars excessively affecting the resistance in the on state. The device was calculated to have a breakdown voltage of about 28V. Figure 4 shows the gate voltage as a function of gate charge for a 25mm2 active area device with 12V across source and drain. The graphs gives a 5.5nC gate charge and hence the figure of merit may be calculated to be 27.5mΩ.mm2 x 5.5nC/25mm2 = 6.0nC.mΩ. This is a figure of merit that exceeds all devices of this type that the inventors are aware of and demonstrates that the approach of the invention offers real benefits. Moreover, the figure of merit is achieved using standard processes that require little change to existing manufacturing. The skilled person will realise that suitable doping levels and epilayer thicknesses will vary depending on the required breakdown voltage. For example, in the case of a 12V device a 2 microns epilayer might be used whereas in a 600V device or even a 1000V device a much thicker epilayer, for example 80 microns, might be needed to support the breakdown voltage when the device is switched off. In an alternative embodiment, the step of carrying out the first body implant is omitted and the body region is formed simply by the diffusion of the dopants in the pillar implant step during subsequent annealing. This alternative embodiment has the benefit of reducing by one the number of implant steps required. The skilled person will appreciate that a number of modifications may be made to the embodiments without departing from the scope of the invention. In particular, the n- and p- type regions may be interchanged. The invention is not just applicable to silicon as the semiconductor but may be applied in any suitable semiconductor including for example GaAs. Further, the device is of simple form and may be used not merely on a single crystal substrate but also as part of thin film transistors. From reading the present disclosure, other variations and modifications will be apparent to persons skilled in the art. Such variations and modifications may involve equivalent and other features which are already known in the design, manufacture and use of semiconductor devices and which may be used in addition to or instead of features described herein. Although claims have been formulated in this application to particular combinations of features, it should be understood that the scope of disclosure also includes any novel feature or any novel combination of features disclosed herein either explicitly or implicitly or any generalisation thereof, whether or not it mitigates any or all of the same technical problems as does the present invention. The applicants hereby give notice that new claims may be formulated to any such features and/or combinations of such features during the prosecution of the present application or of any further applications derived therefrom.

Claims

1. A trench field effect transistor (trench FET), comprising: a semiconductor body defining opposed first and second major surfaces; an insulated gate (16) extending from the first major surface vertically towards the second major surface in a gate trench (10) having insulator (12,14) on the sidewalls and base of the gate trench and a conductive gate electrode (16) in the trench; a source region (18) doped to be of first conductivity type at the first major surface adjacent to the gate trench (10); a body region (22) under the source region doped to be of second conductivity type opposite to the first conductivity type; and a drain region (20,2) of first conductivity type under the body region, wherein conductive pillars (32) of semiconductor doped to have the second conductivity type are provided on either side of the gate trench (10) and are spaced away from the gate trench (10), the pillars (32) being doped to have a concentration higher than the body region (22), the pillars extending from the first major surface into the drain region (20,2) at least 0.2 micron past the bottom of the trench (10) towards the second major surface so that the pillars (32) form a p-n junction with the drain region (20,2).
2. A trench FET according to claim 1 further comprising a sub- trench implant region (26) of first conductivity type under the trench (10), the implant region being doped to have a higher dopant concentration than the drain region (20) away from the trench, wherein the pillars (32) extend below the implant region (26) of first conductivity type so that when a drain-source voltage is applied depletion regions in the drain region extend from the pillars (32) towards each other under the implant region (26) of first conductivity type to shield the trench (10) from the drain.
3. A trench FET according to claim 2 wherein the pillars (32) extend to a depth of at least 0.3 micron deeper than the sub-trench implant region (26).
4. A trench FET according to any preceding claim wherein the trench implant has an implant density in the range of 1016 cm"2 to 1017 cm"2 and the pillar implant has an implant density in the range 1015 cm"2 to 1016 cm"2.
5. A method of making a trench FET, comprising the steps of: providing a substrate (2) having a first major surface and doped to have a first conductivity type; forming gate trenches (10) extending from the first major surface; forming gate insulator (12,14) on the base and sidewalls of the gate trenches; forming a body region (22) of second conductivity type opposite to the first conductivity type in the low-doped regions between the trenches; forming source regions (18) at the first major surface adjacent to the gate trenches (10); and forming pillars (32) of second conductivity type opposite to the first conductivity type in a region spaced laterally away from the trenches on both sides of the trenches to a depth at least 0.2 micron below the depth of the trenches (10) to form pillar regions (32) extending below the trench.
6. A method according to claim 5 further comprising implanting dopants (26) of first conductivity type at the base of the trenches (10).
7. A method according to claim 5 or 6 further comprising carrying out a moat etch to a depth greater than the depth of the source regions from the first major surface, the moat etch being carried out in a region spaced laterally away from the trench.
8. A method according to any of claims 5 to 7 wherein the step of forming pillars comprises carrying out a pillar implant of dopants of second conductivity type to a depth of at least 0.2 micron below the depth of the trench.
9. A method according to any of claims 5 to 8 wherein the step of forming the body region (22) includes implanting a body implant of second conductivity type opposite to the first conductivity type in the low-doped regions between the trenches.
10. A method according to any of claims 5 to 8 wherein the step of forming the body region (22) includes carrying out an annealing step to diffuse dopants from the conductive pillars (32) towards the trench.
PCT/IB2005/050651 2004-03-03 2005-02-23 Trench field effect transistor and method of making it WO2005088722A2 (en)

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Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5072266A (en) * 1988-12-27 1991-12-10 Siliconix Incorporated Trench DMOS power transistor with field-shaping body profile and three-dimensional geometry
WO1998004004A1 (en) * 1996-07-19 1998-01-29 Siliconix Incorporated High density trench dmos transistor with trench bottom implant

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5072266A (en) * 1988-12-27 1991-12-10 Siliconix Incorporated Trench DMOS power transistor with field-shaping body profile and three-dimensional geometry
WO1998004004A1 (en) * 1996-07-19 1998-01-29 Siliconix Incorporated High density trench dmos transistor with trench bottom implant

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