CN100561589C - 具有片内终止功能的半导体存储器芯片 - Google Patents
具有片内终止功能的半导体存储器芯片 Download PDFInfo
- Publication number
- CN100561589C CN100561589C CNB2006101320248A CN200610132024A CN100561589C CN 100561589 C CN100561589 C CN 100561589C CN B2006101320248 A CNB2006101320248 A CN B2006101320248A CN 200610132024 A CN200610132024 A CN 200610132024A CN 100561589 C CN100561589 C CN 100561589C
- Authority
- CN
- China
- Prior art keywords
- signal
- delay
- semiconductor memory
- circuit
- memory chips
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
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Classifications
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
- G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
- G11C7/1051—Data output circuits, e.g. read-out amplifiers, data output buffers, data output registers, data output level conversion circuits
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
- G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
- G11C7/1051—Data output circuits, e.g. read-out amplifiers, data output buffers, data output registers, data output level conversion circuits
- G11C7/1057—Data output buffers, e.g. comprising level conversion circuits, circuits for adapting load
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
- G11C7/22—Read-write [R-W] timing or clocking circuits; Read-write [R-W] control signal generators or management
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
- G11C7/22—Read-write [R-W] timing or clocking circuits; Read-write [R-W] control signal generators or management
- G11C7/222—Clock generating, synchronizing or distributing circuits within memory device
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
- G11C7/22—Read-write [R-W] timing or clocking circuits; Read-write [R-W] control signal generators or management
- G11C7/225—Clock input buffers
Landscapes
- Dram (AREA)
- Memory System (AREA)
- Logic Circuits (AREA)
Abstract
Description
Claims (17)
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2005307908A JP4524662B2 (ja) | 2005-10-21 | 2005-10-21 | 半導体メモリチップ |
JP2005307908 | 2005-10-21 |
Publications (2)
Publication Number | Publication Date |
---|---|
CN1953095A CN1953095A (zh) | 2007-04-25 |
CN100561589C true CN100561589C (zh) | 2009-11-18 |
Family
ID=38003124
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
CNB2006101320248A Expired - Fee Related CN100561589C (zh) | 2005-10-21 | 2006-10-19 | 具有片内终止功能的半导体存储器芯片 |
Country Status (4)
Country | Link |
---|---|
US (1) | US7688671B2 (zh) |
JP (1) | JP4524662B2 (zh) |
CN (1) | CN100561589C (zh) |
TW (1) | TWI314734B (zh) |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN103516348A (zh) * | 2012-06-27 | 2014-01-15 | 爱思开海力士有限公司 | 片上端接电路 |
Families Citing this family (14)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
KR101058468B1 (ko) | 2006-06-28 | 2011-08-24 | 아크로닉스 세미컨덕터 코포레이션 | 집적 회로용의 재구성 가능한 로직 패브릭과, 재구성 가능한 로직 패브릭을 구성하기 위한 시스템 및 방법 |
JP2009237678A (ja) | 2008-03-26 | 2009-10-15 | Fujitsu Microelectronics Ltd | メモリコントローラデバイス、メモリコントローラデバイスの制御方法およびデータ受信デバイス |
JP5654196B2 (ja) | 2008-05-22 | 2015-01-14 | ピーエスフォー ルクスコ エスエイアールエルPS4 Luxco S.a.r.l. | Dll回路ユニット及び半導体メモリ |
US8375241B2 (en) * | 2009-04-02 | 2013-02-12 | Intel Corporation | Method and system to improve the operations of a registered memory module |
JP5474458B2 (ja) * | 2009-09-10 | 2014-04-16 | ピーエスフォー ルクスコ エスエイアールエル | 半導体装置及びこれを備えるデータ処理システム |
US7900078B1 (en) * | 2009-09-14 | 2011-03-01 | Achronix Semiconductor Corporation | Asynchronous conversion circuitry apparatus, systems, and methods |
CN102279801B (zh) * | 2010-06-09 | 2014-12-17 | 晨星软件研发(深圳)有限公司 | 存储器共享系统及方法 |
KR101095007B1 (ko) * | 2010-09-30 | 2011-12-20 | 주식회사 하이닉스반도체 | 온 다이 터미네이션 신호 생성회로, 생성 방법 및 이를 이용하는 반도체 장치 |
JP2015035241A (ja) | 2013-08-09 | 2015-02-19 | マイクロン テクノロジー, インク. | 半導体装置 |
US9997220B2 (en) * | 2016-08-22 | 2018-06-12 | Micron Technology, Inc. | Apparatuses and methods for adjusting delay of command signal path |
US10153014B1 (en) | 2017-08-17 | 2018-12-11 | Micron Technology, Inc. | DQS-offset and read-RTT-disable edge control |
US10957365B2 (en) * | 2018-08-31 | 2021-03-23 | Micron Technology, Inc. | Setting local power domain timeout via temperature sensor systems and methods |
JP7110374B2 (ja) * | 2018-09-13 | 2022-08-01 | キオクシア株式会社 | メモリシステム及び制御方法 |
CN115602215A (zh) * | 2021-07-09 | 2023-01-13 | 长鑫存储技术有限公司(Cn) | 使能控制电路以及半导体存储器 |
Family Cites Families (10)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US6209071B1 (en) * | 1996-05-07 | 2001-03-27 | Rambus Inc. | Asynchronous request/synchronous data dynamic random access memory |
JPH1020974A (ja) | 1996-07-03 | 1998-01-23 | Fujitsu Ltd | バス構造及び入出力バッファ |
JP4178225B2 (ja) * | 1998-06-30 | 2008-11-12 | 富士通マイクロエレクトロニクス株式会社 | 集積回路装置 |
US7102200B2 (en) * | 2001-09-04 | 2006-09-05 | Intel Corporation | On-die termination resistor with analog compensation |
US6754132B2 (en) * | 2001-10-19 | 2004-06-22 | Samsung Electronics Co., Ltd. | Devices and methods for controlling active termination resistors in a memory system |
JP4317353B2 (ja) | 2001-10-19 | 2009-08-19 | 三星電子株式会社 | メモリシステムの能動終端抵抗の制御装置及び方法 |
KR100528164B1 (ko) * | 2004-02-13 | 2005-11-15 | 주식회사 하이닉스반도체 | 반도체 기억 소자에서의 온 다이 터미네이션 모드 전환회로 및 그 방법 |
KR100596781B1 (ko) * | 2004-04-28 | 2006-07-04 | 주식회사 하이닉스반도체 | 온 다이 터미네이션의 종단 전압 조절 장치 |
US7245552B2 (en) * | 2005-06-22 | 2007-07-17 | Infineon Technologies Ag | Parallel data path architecture |
JP4930875B2 (ja) * | 2005-09-29 | 2012-05-16 | 株式会社ハイニックスセミコンダクター | オンダイターミネーション制御装置 |
-
2005
- 2005-10-21 JP JP2005307908A patent/JP4524662B2/ja not_active Expired - Fee Related
-
2006
- 2006-10-19 US US11/582,981 patent/US7688671B2/en active Active
- 2006-10-19 CN CNB2006101320248A patent/CN100561589C/zh not_active Expired - Fee Related
- 2006-10-20 TW TW095138661A patent/TWI314734B/zh not_active IP Right Cessation
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN103516348A (zh) * | 2012-06-27 | 2014-01-15 | 爱思开海力士有限公司 | 片上端接电路 |
CN103516348B (zh) * | 2012-06-27 | 2017-09-15 | 爱思开海力士有限公司 | 片上端接电路 |
Also Published As
Publication number | Publication date |
---|---|
TWI314734B (en) | 2009-09-11 |
JP4524662B2 (ja) | 2010-08-18 |
TW200729209A (en) | 2007-08-01 |
JP2007115366A (ja) | 2007-05-10 |
US20070103188A1 (en) | 2007-05-10 |
US7688671B2 (en) | 2010-03-30 |
CN1953095A (zh) | 2007-04-25 |
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Legal Events
Date | Code | Title | Description |
---|---|---|---|
C06 | Publication | ||
PB01 | Publication | ||
C10 | Entry into substantive examination | ||
SE01 | Entry into force of request for substantive examination | ||
C14 | Grant of patent or utility model | ||
GR01 | Patent grant | ||
C56 | Change in the name or address of the patentee |
Owner name: ELPIDA MEMORY, INC. Free format text: FORMER NAME: ELPIDA MEMORY INC. |
|
CP01 | Change in the name or title of a patent holder |
Address after: Tokyo, Japan Patentee after: Nihitatsu Memory Co., Ltd. Address before: Tokyo, Japan Patentee before: Elpida Memory Inc. |
|
ASS | Succession or assignment of patent right |
Owner name: PS4 LASCO CO., LTD. Free format text: FORMER OWNER: NIHITATSU MEMORY CO., LTD. Effective date: 20130905 |
|
C41 | Transfer of patent application or patent right or utility model | ||
TR01 | Transfer of patent right |
Effective date of registration: 20130905 Address after: Luxemburg Luxemburg Patentee after: ELPIDA MEMORY INC. Address before: Tokyo, Japan Patentee before: Nihitatsu Memory Co., Ltd. |
|
CF01 | Termination of patent right due to non-payment of annual fee |
Granted publication date: 20091118 Termination date: 20151019 |
|
EXPY | Termination of patent right or utility model |