CN100538880C - 半导体存储器件 - Google Patents

半导体存储器件 Download PDF

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Publication number
CN100538880C
CN100538880C CNB2005100626904A CN200510062690A CN100538880C CN 100538880 C CN100538880 C CN 100538880C CN B2005100626904 A CNB2005100626904 A CN B2005100626904A CN 200510062690 A CN200510062690 A CN 200510062690A CN 100538880 C CN100538880 C CN 100538880C
Authority
CN
China
Prior art keywords
clock signal
data
phase
circuit
signal
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
CNB2005100626904A
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English (en)
Chinese (zh)
Other versions
CN1674150A (zh
Inventor
奥田正树
小林広之
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Socionext Inc
Original Assignee
Fujitsu Semiconductor Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Semiconductor Ltd filed Critical Fujitsu Semiconductor Ltd
Publication of CN1674150A publication Critical patent/CN1674150A/zh
Application granted granted Critical
Publication of CN100538880C publication Critical patent/CN100538880C/zh
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

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    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C8/00—Arrangements for selecting an address in a digital store
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/02—Detection or location of defective auxiliary circuits, e.g. defective refresh counters
    • G11C29/028—Detection or location of defective auxiliary circuits, e.g. defective refresh counters with adaption or trimming of parameters
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
    • G11C11/407—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
    • G11C11/4076—Timing circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/02—Detection or location of defective auxiliary circuits, e.g. defective refresh counters
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
    • G11C29/50—Marginal testing, e.g. race, voltage or current testing
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/56—External testing equipment for static stores, e.g. automatic test equipment [ATE]; Interfaces therefor
    • G11C29/56012—Timing aspects, clock generation, synchronisation
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/22—Read-write [R-W] timing or clocking circuits; Read-write [R-W] control signal generators or management 
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/22—Read-write [R-W] timing or clocking circuits; Read-write [R-W] control signal generators or management 
    • G11C7/222—Clock generating, synchronizing or distributing circuits within memory device
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Computer Hardware Design (AREA)
  • Dram (AREA)
CNB2005100626904A 2002-05-09 2002-11-29 半导体存储器件 Expired - Fee Related CN100538880C (zh)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP2002134073A JP2003331577A (ja) 2002-05-09 2002-05-09 半導体記憶装置
JP134073/2002 2002-05-09

Related Parent Applications (1)

Application Number Title Priority Date Filing Date
CNB021526753A Division CN1212666C (zh) 2002-05-09 2002-11-29 半导体存储器件

Publications (2)

Publication Number Publication Date
CN1674150A CN1674150A (zh) 2005-09-28
CN100538880C true CN100538880C (zh) 2009-09-09

Family

ID=29397444

Family Applications (3)

Application Number Title Priority Date Filing Date
CNB2005100626904A Expired - Fee Related CN100538880C (zh) 2002-05-09 2002-11-29 半导体存储器件
CNB021526753A Expired - Fee Related CN1212666C (zh) 2002-05-09 2002-11-29 半导体存储器件
CNB2005100626891A Expired - Fee Related CN100511472C (zh) 2002-05-09 2002-11-29 半导体存储器件

Family Applications After (2)

Application Number Title Priority Date Filing Date
CNB021526753A Expired - Fee Related CN1212666C (zh) 2002-05-09 2002-11-29 半导体存储器件
CNB2005100626891A Expired - Fee Related CN100511472C (zh) 2002-05-09 2002-11-29 半导体存储器件

Country Status (5)

Country Link
US (1) US6667913B2 (https=)
JP (1) JP2003331577A (https=)
KR (1) KR100869985B1 (https=)
CN (3) CN100538880C (https=)
TW (1) TW578153B (https=)

Families Citing this family (15)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP4271623B2 (ja) * 2004-06-17 2009-06-03 富士通株式会社 クロック調整装置および方法
DE102004044721B4 (de) * 2004-09-15 2013-11-14 Qimonda Ag Selbsttest für die Phasenlage des Datenleseclocksignals DQS
JP4808414B2 (ja) * 2005-01-31 2011-11-02 富士通株式会社 コンピュータシステム及びメモリシステム
CN100550199C (zh) * 2006-09-20 2009-10-14 南亚科技股份有限公司 存储器控制电路与方法
KR100834401B1 (ko) * 2007-01-08 2008-06-04 주식회사 하이닉스반도체 반도체 메모리 소자와 그의 구동 방법
KR101006088B1 (ko) * 2009-06-04 2011-01-06 주식회사 하이닉스반도체 데이터 전달의 신뢰성을 보장하기 위한 반도체 메모리 장치 및 이를 포함하는 반도체 시스템
JP2010282511A (ja) * 2009-06-05 2010-12-16 Elpida Memory Inc メモリモジュール及びこれを備えるメモリシステム
CN102280129B (zh) * 2010-06-09 2014-12-17 上海华虹宏力半导体制造有限公司 闪速存储器及其读取电路
JP2012043510A (ja) 2010-08-20 2012-03-01 Elpida Memory Inc 半導体装置およびその制御方法
JP6596051B2 (ja) * 2016-10-28 2019-10-23 インテグレイテッド シリコン ソリューション インコーポレイテッド 同期半導体集積回路内のクロック式指令タイミング調節
JP7195913B2 (ja) 2018-12-19 2022-12-26 キオクシア株式会社 半導体記憶装置
KR102754270B1 (ko) * 2019-03-05 2025-01-14 에스케이하이닉스 주식회사 반도체장치
KR102849290B1 (ko) * 2020-08-21 2025-08-25 삼성전자주식회사 반도체 장치 및 메모리 시스템
CN114489233B (zh) * 2022-01-24 2024-06-11 上海华力集成电路制造有限公司 一种相位可调任意波形发生器
CN114938258B (zh) * 2022-07-25 2022-10-14 星河动力(北京)空间科技有限公司 火箭控制时钟同步装置、飞行控制器和箭上控制计算机

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN1195864A (zh) * 1997-01-28 1998-10-14 日本电气株式会社 有同步型信号输入电路的半导体存储器

Family Cites Families (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5062081A (en) * 1989-10-10 1991-10-29 Advanced Micro Devices, Inc. Multiport memory collision/detection circuitry
JP3631277B2 (ja) * 1995-01-27 2005-03-23 株式会社日立製作所 メモリモジュール
KR100290007B1 (ko) * 1998-07-23 2001-05-15 김철근 미꾸라지성장호르몬발현벡터
JP4117977B2 (ja) * 1999-06-25 2008-07-16 富士通株式会社 半導体装置
JP2001195149A (ja) * 2000-01-17 2001-07-19 Mitsubishi Electric Corp 内部クロック信号発生回路

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN1195864A (zh) * 1997-01-28 1998-10-14 日本电气株式会社 有同步型信号输入电路的半导体存储器

Also Published As

Publication number Publication date
CN1674150A (zh) 2005-09-28
CN1674149A (zh) 2005-09-28
TW578153B (en) 2004-03-01
US6667913B2 (en) 2003-12-23
TW200306574A (en) 2003-11-16
US20030210577A1 (en) 2003-11-13
CN100511472C (zh) 2009-07-08
KR20030087902A (ko) 2003-11-15
JP2003331577A (ja) 2003-11-21
KR100869985B1 (ko) 2008-11-21
CN1457100A (zh) 2003-11-19
CN1212666C (zh) 2005-07-27

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Date Code Title Description
C06 Publication
PB01 Publication
C10 Entry into substantive examination
SE01 Entry into force of request for substantive examination
C41 Transfer of patent application or patent right or utility model
TA01 Transfer of patent application right

Effective date of registration: 20081212

Address after: Tokyo, Japan

Applicant after: Fujitsu Microelectronics Ltd.

Address before: Kanagawa, Japan

Applicant before: Fujitsu Ltd.

ASS Succession or assignment of patent right

Owner name: FUJITSU MICROELECTRONICS CO., LTD.

Free format text: FORMER OWNER: FUJITSU LIMITED

Effective date: 20081212

C14 Grant of patent or utility model
GR01 Patent grant
C56 Change in the name or address of the patentee

Owner name: FUJITSU SEMICONDUCTOR CO., LTD.

Free format text: FORMER NAME: FUJITSU MICROELECTRON CO., LTD.

CP01 Change in the name or title of a patent holder

Address after: Kanagawa

Patentee after: FUJITSU MICROELECTRONICS Ltd.

Address before: Kanagawa

Patentee before: Fujitsu Microelectronics Ltd.

CP02 Change in the address of a patent holder

Address after: Kanagawa

Patentee after: Fujitsu Microelectronics Ltd.

Address before: Tokyo, Japan

Patentee before: Fujitsu Microelectronics Ltd.

ASS Succession or assignment of patent right

Owner name: SUOSI FUTURE CO., LTD.

Free format text: FORMER OWNER: FUJITSU SEMICONDUCTOR CO., LTD.

Effective date: 20150520

C41 Transfer of patent application or patent right or utility model
TR01 Transfer of patent right

Effective date of registration: 20150520

Address after: Kanagawa

Patentee after: SOCIONEXT Inc.

Address before: Kanagawa

Patentee before: FUJITSU MICROELECTRONICS Ltd.

CF01 Termination of patent right due to non-payment of annual fee
CF01 Termination of patent right due to non-payment of annual fee

Granted publication date: 20090909

Termination date: 20201129