CN100524824C - 高压半导体器件及其制造方法 - Google Patents

高压半导体器件及其制造方法 Download PDF

Info

Publication number
CN100524824C
CN100524824C CNB2006101646882A CN200610164688A CN100524824C CN 100524824 C CN100524824 C CN 100524824C CN B2006101646882 A CNB2006101646882 A CN B2006101646882A CN 200610164688 A CN200610164688 A CN 200610164688A CN 100524824 C CN100524824 C CN 100524824C
Authority
CN
China
Prior art keywords
region
type
drift region
area
field plate
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
CNB2006101646882A
Other languages
English (en)
Other versions
CN1983635A (zh
Inventor
高光永
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
DB HiTek Co Ltd
Original Assignee
Dongbu Electronics Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Dongbu Electronics Co Ltd filed Critical Dongbu Electronics Co Ltd
Publication of CN1983635A publication Critical patent/CN1983635A/zh
Application granted granted Critical
Publication of CN100524824C publication Critical patent/CN100524824C/zh
Expired - Fee Related legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Images

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/08—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
    • H01L29/0843—Source or drain regions of field-effect devices
    • H01L29/0847—Source or drain regions of field-effect devices of field-effect transistors with insulated gate
    • H01L29/0852—Source or drain regions of field-effect devices of field-effect transistors with insulated gate of DMOS transistors
    • H01L29/0856—Source regions
    • H01L29/0865—Disposition
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/7833—Field effect transistors with field effect produced by an insulated gate with lightly doped drain or source extension, e.g. LDD MOSFET's; DDD MOSFET's
    • H01L29/7835—Field effect transistors with field effect produced by an insulated gate with lightly doped drain or source extension, e.g. LDD MOSFET's; DDD MOSFET's with asymmetrical source and drain regions, e.g. lateral high-voltage MISFETs with drain offset region, extended drain MISFETs
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0657—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape of the body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
    • H01L29/42312—Gate electrodes for field effect devices
    • H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
    • H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
    • H01L29/42356—Disposition, e.g. buried gate electrode
    • H01L29/4236—Disposition, e.g. buried gate electrode within a trench, e.g. trench gate electrode, groove gate electrode
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66568—Lateral single gate silicon transistors
    • H01L29/66613—Lateral single gate silicon transistors with a gate recessing step, e.g. using local oxidation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66568—Lateral single gate silicon transistors
    • H01L29/66659—Lateral single gate silicon transistors with asymmetry in the channel direction, e.g. lateral high-voltage MISFETs with drain offset region, extended drain MISFETs
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
    • H01L29/42312—Gate electrodes for field effect devices
    • H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
    • H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
    • H01L29/42364—Gate electrodes for field effect devices for field-effect transistors with insulated gate characterised by the insulating layer, e.g. thickness or uniformity
    • H01L29/42368—Gate electrodes for field effect devices for field-effect transistors with insulated gate characterised by the insulating layer, e.g. thickness or uniformity the thickness being non-uniform

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Ceramic Engineering (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Manufacturing & Machinery (AREA)
  • Insulated Gate Type Field-Effect Transistor (AREA)

Abstract

本发明提供一种高压半导体器件，包括：第一导电类型的半导体衬底，包括第一区域、低于所述第一区域的第二区域、和在所述第一区域与所述第二区域之间的倾斜区域；第二导电类型的漂移区，形成于所述第二区域；第二导电类型的源极区域，配置于所述第一区域，并通过所述倾斜区域与所述漂移区相隔；第二导电类型的漏极区域，配置于所述漂移区；场板，位于所述第二区域中的漂移区上；栅极绝缘层，配置于所述源极区域与所述漂移区之间；和栅极层，其配置在所述栅极绝缘层上，并延伸至所述场板上方。

Description

高压半导体器件及其制造方法
技术领域
本发明涉及一种半导体器件及其制造方法，更具体地，涉及一种具有低工作电阻(operation resistance)的高压半导体器件及其制造方法。
背景技术
图1是示出传统高压半导体器件实例的剖视图。
参照图1，n型漂移区110配置在p型半导体衬底100上的预定区域。n+型源极区域121配置在半导体衬底100的表面上，并以预定间隔与n型漂移区110相隔。n+型漏极区域122配置在n型漂移区110上。沟道区域102配置在n型漂移区110与n+型源极区域121之间的半导体衬底100的表面上，并且反型层在预定条件下形成于沟道区域102中。硅的局部氧化(LOCOS)场板(field plate)130配置在沟道区域102与n+型漏极区域122之间的n型漂移区110上。
栅极层150配置于沟道区域102的上方，在所述栅极层150和所述沟道区域102之间插入栅极绝缘层140。栅极层150延伸到n型漂移区110上的场板130的顶表面。多个栅极间隔层160形成于栅极层150的两个侧壁。n+型源极区域121、n+型漏极区域122和栅极层150分别通过它们的互连结构连接至源极端子S、漏极端子D和栅极端子G。
在上述高压半导体器件中，为了保证击穿电压(BV)，需要n型漂移区110，并且沟道的长度要较长。n型漂移区110和长沟道占用了高压半导体器件的大部分表面面积。另外，当采用场板130时，电流经过路径沿场板130的底表面形成于n型漂移区110中，如图1中箭头所示。因此，相对变长的电流路径和增高的半导体器件的导通电阻(Ron)降低了半导体器件的工作性能。
发明内容
根据本发明，提供一种高压半导体器件，其可以通过降低半导体器件的导通电阻来改善半导体器件的工作性能。
根据本发明，还提供一种上述高压半导体器件的制造方法。
根据本发明的优选实施例，提供一种高压半导体器件，包括：第一导电类型的半导体衬底，包括相对高的第一区域、相对低的第二区域、和在所述第一区域与所述第二区域之间的倾斜区域；第二导电类型的漂移区，形成于所述第二区域；第二导电类型的源极区域，配置于所述第一区域，并通过所述倾斜区域与所述漂移区相隔；第二导电类型的漏极区域，配置于所述漂移区上；场板，配置于所述第二区域中的漂移区上；栅极绝缘层，配置于所述源极区域与所述漂移区之间；和栅极层，其配置在所述栅极绝缘层上，并延伸至所述场板的顶表面。
所述第一导电类型可为p型，所述第二导电类型可为n型。
根据本发明的另一优选实施例，提供一种制造高压半导体器件的方法，包括：在第一导电类型的半导体衬底的预定区域上形成第二导电类型的漂移区；在与所述漂移区接触的半导体衬底的表面上形成硅的局部氧化(LOCOS)场板，所述LOCOS场板的两侧是倾斜的；通过对所述场板进行图案化而暴露出在场板一侧的倾斜部分的半导体衬底；通过插入栅极绝缘层来形成栅极导电层图案，其中以使栅极绝缘层与通过对场板进行图案化而暴露出的半导体衬底一侧的倾斜部分相叠置的方式来插入所述栅极绝缘层；和形成分别配置在半导体衬底和漂移区中的源极/漏极区域。
优选地，所述栅极导电层图案可形成为延伸至所述场板的顶表面。
所述第一导电类型可为p型，所述第二导电类型可为n型。
附图说明
根据结合附图所给出的优选实施例的以下描述，本发明的特征将变得清楚，其中：
图1是示出传统高压半导体器件的实例的剖视图；
图2是示出根据本发明实施例的高压半导体器件的剖视图；及
图3至图5以结构剖视图示出根据本发明实施例的高压半导体器件的制造方法。
具体实施方式
以下，将参照附图详细描述根据本发明的实施例，以使这些实施例可被所属领域技术人员容易地实施。然而，本发明可以以多种不同形式来具体实施，并且不应被解释为受限于这里所述的实施例。
图2是示出根据本发明实施例的高压半导体器件的剖视图。
参照图2，第一导电类型半导体衬底、即p型半导体衬底200包括：第一区域201、低于第一区域201的第二区域202、和连接第一区域201与第二区域202的第三区域203。第二导电类型漂移区、即n型漂移区210配置在半导体衬底200的第二区域202上方的预定位置。第二导电类型漏极区域、即具有高浓度的n+型漏极区域222配置在漂移区210上的预定位置。场板230配置在半导体衬底200的第二区域202的顶表面上。场板230可由氧化层形成，并包括开口232，以暴露出n+型漏极区域222的接触形成区域。
n+型源极区域221配置在半导体衬底200的第一区域201。在n+型源极区域221与n型漂移区210之间形成连接第一区域201和第二区域202的台阶(step)243。n+型源极区域221配置为相对高于n型漂移区210。倾斜的第三区域203配置在n+型源极区域221与n型漂移区210之间，并变成在预定条件下(即，当施加栅极电压时)形成反型层的沟道区域102。
栅极绝缘层240配置在沟道区域102上，栅极导电层图案250配置在栅极绝缘层240上。栅极绝缘层240可以由氧化层形成，栅极导电层图案250由多晶硅层形成。一部分栅极导电层图案250配置在场板230的顶表面上。多个栅极间隔层260配置在栅极导电层图案250的两个侧壁。栅极间隔层260可以由氮化层形成。n+型源极区域221、n+型漏极区域222和栅极导电层图案250利用金属线分别连接至源极端子S、漏极端子D和栅极端子G。
在根据本发明实施例的高压半导体器件中，n+型源极区域221配置为高于n型漂移区210。沟道区域102在n+型源极区域221与n型漂移区210之间具有倾斜表面(profile)。因此，与图1相比，电流沿水平方向经过场板230下方，而不需绕开场板230。因此，缩短了由图2中箭头所示的电流路径，从而降低了半导体器件的导通电阻。
图3至图5以结构剖视图示出根据本发明实施例的高压半导体器件的制造方法。
参照图3，通过使用预定掩模层图案来执行离子注入工艺，将n型漂移区210形成在p型半导体衬底200上。通过使用抗氧化层(例如氮化层)执行一般的硅的局部氧化(LOCOS)工艺，将LOCOS隔离层(未示出)和LOCOS场板230形成在n型漂移区210上。作为这种工艺的结果，场板230的两侧具有倾斜表面。
参照图4，通过使用掩模层图案(例如光致抗蚀剂层图案)执行蚀刻工艺来去除部分场板230。去除的部分包括：在场板230的一侧具有倾斜表面的一部分；以及待在后续工艺中形成漏极接点的邻近于场板230另一侧的一部分。
参照图5，在衬底200的一部分表面上形成栅极绝缘层240，并且在栅极绝缘层240的整个表面上形成栅极导电层。所述栅极导电层可以由多晶硅层形成。对所述栅极导电层进行图案化，以形成栅极导电层图案250。栅极导电层图案250叠置于由于对场板230图案化而已暴露出的半导体衬底200的倾斜区域上方。对栅极导电层图案250进行图案化，以使其延伸至场板230的顶表面。然后，多个栅极间隔层260形成在栅极导电层图案250的两个侧壁。
随后，通过使用离子注入掩模层图案执行一般的离子注入工艺，来形成n+型源极区域221和n+型漏极区域222，从而制造如图2中所示的高压半导体器件。
如上所述，在高压半导体器件以及高压半导体器件的制造方法中，源极区域被配置为高于漂移区。因此，在水平方向上缩短了栅极长度，而不降低击穿电压，从而减小半导体器件的面积。另外，缩短了电流路径的长度，以减小导通电阻。
尽管参照优选实施例已示出和描述本发明，但所属领域技术人员将理解的是，在不脱离所附权利要求所限定的本发明的精神和范围的情况下，可以进行各种改变和修改。

Claims (6)

1.一种半导体器件，包括：
第一导电类型的半导体衬底，包括第一区域、低于所述第一区域的第二区域、和在所述第一区域与所述第二区域之间的倾斜区域；
第二导电类型的漂移区，形成于所述第二区域中；
第二导电类型的源极区域，形成于所述第一区域中，并通过所述倾斜区域与所述漂移区相隔；
第二导电类型的漏极区域，形成于所述漂移区上；
场板，形成于所述第二区域中的漂移区上；
栅极绝缘层，形成于所述源极区域与所述漂移区之间的半导体衬底上；和
栅极层，其配置在所述栅极绝缘层上，并延伸至所述场板上方。
2.根据权利要求1所述的半导体器件，其中所述第一导电类型为p型，所述第二导电类型为n型。
3.一种制造半导体器件的方法，包括：
在第一导电类型的半导体衬底的预定区域上形成第二导电类型的漂移区；
在与所述漂移区接触的半导体衬底的表面上形成硅的局部氧化场板；
通过对所述场板进行图案化来暴露出半导体衬底的倾斜部分；
在暴露出的半导体衬底的倾斜部分上方形成栅极导电层图案，并且在所述栅极导电层图案与半导体衬底之间形成栅极绝缘层；和
分别在所述半导体衬底和漂移区上形成源极区域和漏极区域。
4.根据权利要求3所述的方法，其中所述栅极导电层图案形成为延伸至所述场板上方。
5.根据权利要求3所述的方法，其中所述第一导电类型为p型，所述第二导电类型为n型。
6.根据权利要求3所述的方法，其中所述硅的局部氧化场板的两侧都是倾斜的。
CNB2006101646882A 2005-12-14 2006-12-14 高压半导体器件及其制造方法 Expired - Fee Related CN100524824C (zh)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
KR1020050123358A KR100649867B1 (ko) 2005-12-14 2005-12-14 고전압 반도체소자 및 그 제조방법
KR1020050123358 2005-12-14

Publications (2)

Publication Number Publication Date
CN1983635A CN1983635A (zh) 2007-06-20
CN100524824C true CN100524824C (zh) 2009-08-05

Family

ID=37713575

Family Applications (1)

Application Number Title Priority Date Filing Date
CNB2006101646882A Expired - Fee Related CN100524824C (zh) 2005-12-14 2006-12-14 高压半导体器件及其制造方法

Country Status (3)

Country Link
US (1) US7573100B2 (zh)
KR (1) KR100649867B1 (zh)
CN (1) CN100524824C (zh)

Families Citing this family (15)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100947941B1 (ko) 2007-12-27 2010-03-15 주식회사 동부하이텍 반도체 소자 및 그 제조방법
JP2010157582A (ja) * 2008-12-26 2010-07-15 Rohm Co Ltd 半導体装置
EP2306508B1 (en) * 2009-09-29 2012-11-28 STMicroelectronics Srl Integrated device with raised LOCOS insulation regions and process for manufacturing such device
EP2306509A1 (en) * 2009-09-29 2011-04-06 STMicroelectronics Srl Process for manufacturing an integrated device with "damascene" field insulation, and integrated device made by such process
US8878295B2 (en) * 2011-04-13 2014-11-04 National Semiconductor Corporation DMOS transistor with a slanted super junction drift structure
CN102214583A (zh) * 2011-05-26 2011-10-12 上海先进半导体制造股份有限公司 深槽高压终端结构的制作方法以及高压半导体器件
CN102214581A (zh) * 2011-05-26 2011-10-12 上海先进半导体制造股份有限公司 用于深槽超结mos器件的终端结构的制作方法
US8530978B1 (en) * 2011-12-06 2013-09-10 Hrl Laboratories, Llc High current high voltage GaN field effect transistors and method of fabricating same
CN103606515B (zh) * 2013-11-14 2016-03-16 中国科学院微电子研究所 一种宽禁带功率器件场板的制造方法
US9318366B2 (en) * 2014-01-06 2016-04-19 Taiwan Semiconductor Manufacturing Company, Ltd. Method of forming integrated circuit having modified isolation structure
US10276712B2 (en) 2014-05-29 2019-04-30 Hrl Laboratories, Llc III-nitride field-effect transistor with dual gates
US9812532B1 (en) 2015-08-28 2017-11-07 Hrl Laboratories, Llc III-nitride P-channel transistor
CN108292678B (zh) 2015-11-19 2021-07-06 Hrl实验室有限责任公司 具有双栅极的iii族氮化物场效应晶体管
DE102017130213B4 (de) * 2017-12-15 2021-10-21 Infineon Technologies Ag Planarer feldeffekttransistor
CN113314405B (zh) * 2021-05-26 2022-07-26 四川上特科技有限公司 半导体功率器件斜坡场板的制作方法

Family Cites Families (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6232636B1 (en) * 1998-11-25 2001-05-15 Philips Electronics North America Corporation Lateral thin-film silicon-on-insulator (SOI) device having multiple doping profile slopes in the drift region
JP4590884B2 (ja) * 2003-06-13 2010-12-01 株式会社デンソー 半導体装置およびその製造方法
DE10345347A1 (de) * 2003-09-19 2005-04-14 Atmel Germany Gmbh Verfahren zur Herstellung eines DMOS-Transistors mit lateralem Driftregionen-Dotierstoffprofil
US7187033B2 (en) * 2004-07-14 2007-03-06 Texas Instruments Incorporated Drain-extended MOS transistors with diode clamp and methods for making the same
US7224025B2 (en) * 2004-08-03 2007-05-29 Taiwan Semiconductor Manufacturing Co., Ltd. Isolated LDMOS IC technology
KR100632684B1 (ko) * 2004-12-31 2006-10-12 동부일렉트로닉스 주식회사 반도체 소자의 로코스 제조 방법

Also Published As

Publication number Publication date
CN1983635A (zh) 2007-06-20
US7573100B2 (en) 2009-08-11
KR100649867B1 (ko) 2006-11-27
US20070138551A1 (en) 2007-06-21

Similar Documents

Publication Publication Date Title
CN100524824C (zh) 高压半导体器件及其制造方法
US7541642B2 (en) Semiconductor device with a gate electrode including a pair of polysilicon layers
TWI647843B (zh) 半導體裝置
US7800185B2 (en) Closed trench MOSFET with floating trench rings as termination
US8021947B2 (en) Method of forming an insulated gate field effect transistor device having a shield electrode structure
WO2014163058A1 (ja) 半導体装置
US8803234B1 (en) High voltage semiconductor device and method for fabricating the same
JP2009043966A (ja) 半導体装置及びその製造方法
JP2004297086A (ja) 高スイッチングスピードのための横方向パワーｍｏｓｆｅｔ
US11742420B2 (en) Semiconductor device and structure therefor
KR100289049B1 (ko) 이중필드판구조를갖는전력소자
US6486512B2 (en) Power semiconductor device having high breakdown voltage and method for fabricating the same
JP2800884B2 (ja) 横型ｄｓａパワーｍｏｓｆｅｔを備えた半導体装置
WO2013161568A1 (ja) 半導体装置及びその製造方法
KR20060051408A (ko) 낮은 용량 반도체 장치 및 이의 구조를 형성하는 방법
JP6490679B2 (ja) 複数の注入層をもつ高電圧電界効果トランジスタ
US20210159327A1 (en) Semiconductor devices
KR20070084612A (ko) 전계 효과 트랜지스터 및 그 제조 방법
JP2019012803A (ja) 半導体装置
KR20150142220A (ko) 전력 반도체 소자
US20110269285A1 (en) Field transistors for electrostatic discharge protection and methods for fabricating the same
EP1429391A1 (en) Insulated gate semiconductor device and method of making the same
JP2023069620A (ja) 半導体装置
CN113097298A (zh) 一种绝缘栅双极型晶体管及其制备方法
CN110581069A (zh) 制造高压半导体器件的方法

Legal Events

Date Code Title Description
C06 Publication
PB01 Publication
C10 Entry into substantive examination
SE01 Entry into force of request for substantive examination
C14 Grant of patent or utility model
GR01 Patent grant
C17 Cessation of patent right
CF01 Termination of patent right due to non-payment of annual fee

Granted publication date: 20090805

Termination date: 20131214