CN100524722C - 无外引脚导线架的封装结构 - Google Patents

无外引脚导线架的封装结构 Download PDF

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CN100524722C
CN100524722C CNB2006100636525A CN200610063652A CN100524722C CN 100524722 C CN100524722 C CN 100524722C CN B2006100636525 A CNB2006100636525 A CN B2006100636525A CN 200610063652 A CN200610063652 A CN 200610063652A CN 100524722 C CN100524722 C CN 100524722C
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周昶旭
陈淑茵
陈子康
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Advanced Semiconductor Engineering Inc
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L24/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L24/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/3201—Structure
    • H01L2224/32012—Structure relative to the bonding area, e.g. bond pad
    • H01L2224/32014—Structure relative to the bonding area, e.g. bond pad the layer connector being smaller than the bonding area, e.g. bond pad
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32245—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73265—Layer and wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation

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Abstract

本发明一种无外引脚导线架的封装结构。该封装结构包括一个无外引脚的导线架、一个芯片及一个封装材料。该无外引脚导线架包括一个框架及一个芯片承座。该框架具有若干个导接部，该等导接部的内侧部分具有一个第一凹陷部。该芯片承座具有一个第二凹陷部，该第二凹陷部形成于该芯片承座的周边。在该芯片设置于该芯片承座时，本发明的该第二凹陷部可抑制树脂溢流而造成污染及造成不平整面的问题。再者，本发明的封装结构不需利用垫高片设置于芯片与芯片承座之间，因此，更可减少封装步骤及生产成本。

Description

无外引脚导线架的封装结构
技术领域
本发明是关于一种封装结构，特别是关于一种无外引脚的导线架的封装结构。
背景技术
参考图1，其显示现有无外引脚的封装结构。该封装结构1包括一个无外引脚导线架10、一个芯片11、一个垫高片12、若干条导线13及一个封装材料14。该无外引脚导线架10包括一个框架101及一个芯片承座102。该框架101具有一个第一表面103及若干个导接部104。该芯片承座102设置于该框架101中，该芯片承座102具有一个置晶面105，该置晶面105与该框架101的该第一表面103位于同一平面。该垫高片12利用树脂设置于该芯片11与芯片承座102之间。该等导线13是用以电线连接该芯片11及该等导接部104。该封装材料14用以封装该无外引脚导线架10、该等导线13及该芯片11。
在该现有的封装结构1中，由于该芯片11的尺寸大于该芯片承座102，故必须利用该垫高片12以避免该芯片11与该等导接部104接触。该垫高片12是利用树脂设置于该芯片11与芯片承座102之间，但该芯片承座102没有可抑制树脂溢流的结构，故该树脂会溢流至该芯片承座102的侧边及底面，而造成污染及不平整面的问题。再者，该现有的封装结构1必须利用该垫高片12设置于该芯片11与芯片承座102之间，因此，更增加了封装步骤及生产成本。
因此，有必要提供一种新的无外引脚导线架的封装结构，以解决上述问题。
发明内容
本发明的目的在于提供一种封装结构中不会出现污染芯片和不平整平面情况的无外引脚导线架。
为达成前述目的，本发明一种无外引脚导线架，其包括一个框架及一个芯片承座。该框架具有第一表面及若干个导接部，该等导接部的内侧部分具有第一凹陷部。该芯片承座设置于该框架中，该芯片承座具有一个置晶面及一个第二凹陷部，该置晶面与该框架的该第一表面位于同一平面，该第二凹陷部形成于该置晶面及该芯片承座的侧边之间。
本发明的该芯片承座具有第二凹陷部，因此，在该芯片利用树脂贴设于该置晶面时，可使溢流的树脂仅停留在该第二凹陷部，不会溢流至该芯片承座的侧边或底部，故可以解决现有技术的污染及不平整面的问题。由于该等导接部具有该第一凹陷部，该芯片的边缘可延伸至该第一凹陷部的上方相对位置，故可应用于封装较大尺寸的芯片。再者，本发明的封装结构不需要现有技术的垫高片，因此，更可减少封装步骤及生产成本。
附图说明
图1显示现有的无外引脚的封装结构示意图。
图2显示本发明无外引脚导线架的第一实施例示意图。
图3显示本发明无外引脚导线架的第二实施例示意图。
图4显示本发明无外引脚的封装结构的第一实施例示意图。
图5显示本发明无外引脚的封装结构的第二实施例示意图。
具体实施方式
参考图2，其显示本发明的无外引脚导线架的第一实施例示意图。该第一实施例的无外引脚导线架2包括一个框架20及一个芯片承座21。该框架20具有第一表面201及若干个导接部202。该等导接部202的内侧部分具有一个第一凹陷部203，该第一凹陷部203为一个弧角。在该实施例中，该导线架2为四边扁平无接脚的导线架，在其它应用中，该导线架2也可为二边扁平无接脚的导线架。
该芯片承座21设置于该框架20中，该芯片承座21具有一个置晶面211及一个第二凹陷部212，该第二凹陷部212为一个弧角。该置晶面211与该框架20的该第一表面201位于同一平面，该第二凹陷部212形成于该芯片承座21周缘。在该实施例中，该第一凹陷部203及该第二凹陷部212是由蚀刻方式所形成，使该等导接部202及该芯片承座21为上窄下宽的形状。较佳地，该第二凹陷部212是形成于该置晶面211的周缘。参考图3，其显示本发明的无外引脚导线架的第二实施例示意图。该第二实施例的无外引脚导线架3包括一个框架30及一个芯片承座31。该第二实施例的无外引脚导线架3与上述图2的该第一实施例的无外引脚导线架2，不同之处在于该第二实施例中，该导接部302包括若干个内导接部304及若干个外导接部305，该等内导接部304及该等外导接部305相隔一段设定的距离d，该内导接部304的内侧部分具有一个第一凹陷部303。
参考图4，其显示本发明无外引脚的封装结构的第一实施例。该封装结构4包括一个如上述图2的该第一实施例的无外引脚导线架2、一个芯片41、若干条导线42及封装材料43。该芯片41与该芯片承座21之间设有一层胶层44(如树脂等材料)，该芯片41是利用该胶层44设置于该置晶面211，且该胶层44覆盖部分该芯片承座21的第二凹陷部212。该芯片41的边缘位于相对于该第一凹陷部203的上方且不与该等导接部202接触。该芯片41利用该等导线42分别电性连接至该等导接部202。接着，再利用该封装材料43用以封装该无外引脚导线架2、该芯片41及该等导线42。该封装结构4可应用于四边扁平无接脚封装(Quad FlatNon-lead，QFN)及双扁平无接脚封装(Dual Flat Non-lead，DFN)领域中。
本发明的该芯片承座21具有第二凹陷部212，因此，在该芯片41利用树脂贴设于该置晶面211时，可使溢流的树脂仅停留在该第二凹陷部212，不会溢流至该芯片承座21的侧边或底部，故可以解决现有技术的污染及不平整面的问题。由于该等导接部202具有第一凹陷部203，该芯片41的边缘可延伸至该第一凹陷部203的上方相对位置，故可应用于封装较大尺寸的芯片。再者，本发明的封装结构4不需要现有技术的垫高片，因此，更可减少封装步骤及生产成本。
参考图5，其显示本发明的无外引脚之封装结构的第二实施例。该封装结构包括一个如上述图3的该第二实施例的无外引脚导线架3、一个芯片51、若干条导线52、53及封装材料54。该芯片51与该芯片承座31之间设有一层胶层55(如树脂等材料)，该芯片51是利用该胶层55设置于该置晶面311，且该胶层55覆盖部分该芯片承座31的第二凹陷部312。该芯片51的边缘位于相对于该第一凹陷部303的上方且不与该等内导接部304接触。
该芯片51是利用该等导线52、53分别电性连接至该等内导接部304及该等外导接部305。接着，再利用该封装材料54用以封装该无外引脚导线架50、该芯片51及该等导线52、53。该封装结构5可应用于四边扁平无接脚封装或双扁平无接脚封装领域中。该封装结构5除具有上述封装结构4的功效外，因具有该等内导接部304及该等外导接部305，可以增加与外界连接的接点。

Claims (11)

1、一种无外引脚导线架，其包括一框架和一芯片承座，所述框架具有一第一表面及若干个导接部，所述芯片承座具有一置晶面，所述置晶面与所述框架的第一表面位于同一平面；其特征在于：所述导接部的内侧部分具有第一凹陷部；所述芯片承座具有形成于所述芯片承座周缘的第二凹陷部。
2、如权利要求1所述的无外引脚导线架，其特征在于：所述导线架为四边扁平无接脚的导线架。
3、如权利要求1所述的无外引脚导线架，其特征在于：所述第一凹陷部为一个弧角。
4、如权利要求1所述的无外引脚导线架，其特征在于：所述第二凹陷部为一个弧角。
5、如权利要求1所述的无外引脚导线架，其特征在于：所述第一凹陷部及所述第二凹陷部是以蚀刻方式形成。
6、如权利要求1所述的无外引脚导线架，其特征在于：所述第二凹陷部是形成于所述置晶面的周缘。
7、如权利要求1所述的无外引脚导线架，其特征在于：所述芯片承座的置晶面上另设有一芯片，所述芯片的边缘位于相对于所述第一凹陷部的上方且不接触所述导接部。
8、如权利要求1所述的无外引脚导线架，其特征在于：所述芯片承座的置晶面上另设有一芯片，在所述芯片与所述芯片承座之间设有一层胶层。
9、如权利要求8所述的无外引脚导线架，其特征在于：所述胶层覆盖部分所述芯片承座的第二凹陷部。
10、如权利要求1所述的无外引脚导线架，其特征在于：所述导接部包括若干个内导接部及若干个外导接部，所述内导接部及所述外导接部相隔一段设定距离，所述第一凹陷部形成于所述内导接部的内侧部分。
11、如权利要求1所述的无外引脚导线架，其中所述芯片承座的置晶面上另设有一芯片，所述芯片是利用若干条导线分别电性连接至所述导接部。
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CN101964335B (zh) * 2009-07-23 2013-04-24 日月光半导体制造股份有限公司 封装件及其制造方法
CN107256851B (zh) * 2011-07-18 2020-04-24 日月光半导体制造股份有限公司 半导体封装结构
CN102315191A (zh) * 2011-09-13 2012-01-11 江苏长电科技股份有限公司 新型有基岛预填塑封料引线框结构
CN104064533A (zh) * 2014-07-03 2014-09-24 江苏东光微电子股份有限公司 一种双面半导体器件的qfn封装结构及方法

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