CN102931150B - 无外引脚封装结构 - Google Patents
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
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- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32245—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
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- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
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- H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
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- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
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- H—ELECTRICITY
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/73—Means for bonding being of different types provided for in two or more of groups H01L24/10, H01L24/18, H01L24/26, H01L24/34, H01L24/42, H01L24/50, H01L24/63, H01L24/71
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/181—Encapsulation
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Abstract
一种无外引脚封装结构,包括导线架、芯片以及封装胶体。导线架包括芯片座以及多个引脚。芯片座具有顶面与底面,且芯片座包括芯片接合部与周缘部。周缘部连接且围绕芯片接合部。芯片座的顶面于芯片接合部之外凹陷而形成周缘部。引脚配置于芯片座周围且与芯片座电性分离。各引脚具有上表面与下表面,且各引脚包括悬臂部与外接部。各引脚的下表面于外接部之外凹陷而形成悬臂部。悬臂部自外接部延伸至周缘部之上而与周缘部局部重迭。芯片配置于芯片接合部上,且经由多条焊线电性连接至悬臂部。封装胶体覆盖芯片、焊线与导线架。
Description
技术领域
本发明是有关于一种芯片封装结构,且特别是有关于一种无外引脚封装结构。
背景技术
半导体封装技术包含许多封装形态,随着芯片封装结构小型化以及薄化的趋势,发展出属于扁平封装系列的四方扁平无外引脚(quad flat no-lead,QFN)封装。四方扁平无引脚封装因无向外延伸的引脚,尺寸可大幅缩减,并且具有较短的讯号传递路径及相对较快的讯号传递速度。因此,四方扁平无引脚封装非常适用于中、低脚数的高速及高频产品,并已成为此类型的封装型态的主流之一。
在四方扁平无引脚封装结构中,芯片座(die pad)与引脚(lead)之间具有一间隙,以藉此使二者电性分离。此外,芯片装设于芯片座上,并藉由焊线(bonding wire)而与引脚电性连接。随着技术提升以及组件尺寸微型化的趋势,芯片的尺寸逐渐缩小。然而,当芯片的尺寸缩小时,芯片的焊垫与引脚间的距离相对地增加,连接芯片与引脚的焊线长度也因此增长。如此一来,可能造成组件的传输信号衰减、电性效能降低、生产成本提高,长焊线也可能在封胶时产生线塌(collapse)或线偏移(wiresweep)的状况。若对应芯片尺寸缩小而缩减芯片座尺寸以及变更引脚长度设计,因芯片座尺寸缩小,封装结构与外界的接触面积亦缩小,芯片运作时产生的热透过芯片座传导消散的效果亦会减弱。再者,变更芯片座与引脚的设计,可能造成引脚悬空部分过长而有晃动变形的疑虑,或者后续工艺中的外部组件(例如印刷电路板)也须相应的变更设计,而造成成本增加。
发明内容
本发明提供一种无外引脚封装结构,其具有较短的焊线长度。
本发明提出一种无外引脚封装结构,包括导线架、芯片以及封装胶体。导线架包括芯片座以及多个引脚。芯片座具有顶面与底面,且芯片座包括芯片接合部与周缘部。周缘部连接且围绕芯片接合部。芯片座的顶面于芯片接合部之外凹陷而形成周缘部。引脚配置于芯片座周围且与芯片座电性分离。各引脚具有上表面与下表面,且各引脚包括悬臂部与外接部。各引脚的下表面于外接部之外凹陷而形成悬臂部。悬臂部自外接部延伸至周缘部之上而与周缘部局部重迭。芯片配置于芯片接合部上,且经由多条焊线电性连接至悬臂部。封装胶体覆盖芯片、焊线与导线架。
依照本发明实施例所述的无外引脚封装结构,还包括绝缘层,其配置于周缘部上,且至少填充于悬臂部与周缘部重迭的间隙中。
依照本发明实施例所述的无外引脚封装结构,上述的各悬臂部与芯片接合部之间的水平距离例如小于周缘部的宽度。
依照本发明实施例所述的无外引脚封装结构,上述的引脚的上表面与芯片接合部的顶面例如为共平面。
依照本发明实施例所述的无外引脚封装结构,上述的封装胶体暴露出外接部的下表面。
依照本发明实施例所述的无外引脚封装结构,上述的封装胶体还暴露出芯片座的底面。
依照本发明实施例所述的无外引脚封装结构,还包括配置于芯片与芯片接合部之间的黏着层。
依照本发明实施例所述的无外引脚封装结构,上述的悬臂部与周缘部重迭的间隙中填充有封装胶体。
基于上述,在本发明的无外引脚封装结构中,引脚的悬臂部与芯片座的周缘部局部重迭,使得引脚与芯片座之间的距离随之缩短。因此,连接芯片与引脚的焊线的长度可藉此缩短,以避免因焊线长度过长而导致电性效能降低,且可达到降低生产成本的目的。此外,本发明在不改变芯片座尺寸的前提下缩短焊线的长度,因此芯片座的底面可以维持所需的面积,以保持所需的散热效果。
为让本发明的上述特征和优点能更明显易懂,下文特举实施例,并配合所附附图作详细说明如下。
附图说明
图1为依照本发明一实施例所绘示的无外引脚封装结构的剖面示意图。
图2为图1中无外引脚封装结构的上视示意图。
图3为依照本发明另一实施例所绘示的无外引脚封装结构的剖面示意图。
具体实施方式
图1为依照本发明一实施例所绘示的无外引脚封装结构的剖面示意图。图2为图1中无外引脚封装结构的上视示意图。在图2中,引脚的的数量仅用于示意,并非用以限定本发明。请参照图1与图2,本实施例的无外引脚封装结构10包括导线架100、芯片102以及封装胶体104。导线架100包括芯片座106以及多个引脚108。芯片座106具有顶面106a与底面106b。此外,芯片座106包括芯片接合部110与周缘部112。周缘部112连接且围绕芯片接合部110。芯片接合部110用以供芯片102设置于其上。
在本实施例中,芯片座106的顶面106a于芯片接合部110之外的区域凹陷而形成周缘部112。因此,在芯片座106中,芯片接合部110的厚度大于周缘部112的厚度。也就是说,在本实施例中,芯片座106呈倒T形。
引脚108配置于芯片座106的周围,且与芯片座106电性分离。每一个引脚108具有上表面108a与下表面108b。此外,每一个引脚108包括悬臂部114与外接部116。悬臂部114用以供焊线接合,而外接部116则用以供无外引脚封装结构10与外部组件(例如印刷电路板)电性连接。在本实施例中,每一个引脚108的下表面108b于外接部116之外的区域凹陷而形成悬臂部114。因此,在每一个引脚108中,外接部116的厚度大于悬臂部114的厚度。另外,悬臂部114自外接部116延伸至芯片座106的周缘部112上方而与周缘部112局部重迭,使得悬臂部114的端部与芯片接合部110之间的水平距离小于周缘部112的宽度。由于悬臂部114延伸进入芯片座106的范围内而与周缘部112局部重迭,因此缩短了引脚108与芯片102之间的距离。
在本实施例中,引脚108的上表面108a与芯片座106的顶面106a为共平面,也就是悬臂部114的上表面、外接部116的上表面以及芯片接合部110的顶面为共平面。此外,引脚108的下表面108b与芯片座106的底面106b为共平面,也就是外接部116的下表面、芯片接合部110的底面以及周缘部112的底面为共平面。
芯片102配置于芯片接合部110上,且经由多条焊线118电性连接至悬臂部114。此外,在芯片102与芯片接合部110之间另外配置有黏着层120,以使芯片102稳固地设置于芯片接合部110上。
封装胶体104覆盖芯片102、焊线118与导线架110。封装胶体104暴露出外接部116的下表面,使得无外引脚封装结构10可经由外接部116而电性连接至外部组件(例如:表面黏着至印刷电路板)。此外,封装胶体104亦暴露出芯片座106的底面106b(即芯片接合部110与周缘部112的底面),使无外引脚封装结构10可透过暴露的芯片座106的底面106b进行散热。另外,封装胶体104亦会填充于悬臂部114与周缘部112重迭的间隙中,以隔绝引脚108的悬臂部114与芯片座106的周缘部112。
此外,在另一实施例中,还可以于悬臂部与周缘部重迭的间隙中配置绝缘层。
图3为依照本发明另一实施例所绘示的无外引脚封装结构的剖面示意图。请参照图3,无外引脚封装结构30与无外引脚封装结构10的差异在于:在无外引脚封装结构30中,芯片座106的周缘部112上配置有绝缘层300,且绝缘层300填充于悬臂部114与周缘部112重迭的间隙中,以确保悬臂部114与周缘部112电性分离,绝缘层300并可支撑悬臂部114,使悬臂部114不致因打线工艺或封模工艺而弯折变形或偏移。当然,在其它实施例中,绝缘层300可完全覆盖周缘部112。
综上所述,在本发明的无外引脚封装结构中,由于引脚的悬臂部延伸进入芯片座的范围内而与芯片座的周缘部局部重迭,因此可以缩短引脚与芯片之间的距离,使得用以连接芯片与引脚的焊线的长度能够缩短,进而避免因焊线的长度过长而导致电性效能降低的问题,且可降低生产成本。
此外,本发明在不改变芯片座尺寸的前提下缩短焊线的长度,因此芯片座的底面可以维持所需的面积,以保持所需的散热效果。
虽然本发明已以实施例揭露如上,然其并非用以限定本发明,任何所属技术领域中具有通常知识者,在不脱离本发明的精神和范围内,当可作些许的更动与润饰,故本发明的保护范围当视后附的权利要求所界定者为准。
Claims (8)
1.一种无外引脚封装结构,包括:
一导线架,包括:
一芯片座,具有一顶面与一底面,且该芯片座包括一芯片接合部与一周缘部,其中该周缘部连接且围绕该芯片接合部,且该顶面于该芯片接合部之外凹陷而形成该周缘部;以及
多个引脚,配置于该芯片座周围且与该芯片座电性分离,各该引脚具有一上表面与一下表面,且各该引脚包括一悬臂部与一外接部,其中该下表面于该外接部之外凹陷而形成该悬臂部,且该悬臂部自该外接部延伸至该周缘部之上而与该周缘部局部重迭;
一芯片,配置于该芯片接合部上,且经由多条焊线电性连接至所述多个悬臂部;以及
一封装胶体,覆盖该芯片、所述多个焊线与该导线架。
2.如权利要求1所述的无外引脚封装结构,其特征在于,还包括一绝缘层,配置于该周缘部上,且至少填充于所述多个悬臂部与该周缘部重迭的间隙中。
3.如权利要求1所述的无外引脚封装结构,其特征在于,各该悬臂部与该芯片接合部之间的水平距离小于该周缘部的宽度。
4.如权利要求1所述的无外引脚封装结构,其特征在于,所述多个引脚的上表面与该芯片接合部的顶面为共平面。
5.如权利要求1所述的无外引脚封装结构,其特征在于,该封装胶体暴露出所述多个外接部的下表面。
6.如权利要求5所述的无外引脚封装结构,其特征在于,该封装胶体还暴露出该芯片座的该底面。
7.如权利要求1所述的无外引脚封装结构,其特征在于,还包括一黏着层,配置于该芯片与该芯片接合部之间。
8.如权利要求1所述的无外引脚封装结构,其特征在于,所述多个悬臂部与该周缘部重迭的间隙中填充有该封装胶体。
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JP2005142284A (ja) * | 2003-11-05 | 2005-06-02 | Renesas Technology Corp | 半導体装置 |
EP1825524A4 (en) * | 2004-12-16 | 2010-06-16 | Seoul Semiconductor Co Ltd | CONNECTION GRID COMPRISING A THERMAL DISSIPATOR SUPPORT RING, METHOD FOR MANUFACTURING LIGHT-EMITTING DIODE HOUSING USING THE SAME, AND LIGHT-EMITTING DIODE HOUSING MADE THEREBY |
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