TWI574359B - 半導體封裝 - Google Patents
半導體封裝 Download PDFInfo
- Publication number
- TWI574359B TWI574359B TW104135554A TW104135554A TWI574359B TW I574359 B TWI574359 B TW I574359B TW 104135554 A TW104135554 A TW 104135554A TW 104135554 A TW104135554 A TW 104135554A TW I574359 B TWI574359 B TW I574359B
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- Taiwan
- Prior art keywords
- pedal
- wafer
- semiconductor package
- power
- pins
- Prior art date
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- 239000004065 semiconductor Substances 0.000 title claims description 76
- 239000000463 material Substances 0.000 claims description 33
- 239000012778 molding material Substances 0.000 claims description 8
- 239000000758 substrate Substances 0.000 description 8
- 238000000034 method Methods 0.000 description 3
- 238000005530 etching Methods 0.000 description 2
- 229910000838 Al alloy Inorganic materials 0.000 description 1
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 1
- 229910052802 copper Inorganic materials 0.000 description 1
- 239000010949 copper Substances 0.000 description 1
- 230000009977 dual effect Effects 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000005538 encapsulation Methods 0.000 description 1
- 238000002955 isolation Methods 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
- 230000000873 masking effect Effects 0.000 description 1
- 229910052751 metal Inorganic materials 0.000 description 1
- 239000002184 metal Substances 0.000 description 1
- 239000007769 metal material Substances 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 238000004806 packaging method and process Methods 0.000 description 1
- 239000011347 resin Substances 0.000 description 1
- 229920005989 resin Polymers 0.000 description 1
- 238000003466 welding Methods 0.000 description 1
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/495—Lead-frames or other flat leads
- H01L23/49503—Lead-frames or other flat leads characterised by the die pad
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- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
- H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
- H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
- H01L23/3121—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation
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- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/495—Lead-frames or other flat leads
- H01L23/49541—Geometry of the lead-frame
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- H01L23/495—Lead-frames or other flat leads
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- H01L23/495—Lead-frames or other flat leads
- H01L23/49541—Geometry of the lead-frame
- H01L23/49558—Insulating layers on lead frames, e.g. bridging members
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- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K1/00—Printed circuits
- H05K1/02—Details
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- Computer Hardware Design (AREA)
- Power Engineering (AREA)
- Geometry (AREA)
- Lead Frames For Integrated Circuits (AREA)
- Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
Description
本發明涉及半導體封裝(semiconductor package),更特別地,涉及一種用於半導體封裝的引線框架(lead frame)設計。
對於半導體晶粒(die)封裝設計,有需要增加用於多功能晶粒的輸入/輸出連接數量。引線框架提供一種用於半導體晶粒封裝的解決方案,在將半導體晶粒裝配到製成品期間具有給該半導體晶粒的機械支撐作用。引線框架通常由金屬板(metal sheet)製成以及通過衝壓工藝(stamping process)或蝕刻工藝(etching process)形成。然而,對於傳統的基於引線框架的半導體封裝,用於半導體晶粒的輸入/輸出連接的引線數量是受限制的。
因此,提供一種新型半導體封裝是可取的。
有鑑於此,本發明的目的之一在於提供一種半導體封裝,以解決上述問題。
本發明提供一種半導體封裝。在一示例實施例中,該半導體封裝包括引線框架,該引線框架構包括晶片踏板、支撐杆、至少兩個電源引腳、電源條和壓模材質。支撐杆與晶片
踏板連接,且從晶片踏板向外方向延伸。至少兩個電源引腳與晶片踏板、支撐杆分離,且具有靠近晶片踏板的第一端和從晶片踏板向外延伸的第二端。電源條與所述至少兩個電源引腳連接,且具有支撐部分。壓模材質用於封裝該引線框架,使該支撐部分暴露出來。
在另一示例實施例中,該半導體封裝包括引線框
架,該引線框架構包括晶片踏板、支撐杆、至少兩個電源引腳和電源條。支撐杆與晶片踏板電氣連接,且從晶片踏板向外方向延伸。至少兩個電源引腳與晶片踏板、支撐杆分離,且具有靠近晶片踏板的第一端和從晶片踏板向外延伸的第二端。電源條與電源引腳連接。電源條包括支撐部分。電源條的支撐部分的厚度大於所述第一端的厚度。
在另一示例實施例中,該半導體封裝包括引線框
架,該引線框架構包括晶片踏板、支撐杆、至少兩個電源引腳和電源條。支撐杆與晶片踏板電氣連接,且從晶片踏板向外方向延伸。至少兩個電源引腳與晶片踏板、支撐杆分離。電源條具有端子部分和支撐部分,端子部分與所述至少兩個電源引腳之一的第一端接觸,支撐部分未與所述至少兩個電源引腳中的任何一個接觸。支撐部分的厚大於端子部分的厚度。
上述半導體封裝可以提高設計的靈活性。
下面的實施例中參照附圖給出了詳細描述。
500‧‧‧半導體封裝
232‧‧‧支撐杆
200‧‧‧引線框架
220、222、224‧‧‧接地引腳
230‧‧‧引腳
234‧‧‧壓模材質
216、218、226‧‧‧電源引腳
216-1‧‧‧電源引腳216的第一端
210a、210b‧‧‧端子部分
302‧‧‧晶片端子
202a‧‧‧晶片貼附面
212‧‧‧支撐部分
208‧‧‧電源條
300‧‧‧半導體晶粒
202‧‧‧晶片踏板
204‧‧‧接地環部分
206‧‧‧連接部分
218-1‧‧‧電源引腳218的第一端
234a‧‧‧壓模材質的頂面
224-2‧‧‧接地引腳224的第二端
225‧‧‧接合區域
225a‧‧‧接合區域225的底面
223‧‧‧接地引腳224的頂面
224-1‧‧‧接地引腳224的第一端
205‧‧‧接地引腳224的第一端224-1的底面
304a、304b‧‧‧焊線
302b‧‧‧接地端子
202b‧‧‧基板貼附面
302a‧‧‧電源端子
202c‧‧‧晶片踏板202的邊緣
214‧‧‧電源條208的頂面
213a‧‧‧支撐部分212的底面
226-1‧‧‧電源引腳226的第一端
234b‧‧‧壓模材質234的底面
228‧‧‧第一端226-1的底面
227‧‧‧電源引腳226的接合區域
227a‧‧‧接合區域227的底面
229‧‧‧電源引腳226的頂面
226-2‧‧‧電源引腳226的第二端
通過閱讀隨後的詳細描述和參考附圖的示例,可以更充分地理解本發明,其中:
第1A圖係根據本發明實施例提供的一種半導體封裝的俯視圖;第1B圖係沿第1A圖的線A-A’的截面圖;第1C圖係根據本發明實施例提供的一種半導體封裝的仰視圖。
以下描述為實施本發明的較佳實施例。該描述用於說明本發明的一般原則,並不應當視為具有限制意義。本發明的範圍應當通過參照所附權利要求書來進行確定。
本發明將參照一些附圖和相對於特定的實施例來進行描述,但本發明並不限於其中,以及,僅受權利要求書的限制。所描述的附圖僅僅是示意圖且是非限制性的。在附圖中,為了說明目的,一些元件的尺寸可能被放大,而並沒有按比例示出。附圖中示出的尺寸和相對尺寸並不對應于本發明在實踐中的實際尺寸。通常而言,“大致上”是指在可接受的誤差範圍內,本領域技術人員能夠在一定誤差範圍內解決所述技術問題,基本達到技術效果。
本實施例提供一種半導體封裝。該半導體封裝的引線框架包括連接至少兩個電源引腳(power lead)的電源條(power bar),以給安裝(mount)在該引線框架上的半導體晶粒提供相同的電壓。該電源條包括與電源引腳接觸的端子部分(terminal portion)和不與電源引腳接觸的支撐部分(supporting portion)。該支撐部分的厚度被設計為大於該端子部分的厚度。因此,具有厚的厚度的支撐部分能夠提高機械
強度以及避免搖擺的(dangling)問題。
第1A圖係根據本發明一些實施例提供的一種半導體封裝500的俯視圖。第1B圖係沿第1A圖的線A-A’的截面圖。第1C圖係根據本發明一些實施例提供的一種半導體封裝500的仰視圖。為了清楚地說明該半導體封裝內部的排列(arrangement),壓模材質(molding material)234的邊界僅用於說明目的,其中,該壓模材質用於封裝(encapsulation)。進一步地,第1B圖所示的焊線(bonding wire)304a和304b在第1A圖中未示出,以清楚地說明俯視圖中半導體封裝內部的排列。
在一些實施例中,半導體封裝500可以包括引線框架封裝,例如,四方扁平無引線封裝(quad-flat-no-leads package,QFN)、高級QFN封裝(advanced QFN,aQFN)、薄型四方扁平封裝(low-profile quad flat package,LQFP)、雙扁平無引線封裝(dual-flat-no-lead package,DFN)、四方扁平封裝(quad-flat package,QFP)或雙列直插式封裝(dual-in-line package,DIP)等等。如第1A圖-第1C圖所示,半導體封裝500包括引線框架200、半導體晶粒(semiconductor die)300和壓模材質234。在一些實施例中,引線框架200包括晶片踏板(die paddle)202、支撐杆(supporting bar)232、引腳(lead)230和電源條208。在一些實施例中,引線框架200是金屬材料形成的,例如,銅及其鋁合金。
如第1A圖-第1C圖所示,晶片踏板202位於引線框架200的中央部位,且與支撐杆232電氣連接。在一些實施
例中,晶片踏板202包括晶片貼附面(die attached surface)202a和與晶片貼附面202a相對的基板貼附面(substrate attached surface)202b。晶片踏板202的晶片貼附面202a用於提供將半導體晶粒300安裝在晶片踏板202上的連接物。晶片踏板202的基板貼附面202b用於提供基板或基底(base,未示出)的連接物(attachment)。
支撐杆232與晶片踏板202連接,以支撐晶片踏板
202。如第1A圖所示,支撐杆232從晶片踏板202的拐角處(corner)向外方向延伸。在一些實施例中,支撐杆232具有接地環部分(ground ring section)204,接地環部分204通過幾個連接部分(connection portion)206與晶片踏板202的拐角處連接。如第1A圖和第1B圖所示,接地環部分204圍繞在相應的晶片踏板202的邊緣,並通過連接部分206與晶片踏板202分離。在一些實施例中,接地環部分204用於電氣連接至半導體晶粒300的接地端子(ground pad)。因此,晶片踏板202能夠作為半導體晶粒300的接地層(ground plane)。
複數個離散的引腳230被設為與晶片踏板202和支
撐杆232分離。引腳230沿著相應的晶片踏板202的邊緣進行佈置。同樣地,引腳230從晶片踏板202向外方向延伸。在一些實施例中,引腳230包括電源引腳(power lead)、接地引腳(ground lead)和信號引腳(signal lead)。例如,如第1A圖所示,引腳230包括至少三個電源引腳216、218和226,以及,設置於這些電源引腳旁邊的至少三個接地引腳220、222和224。電源引腳、接地引腳和信號引腳被設計為分別通過焊
線電氣連接至半導體晶粒300的相應的電源端子(power pad)、接地端子(ground pad)和信號端子(signal pad),如第1A圖的晶片端子(包括電源端子、接地端子和信號端子)302所示。例如,如第1B圖所示,半導體晶粒300的電源端子302a通過焊線304a電氣連接至相應的電源引腳226的頂面(top surface)229。半導體晶粒300的接地端子302b通過焊線304b電氣連接至相應的接地引腳224的頂面223。應當注意的是,引腳230的數量取決於設計要求,本發明並此並不做限制。
如第1A圖和第1B圖所示,應當注意的是,根據
本發明一些實施例,一些接地引腳(例如,接地引腳220、222和224)可以被設計為與接地環部分204接觸。因此,在如第1A圖所示的俯視圖和如第1B圖所示的半導體封裝500的截面圖中,與相應的接地引腳(例如,接地引腳224)直接連接的接地環部分204可以共同形成連續接地(continuous routing)。
該接地環部分所形成的連續接地和該接地引腳可具有為引線框架200的其它信號引腳(未示出)提供接地隔離和射頻(radio-frequency,RF)遮罩的作用。
在如第1A圖和第1B圖所示的一些實施例中,每
個引腳230具有靠近(close to)晶片踏板202的第一端和遠離晶片踏板202以及與該第一端相對的第二端。例如,如第1B圖所示,電源引腳226具有靠近晶片踏板202的第一端226-1和從晶片踏板202向外延伸的第二端226-2。類似地,接地引腳224具有靠近晶片踏板202的第一端224-1和從晶片踏板202
向外延伸的第二端224-2。每個引腳230具有靠近第二端的接合區域(bonding region),以便半導體封裝500可以通過該接合區域安裝在基板(例如,印刷電路板(printed circuit board,PCB))上。例如,如第1B圖所示,電源引腳226具有靠近其第二端226-2的接合區域227。類似地,接地引腳224具有靠近其第二端224-2的接合區域225。應當注意的是,在第1B圖所示的截面圖中,引腳230的接合區域具有比引腳230的第一端的厚度較厚的厚度。例如,電源引腳226的第一端226-1具有厚度T1,電源引腳226的接合區域227具有厚度T2。接地引腳224的第一端224-1具有厚度T1,接地引腳224的接合區域225具有厚度T2。類似地,電源引腳216和218的第一端216-1和218-1具有厚度T1。在一些實施例中,通過用於引線框架製造的半蝕刻(half-etching)工藝,厚度T1被設計為比厚度T2小,以便很好地定義電氣連接至基板的接合區域227。如第1B圖所示,電源引腳226的第一端226-1的底面(bottom surface)228從接合區域227的底面227a凹進。
接地引腳224的第一端224-1的底面205從接合區域225的底面225a凹進。
在如第1A圖-第1C圖所示的一些實施例中,引線
框架200還包括電源條208。電源條208設置於晶片踏板202和引腳230(例如,至少兩個電源引腳)之間。例如,電源條208大體上(Substantially)沿著相應的晶片踏板202的邊緣202c的方向延伸。在一些實施例中,電源條208用於連接至少兩個電源引腳,例如,電源引腳216和218。電源條208可以
給半導體晶粒300的電源端子提供相同的電壓,其中,電源條208電氣連接至引線框架200的電源引腳216和218。因此,電源條208未與任何的接地引腳(例如,接地引腳220、222和224)連接。如第1A圖所示,電源條208具有分別與電源引腳216和218的第一端216-1和218-1接觸的端子部分(terminal portion)210a和210b。因此,電源條208和與其連接的電源引腳216、218可以共同構造連續路由。端子部分210a和210b的厚度可以被設計為與引腳230的第一端的厚度大致上(substantially)相等。例如,端子部分210a和210b的厚度大致上等於電源引腳216和218的第一端216-1和218-1的厚度T1。
在如第1A圖-第1C圖所示的一些實施例中,電源
條208包括放置在端子部分210a和210b之間的支撐部分212,以提高電源條208的機械強度。支撐部分212不與電源引腳216和218中的任何一個接觸(is free from)。在一些實施例中,電源條208的支撐部分212的厚度可以被設計為與引腳230的接合區域的厚度大致上相等。例如,支撐部分212的厚度大致上等於電源引腳226的接合區域227和接地引腳224的接合區域225的厚度T2。此外,支撐部分212的厚度T2被設計為大於電源條208的端子部分210a和210b的厚度T1。
在一些實施例中,支撐部分212的厚度被設計為大於引腳230的第一端的厚度。例如,支撐部分212的厚度T2大於接地引腳224的第一端224-1和電源引腳216、218、226的第一端216-1、218-1、226-1的厚度T1。
在如第1A圖-第1C圖所示的一些實施例中,壓模
材質234封裝(encapsulate)引線框架200、半導體晶粒300和焊線304a、304b。壓模材質234具有頂面234a和與頂面234a相對的底面234b。在一些實施例中,壓模材質234可以由壓模材質(如樹脂)形成。如第1B圖-1C所示,壓模材質234形成,使引腳230的接合區域和電源條208的支撐部分暴露出來。特別地,從壓模材質234暴露出來的該電源條208的支撐部分的表面與引腳230的接合區域共面。更具體地說,壓模材質234覆蓋(wrap)電源條208的頂面214,使支撐部分212的底面從壓模材質234的底面234b暴露出來。壓模材質也覆蓋接地引腳224和電源引腳226的頂面223和229,使接合區域227的底面227a和接合區域225的底面225a從壓模材質234的底面234b暴露出來。在一些實施例中,如圖1C所示的半導體封裝500的仰視圖中,引腳230的接合區域225和227的底面(包括接合區域227的底面227a和接合區域225的底面225a)以及電源條208的支撐部分212的底面213a從壓模材質234的底面234b暴露出來。在一些實施例中,支撐部分212的底面與引腳230的接合區域的底面對齊(align),換句話說,支撐部分212的底面與引腳230的接合區域的底面共面。例如,如第1B圖所示,支撐部分212的底面213a和接合區域227的底面227a、接合區域225的底面225a對齊。
在第1B圖-第1C圖所示的一些實施例中,支撐部
分212可以看作是引線框架200的額外接合區域,該支撐部分212具有從壓模材質234暴露出來的底面213a。因此,用於在
其上安裝半導體封裝500的基板可以具有用於電源端子位置的設計的靈活性。
上述實施例提供了一種用於半導體封裝的引線框
架設計。該引線框架包括連接至少兩根電源引腳的電源條,以給安裝在該引線框架上的半導體晶粒提供相同的電壓。該電源條被設計為具有至少一個支撐部分,該至少一個支撐部分的厚度與電源引腳的接合區域的厚度相差無幾。因此,電源引腳的接合區域的底部和電源條的支撐部分的底部能夠從壓模材質暴露出來。具有厚厚度的該支撐部分能夠提高電源條的機械強度。因此,電源條能夠不與額外的虛擬引腳接觸,以避免搖擺的問題。同樣地,從壓模材質暴露出來的支撐部分可以看作是該引線框架的額外接合區域,以提高用於電源端子位置的設計靈活性。
在不脫離本發明的精神以及範圍內,本發明可以其
它特定格式呈現。所描述的實施例在所有方面僅用於說明的目的而並非用於限制本發明。本發明的保護範圍當視後附的申請專利範圍所界定者為准。所屬領域具有通常知識者皆在不脫離本發明之精神以及範圍內做些許更動與潤飾。
500‧‧‧半導體封裝
232‧‧‧支撐杆
200‧‧‧引線框架
220、222、224‧‧‧接地引腳
230‧‧‧引腳
234‧‧‧壓模材質
216、218、226‧‧‧電源引腳
216-1‧‧‧電源引腳216的第一端
210a、210b‧‧‧端子部分
302‧‧‧晶片端子
202a‧‧‧晶片貼附面
212‧‧‧支撐部分
208‧‧‧電源條
300‧‧‧半導體晶粒
202‧‧‧晶片踏板
204‧‧‧接地環部分
206‧‧‧連接部分
218-1‧‧‧電源引腳218的第一端
Claims (30)
- 一種半導體封裝,包括引線框架和壓模材質,其中,所述引線框架構包括:晶片踏板;支撐杆,與所述晶片踏板連接,且從所述晶片踏板向外方向延伸;至少兩個電源引腳,與所述晶片踏板及所述支撐杆分離,且具有靠近所述晶片踏板的第一端和從所述晶片踏板向外延伸的第二端;以及電源條,與所述至少兩個電源引腳連接,且所述電源條具有支撐部分;所述壓模材質,用於封裝所述引線框架;其中,所述電源條的所述支撐部分係朝向所述壓模材質的底面的方向設置的,且從所述壓模材質暴露出來。
- 如申請專利範圍第1項所述之半導體封裝,其中,所述至少兩個電源引腳的每一個具有靠近所述第二端的接合區域,所述接合區域從所述壓模材質暴露出來。
- 如申請專利範圍第2項所述之半導體封裝,其中,從所述壓模材質暴露出來的所述支撐部分的表面與所述第二端的接合區域共面。
- 如申請專利範圍第1項所述之半導體封裝,其中,所述電源條具有端子部分,所述端子部分與所述至少兩個電源引腳之一的第一端接觸,其中,所述支撐部分的厚度大於所述端子部分的厚度。
- 如申請專利範圍第1項所述之半導體封裝,其中,所述支撐部分未與所述至少兩個電源引腳中的任意一個接觸。
- 如申請專利範圍第1項所述之半導體封裝,其中,所述電源條設於所述晶片踏板和所述至少兩個電源引腳之間,且沿著相應的晶片踏板的邊緣的方向延伸。
- 如申請專利範圍第1項所述之半導體封裝,其中,所述電源條未與任何的接地引腳接觸。
- 如申請專利範圍第1項所述之半導體封裝,其中,所述支撐部分的厚度大於所述第一端的厚度。
- 如申請專利範圍第6項所述之半導體封裝,其中,所述支撐杆具有接地環部分,所述接地環部分圍繞在相應的晶片踏板的邊緣。
- 如申請專利範圍第9項所述之半導體封裝,其中,所述接地環部分與接地引腳接觸,所述接地引腳設於所述至少兩個電源引腳旁邊。
- 一種半導體封裝,包括引線框架和壓模材質,其中,所述引線框架包括:晶片踏板;支撐杆,所述支撐杆與所述晶片踏板電氣連接,且從所述晶片踏板向外方向延伸;至少兩個電源引腳,所述至少兩個電源引腳與所述晶片踏板、所述支撐杆分離,且具有靠近所述晶片踏板的第一端和從所述晶片踏板向外延伸的第二端;以及電源條,所述電源條與所述至少兩個電源引腳連接,其中, 所述電源條包括支撐部分,所述電源條的支撐部分的厚度大於所述第一端的厚度;所述壓模材質,用於封裝所述引線框架;其中,所述電源條的所述支撐部分係朝向所述壓模材質的底面的方向設置的。
- 如申請專利範圍第11項所述之半導體封裝,其中,所述壓模材質使所述支撐部分暴露出來。
- 如申請專利範圍第12項所述之半導體封裝,其中,所述至少兩個電源引腳的每一個具有靠近所述第二端的接合區域,所述接合區域從所述壓模材質暴露出來。
- 如申請專利範圍第13項所述之半導體封裝,其中,從所述壓模材質暴露出來的所述支撐部分的表面與所述第二端的接合區域共面。
- 如申請專利範圍第11項所述之半導體封裝,其中,所述電源條具有與所述至少兩個電源引腳之一的第一端接觸的端子部分,其中,所述支撐部分的厚度大於所述端子部分的厚度。
- 如申請專利範圍第11項所述之半導體封裝,其中,所述支撐部分未與所述至少兩個電源引腳中的任意一個接觸。
- 如申請專利範圍第11項所述之半導體封裝,其中,所述電源條設於所述晶片踏板和所述至少兩個電源引腳之間,且沿著相應的晶片踏板的邊緣的方向延伸。
- 如申請專利範圍第11項所述之半導體封裝,其中,所述電源條未與任何的接地引腳接觸。
- 如申請專利範圍第11項所述之半導體封裝,其中,所述支撐杆具有接地環部分,所述接地環部分圍繞在相應的晶片踏板的邊緣。
- 如申請專利範圍第19項所述之半導體封裝,其中,所述接地環部分與接地引腳接觸,所述接地引腳設於所述至少兩個電源引腳旁邊。
- 一種半導體封裝,包括引線框架和壓模材質,其中,所述引線框架包括:晶片踏板;支撐杆,與所述晶片踏板電氣連接,且從所述晶片踏板向外方向延伸;至少兩個電源引腳,與所述晶片踏板及所述支撐杆分離;以及電源條,具有端子部分和支撐部分,所述端子部分與所述至少兩個電源引腳之一的第一端接觸,所述支撐部分未與所述至少兩個電源引腳中的任何一個接觸,其中,所述支撐部分的厚大於所述端子部分的厚度;所述壓模材質,用於封裝所述引線框架;其中,所述電源條的所述支撐部分係朝向所述壓模材質的底面的方向設置的。
- 如申請專利範圍第21項所述之半導體封裝,其中,所述壓模材質使所述支撐部分暴露出來。
- 如申請專利範圍第22項所述之半導體封裝,其中,所述至少兩個電源引腳具有靠近所述晶片踏板的第一端和從所述 晶片踏板向外延伸的第二端。
- 如申請專利範圍第23項所述之半導體封裝,其中,所述至少兩個電源引腳的每一個具有靠近所述第二端的接合區域,所述接合區域從所述壓模材質暴露出來。
- 如申請專利範圍第24項所述之半導體封裝,其中,從所述壓模材質暴露出來的所述支撐部分的表面與所述第二端的接合區域共面。
- 如申請專利範圍第21項所述之半導體封裝,其中,所述電源條設於所述晶片踏板和所述至少兩個電源引腳之間,且沿著相應的晶片踏板的邊緣的方向延伸。
- 如申請專利範圍第21項所述之半導體封裝,其中,所述電源條未與任何的接地引腳接觸。
- 如申請專利範圍第21項所述之半導體封裝,其中,所述第二端的厚度大於所述第一端的厚度。
- 如申請專利範圍第21項所述之半導體封裝,其中,所述支撐杆具有接地環部分,所述接地環部分圍繞在相應的晶片踏板的邊緣。
- 如申請專利範圍第21項所述之半導體封裝,其中,所述接地環部分與接地引腳接觸,所述接地引腳設於所述至少兩個電源引腳旁邊。
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US11373936B2 (en) | 2019-11-14 | 2022-06-28 | Rohde & Schwarz Gmbh & Co. Kg | Flat no-leads package, packaged electronic component, printed circuit board and measurement device |
CN115331553B (zh) * | 2022-08-11 | 2023-11-10 | 合肥维信诺科技有限公司 | 屏体支撑件及显示模组 |
CN116403986A (zh) * | 2023-03-30 | 2023-07-07 | 宁波德洲精密电子有限公司 | 一种lqfp引线框架结构 |
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TW396565B (en) * | 1996-11-05 | 2000-07-01 | Gcb Technologies Llc | Improved leadframe structure and process for packaging integrated circuits |
TW200629488A (en) * | 2005-02-09 | 2006-08-16 | Renesas Tech Corp | Semiconductor device and electronic circuit |
TW200741924A (en) * | 2006-03-14 | 2007-11-01 | Advanced Interconnect Tech Ltd | Method for making QFN package with power and ground rings |
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US6882035B2 (en) | 2003-07-09 | 2005-04-19 | Agilent Technologies, Inc. | Die package |
US7875963B1 (en) * | 2008-11-21 | 2011-01-25 | Amkor Technology, Inc. | Semiconductor device including leadframe having power bars and increased I/O |
US9299646B1 (en) * | 2015-08-23 | 2016-03-29 | Freescale Semiconductor,Inc. | Lead frame with power and ground bars |
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