WO2019051710A1 - 芯片封装结构及方法、电子设备 - Google Patents

芯片封装结构及方法、电子设备 Download PDF

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Publication number
WO2019051710A1
WO2019051710A1 PCT/CN2017/101728 CN2017101728W WO2019051710A1 WO 2019051710 A1 WO2019051710 A1 WO 2019051710A1 CN 2017101728 W CN2017101728 W CN 2017101728W WO 2019051710 A1 WO2019051710 A1 WO 2019051710A1
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Prior art keywords
chip
pad
wire
metal
electrical conductor
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PCT/CN2017/101728
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English (en)
French (fr)
Inventor
吴宝全
喻新飞
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深圳市汇顶科技股份有限公司
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Priority to PCT/CN2017/101728 priority Critical patent/WO2019051710A1/zh
Priority to CN201780014545.XA priority patent/CN109891584A/zh
Priority to EP17905903.5A priority patent/EP3486944A1/en
Priority to US16/168,169 priority patent/US10770413B2/en
Publication of WO2019051710A1 publication Critical patent/WO2019051710A1/zh

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    • H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L24/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L24/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/42—Wire connectors; Manufacturing methods related thereto
    • H01L24/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L24/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/153—Connection portion
    • H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
    • H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/153—Connection portion
    • H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
    • H01L2924/15313—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a land array, e.g. LGA
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation
    • H01L2924/1815—Shape
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
    • H01L2924/191—Disposition
    • H01L2924/19101—Disposition of discrete passive components
    • H01L2924/19107—Disposition of discrete passive components off-chip wires

Definitions

  • the present application relates to the field of semiconductor packaging technologies, and in particular, to a chip package structure and method, and an electronic device.
  • anti-ESD Electro-Static discharge
  • Static electricity is generated from the outside of the chip package, first reaching the surface of the package, and then passing through the plastic sealing layer of the package to reach the surface of the chip, which will break through the functional circuit of the chip, causing the chip to fail. Due to the ubiquity of static electricity during the production, storage, transportation and use of electronic chips, the proportion of device failure caused by ESD problems is very large.
  • an anti-ESD breakdown protection circuit or an ESD electrostatic path is generally designed inside the chip, so that static electricity reaching the surface of the chip package can be derived through the designed path.
  • the chip package does not break through the functional circuitry of the chip.
  • static electricity does not completely follow the designed path to derive the chip package. If the static electricity is not led out of the chip package, it will still break through the functional circuit on the chip surface.
  • the purpose of some embodiments of the present application is to provide a chip package structure and method, and an electronic device, which substantially reduces the chip failure caused by electrostatic discharge without substantially increasing the cost of the chip package.
  • the embodiment of the present application provides a chip package structure, including: a support body, a chip, at least one electrical conductor, and a plastic package for molding the support body, the chip, and the electrical conductor; the chip is disposed on the upper surface of the support body, and the chip is mounted on the chip.
  • the surface is formed with a chip pad, and the chip pad is connected to the external pad of the support by wire bonding; the electrical conductor is connected to the ground pad in the external pad or the chip pad, and the electrical conductor is to the upper surface of the plastic body
  • the shortest distance is less than the shortest distance from the wire to the upper surface of the molding.
  • the embodiment of the present application further provides an electronic device including at least one of the above chip package structures.
  • the embodiment of the present application further provides a chip packaging method including: disposing a chip on an upper surface of a support body, and connecting a chip pad of an upper surface of the chip to an external pad of the support body by wire bonding; at least one conductive The body is connected to the ground pad in the external pad or the chip pad, and the maximum distance between the conductor and the support is greater than the maximum distance between the wire and the support; the support, the chip, the conductor are packaged, and the plastic body is formed Wherein the shortest distance from the conductor to the upper surface of the molding body is less than the shortest distance from the wire to the upper surface of the molding body.
  • the electrical conductor connected to the external pad of the support or the ground pad in the die pad is disposed in the plastic body, and the shortest distance from the electrical conductor to the upper surface of the molded body is smaller than the prior art.
  • the chip package structure is derived from the external pad or the ground pad through the electrical conductor, and the chip failure caused by the electrostatic discharge is greatly reduced on the basis of substantially no increase in the cost of the chip package.
  • the first end of the electrical conductor is connected to the external pad or the ground pad in the die pad, and the second end of the electrical conductor is exposed on the upper surface of the molding body.
  • the second end of the electrical conductor is exposed on the upper surface of the plastic body, so that when the static electricity reaches the upper surface of the plastic body (not yet entering the plastic body), the second end of the electric conductor can be quickly entered into the electric conductor to be exported. .
  • the electrical conductor is a metal wire, and the first end of the metal wire is connected to the external pad or the ground pad in the chip pad, and the second end of the metal wire is connected to the external pad.
  • This embodiment provides a specific arrangement when the conductive wire is a metal wire.
  • the first end of the metal line is connected to the external pad, and a part of the metal line is projected on the upper surface of the chip.
  • the first end and the second end of the metal wire are both connected to the external pad, and the metal wire straddles the upper surface of the chip, and the arrangement of the metal wire can further reduce the static electricity to the upper surface of the chip. The probability of the chip.
  • the metal wire is tangent to the upper surface of the molded body.
  • This embodiment provides another specific arrangement of the metal wire.
  • the metal wire is tangent to the upper surface of the plastic body, that is, the distance between the metal wire and the upper surface of the plastic body is small, so that the static electricity can reach the plastic body. When the surface is just entering the molding body, the metal wire is quickly tangential to the upper surface of the molding body to enter the metal wire to be led out.
  • the diameter of the wire is greater than or equal to 0.5 mils.
  • the difference between the shortest distance from the upper surface of the molded body and the shortest distance from the conductor to the upper surface of the molded body is greater than or equal to 10 ⁇ m to better derive static electricity.
  • the conductor is a metal wire or a metal block.
  • FIG. 1 is a cross-sectional view of a chip package structure in accordance with a first embodiment of the present application
  • FIG. 2 is a perspective view of a chip package structure according to a first embodiment of the present application
  • FIG. 3 is a cross-sectional view showing a chip package structure according to a second embodiment of the present application.
  • FIG. 4 is a cross-sectional view showing a chip package structure in a third embodiment of the present application.
  • 5A is a cross-sectional view showing a chip package structure in which a metal block is connected to an external pad according to a fourth embodiment of the present application;
  • 5B is a cross-sectional view showing a chip package structure in which a metal block is connected to a ground pad according to a fourth embodiment of the present application;
  • FIG. 6 is a cross-sectional view showing a chip package structure in a fifth embodiment of the present application.
  • FIG. 7 is a specific flowchart of a chip packaging method according to a sixth embodiment of the present application.
  • FIG. 8 is a specific flowchart of a chip packaging method according to a seventh embodiment of the present application.
  • FIG. 9 is a specific flowchart of a chip packaging method according to an eighth embodiment of the present application.
  • the first embodiment of the present application relates to a chip package structure, which is applied to an electronic device, such as a mobile phone, a tablet computer, or the like.
  • the package form of the chip can be QFN (Quad Flat No-lead Package), QFP (Plastic Quad Flat Package), square flat type
  • the package the LGA (Land Grid Array), the BGA (Ball Grid Array), and the like are not limited in this embodiment.
  • the chip package structure includes: a support body, a chip, at least one electrical conductor, and a plastic body for molding the support body, the chip, and the electrical conductor; the chip is disposed on the upper surface of the support body, and the chip is formed on the upper surface of the chip. a pad, and the chip pad is connected to the external pad of the support by wire bonding; the electrical conductor is connected to the ground pad in the external pad or the die pad, and the shortest distance from the conductor to the upper surface of the molded body is less than The shortest distance from the line to the upper surface of the molded body.
  • an electrical conductor connected to an external pad of the support body or a ground pad in the die pad is disposed in the molding body, and the shortest distance from the electrical conductor to the upper surface of the molding body is less than the wire bonding to the plastic sealing
  • the chip package structure is derived from the external pad or the ground pad, and the chip failure caused by the electrostatic discharge is greatly reduced on the basis of substantially no increase in the cost of the chip package.
  • the implementation details of the chip package structure of the present embodiment are specifically described below. The following content is only for the implementation details provided for convenience of understanding, and is not necessary for implementing the solution.
  • the conductor is a metal wire as an example.
  • the diameter of the metal wire may be greater than or equal to 0.5 mil, and the metal wire is, for example, a gold wire, a copper wire, an aluminum wire, or a silver wire. There are no restrictions on the type and diameter of the wire.
  • the chip package structure includes a support body, a chip 2, at least one electrical conductor, and a molding body 4.
  • the metal line 301, the metal line 302, the metal line 303, and the metal line 304 are all conductors.
  • the molded body 4 is used to mold the support, the chip 2, and the electrical conductor.
  • Plastic body 4 can be EMC (Epoxy Molding Compound, epoxy resin molding compound) is constituted, but this embodiment does not impose any limitation.
  • the support body may be a lead frame, a substrate, a metal frame or a non-metal frame.
  • the support body is a lead frame, which includes a frame body 11 and a plurality of external weldings located at the periphery of the frame body 11 .
  • the external pad 12 is an external pin of the chip package structure; wherein the positional relationship between the external pad 12 and the frame body 11 is not limited thereto, and the frame body 11 is also provided with a plurality of external pads 12;
  • the frame body 11 and the outer pad 12 may be made of the same electrical material, but are not limited thereto, and different electrical materials may be used.
  • the support body is taken as the lead frame.
  • the specific type of the support body is not limited in this embodiment.
  • the chip 2 is disposed on the upper surface of the support body, specifically, the chip 2 is fixed to the frame body 11 through the adhesive layer 5, and the upper surface 21 of the chip 2 is formed with a plurality of chip pads 22, and the chip pads 22 are the chips 2 A function pin or a ground pin, which is connected to the external pad 12 of the support by wire bonding, so that the chip can communicate with the outside.
  • one end of the wire is connected to the die pad 22 of the upper surface 21 of the chip 2, and therefore, the highest point of the wire is higher than the upper surface 21 of the chip 2.
  • the ground pad in the chip pad 22 is the ground pin of the chip. Referring to FIG. 2, three wires are illustrated, which are an electrical bonding wire 601, an electrical bonding wire 602, and an electrical bonding wire 603.
  • the die pad 22 is connected to the external pad 12 of the support through each electrical bonding wire.
  • the highest point of the arc of each electric welding wire is higher than the upper surface 21 of the chip 2, and the electric wire 601 is taken as an example, and the highest point 611 of the arc is higher than the upper surface 21 of the chip 2.
  • the shortest distance from the conductor to the upper surface 41 of the molding body 4 is the distance from the highest point of the arc of the metal wire to the upper surface 41 of the molding body 4, and the shortest distance from the upper surface 41 of the molding body 4
  • the distance from the highest point of the arc of the metal wire to the upper surface 41 of the molding body 4 is smaller than the highest point of the arc of the wire to the upper side of the molding body 4.
  • the distance of the surface 41 that is, the maximum distance between the metal line and the plane of the upper surface 21 of the chip 2 is greater than the maximum distance between the wire and the plane of the upper surface 21 of the chip 2, so that the static electricity reaches the upper surface 41 of the molded body 4 and After entering the molding body 4, the metal wire is first contacted, and the chip package structure is led out from the external pad 12 or the ground pad through the metal wire. Please refer to FIG.
  • the distance from the highest point of any metal line arc to the upper surface 41 is smaller than the distance from the highest point 611 of the electric bonding wire 601 to the upper surface 41 , taking the metal line 301 as an example, the metal line 301
  • the distance H 1 between the highest point 311 of the arc and the upper surface 41 is smaller than the distance H 2 from the highest point 611 of the electric bonding wire 601 from the upper surface 41; that is, the highest point 311 of the metal line 301 and the upper surface of the chip 2.
  • H 3 is greater than the upper surface 601 of the electric welding wire 21 from a plane where the highest point of the arc 611 and the plane 21 of the chip 2 distance H 4.
  • the difference between the highest point of the arc of the wire and the upper surface 41 of the molded body 4 and the distance from the highest point of the arc of the metal wire to the upper surface 41 of the molded body 4 is greater than or equal to 10 micrometers, that is, The difference between the distance H 2 of the highest point 611 of the electric bonding wire 601 from the upper surface 41 and the distance H 1 of the highest point 311 of the metal line 301 from the upper surface 41 is greater than or equal to 10 ⁇ m, H 2 -H 1 ⁇ 10 microns for better discharge of static electricity.
  • the first end of the metal wire is connected to the ground pad in the external pad 12 or the die pad 22, and the second end of the metal wire is connected to the external pad 12, that is, the metal wire is connected to any two Between the external pads 12 or between the chip pads 22 and the external pads 12, when the metal lines are connected to the chip pads 22, the connected chip pads 22 are ground pads; please refer to FIG. As an example of the line 302, the metal line 302 is connected to the external pad 12 and the ground pad of the chip 2.
  • the metal wire is connected between any two external pads 12,
  • the wire is placed across the upper surface 21 of the chip 2.
  • the metal line 303 and the metal line 304 in the figure all span the upper surface 21 of the chip 2, except that the positions and lengths of the two projections on the upper surface 21 of the chip 2 are different, that is, the projection area of the metal line 303 is long and The other side extending from one side to the side of the strip; the projected area of the metal line 304 is shorter and located at one corner of the upper surface 21 of the chip 2.
  • the highest point of the metal line is located within a region directly above the upper surface 21 of the chip 2, or a metal wire that does not span the upper surface 21 of the chip 2 (for example)
  • the metal line 301) is closer to the area directly above the upper surface 21 of the chip 2; for example, the highest point of the metal line 303 is located directly above the upper surface 21 of the chip 2; the highest point of the metal line 301 is metal
  • the highest point of the line 304 is located outside the area directly above the upper surface 21 of the chip 2, but the highest point of the metal line 304 is closer to the area immediately above the upper surface 21 of the chip 2 than the highest point of the metal line 301.
  • the path of the highest point of the metal wire (for example, the metal wire 303, the metal wire 304) is relative to the path reaching the highest point of the metal wire (for example, the metal wire 301) that does not straddle the upper surface 21 of the chip 2 Relatively close, the static electricity can be derived more quickly and efficiently, and the probability that the static electricity reaches the upper surface 21 of the chip 2 to damage the chip 2 is reduced (the longer the path of the static electricity reaching the highest point of the metal wire, the greater the probability of error).
  • the second embodiment of the present application relates to a chip package structure, which is based on the first embodiment.
  • the main improvement is that, referring to FIG. 3, the second end of the electrical conductor (metal wire) is exposed on the upper surface 41 of the molding body 4.
  • the first end of the metal wire is connected to the ground pad in the external pad 12 or the die pad 22, and the second end of the metal wire is exposed on the upper surface 41 of the molding body 4, and the arc of the metal wire is the highest.
  • the distance from the point to the upper surface 41 of the molding body 4 is zero, which is smaller than the distance from the highest point of the arc of the wire to the upper surface 41 of the molding body 4.
  • FIG. 3 which is based on the chip package structure of FIG.
  • the upper surface 41 of the molded body 4 is ground such that the metal wire 301, the metal wire 302, and the metal wire 303 are ground to be exposed on the upper surface 41 of the package 4.
  • the second end of the metal wire is exposed on the upper surface of the molding body to be quickly formed by the metal wire when the static electricity reaches the upper surface of the molding body (not yet entering the molding body).
  • the second end enters the metal line, and then the chip package structure is derived from the external pad or ground pad to which the metal line is connected.
  • the third embodiment of the present application relates to a chip package structure.
  • This embodiment is an improvement on the basis of the first embodiment.
  • the main improvement is that: referring to FIG. 4, the electrical conductor (metal wire) and the plastic body are disposed.
  • the surface is tangent.
  • the metal wire is tangential to the upper surface 41 of the molding body 4.
  • the distance from the highest point of the arc of the metal wire to the upper surface 41 of the molded body 4 is close to zero, which is smaller than the distance from the highest point of the arc of the wire to the upper surface 41 of the molded body 4.
  • the metal wire 301, the metal wire 302, and the metal wire 303 are both tangent to the upper surface 41 of the molding body 4.
  • This embodiment provides another specific arrangement of metal wires with respect to the first embodiment.
  • the metal wire is tangent to the upper surface of the plastic body, that is, the distance between the metal wire and the upper surface of the plastic body is small, so that the static electricity can be quickly reached by the metal wire when it reaches the upper surface of the plastic body and just enters the plastic body.
  • the upper surface of the molded body is tangent to the metal wire to be led out.
  • the fourth embodiment of the present invention relates to a chip package structure.
  • the present embodiment is substantially the same as the first embodiment.
  • the main difference is that, in this embodiment, referring to FIG. 5A and FIG. 5B, the electrical conductor is a metal block.
  • the electrical conductor When the electrical conductor is a metal block, it can be connected to the external pad of the support or the ground pad in the die pad, as follows:
  • the metal block is connected to the outer surface of the support.
  • the metal block 31 is disposed on the upper surface of the support body.
  • the metal block 31 is disposed on the support body.
  • the frame body 11 is not limited thereto, and the metal block 31 is connected to the external pad of the support body, that is, to any external pad 12 on the frame body 11 to discharge the static electricity to the chip package structure. external.
  • the external pad 12 connected to the frame body 11 by the metal block 31 is taken as an example.
  • the metal block 31 may be connected to any external pad of the support body, but this embodiment is This is not subject to any restrictions.
  • the metal block is connected to the ground pad in the die pad.
  • the metal block 33 is disposed on the upper surface 21 of the chip 2, and the connected chip pad 22 is a ground pad, so that the static electricity can be extracted. To the outside of the chip package structure.
  • the shortest distance from the conductor to the upper surface 41 of the molding body 4 is the distance from the upper surface of the metal block to the upper surface 41 of the molding body 4, and the shortest distance from the wire to the upper surface 41 of the molding body 4 is The distance from the highest point of the arc of the line to the upper surface 41 of the molded body 4, the distance from the upper surface of the metal block to the upper surface 41 of the molded body 4 is less than the highest point of the arc of the wire to the upper surface 41 of the molded body 4.
  • the distance; that is, the distance between the upper surface of the metal block and the plane of the upper surface 21 of the chip 2 is greater than the distance between the highest point of the arc of the wire and the plane of the upper surface 21 of the chip 2.
  • the distance from the upper surface 32 of the metal block 31 to the upper surface 41 of the molding body 4 is smaller than the distance from the highest point 611 of the electric bonding wire 601 to the upper surface 41, and the metal block 31
  • the distance between the upper surface 32 and the plane of the upper surface 21 of the chip 2 is greater than the distance between the highest point 611 of the electrical bond wire 601 and the plane of the upper surface 21 of the chip 2.
  • the difference between the highest point of the arc of the wire and the upper surface 41 of the molded body 4 and the distance from the upper surface of the metal block to the upper surface 41 of the molded body 4 is greater than or equal to 10 micrometers.
  • the difference between the distance of the highest point 611 of the electric bonding wire 601 from the upper surface 41 and the distance from the upper surface 32 of the metal block 31 to the upper surface 41 of the molding body 4 is greater than or Equal to 10 microns to better derive static electricity.
  • FIG. 5A and FIG. 5B only the shape, the number, and the position of the metal block are schematically described. However, the embodiment does not impose any limitation.
  • the fifth embodiment of the present application relates to a chip package structure.
  • This embodiment is an improvement on the basis of the fourth embodiment.
  • the main improvement is that: referring to FIG. 6, the second end of the electrical conductor (metal block) is exposed.
  • the first end of the metal block is connected to the outer pad 12, and the second end of the metal block is exposed on the upper surface 41 of the molding body 4.
  • the metal block 31 is polished.
  • the upper surface 32 is in the same plane as the upper surface 41 of the molding body 4, and when the static electricity reaches the upper surface 41 of the molding body 4 (has not yet entered the molding body), it can be quickly formed by the metal block 31.
  • the upper surface 32 enters the metal block 31, which in turn is led out of the chip package from the outer pad 12 to which the metal block 31 is connected.
  • the second end of the metal block is exposed on the upper surface of the molding body to be quickly formed by the metal block when the static electricity reaches the upper surface of the molding body (not yet entering the molding body).
  • the second end enters the metal block and is then derived from the external pad to which the metal block is connected.
  • the sixth embodiment of the present application relates to an electronic device, such as a mobile phone, a tablet computer, or the like.
  • the electronic device includes at least one of the chip package structures of any of the first to fifth embodiments.
  • the electrical conductor connected to the external pad of the support or the ground pad in the die pad is disposed in the plastic body, and the shortest distance from the electrical conductor to the upper surface of the molded body is less than that of the prior art.
  • the chip package structure is derived from the external pad or the ground pad by the electrical conductor, and the chip failure caused by the electrostatic discharge is greatly reduced on the basis of substantially no increase in the cost of the chip package.
  • the seventh embodiment of the present invention relates to a chip packaging method, which is applied to package a chip, and the package form of the chip may be a QFN (Quad Flat No-lead Package) or a QFP (Plastic Quad Flat Package).
  • the square flat package), the LGA (Land Grid Array), the BGA (Ball Grid Array), and the like are not limited in this embodiment.
  • step 101 the chip is disposed on the upper surface of the support, and the chip pad of the upper surface of the chip is connected to the external pad of the support by wire bonding.
  • the chip is bonded to the upper surface of the support by an adhesive, please refer to FIG.
  • the support body is an example of a lead frame, which includes a frame body 11 and a plurality of external pads 12, and the frame body 11 is also provided with a plurality of external pads 12, and the chip 2 is fixed to the frame body 11 through the adhesive layer 5, and
  • the die pad 22 of the upper surface 21 of the chip 2 is connected to the external pad 12 of the support by wire bonding; therefore, the highest point of the wire is higher than the plane of the upper surface 21 of the chip 2, that is, the electrical bonding wire
  • the arc highest point 611 of 601 is higher than the plane of the upper surface 21 of the chip 2.
  • Step 102 connecting at least one electrical conductor to a ground pad in an external pad or chip pad.
  • the electrical conductor may be a metal wire or a metal block.
  • the maximum distance between the electrical conductor and the support body is greater than the maximum distance between the wire and the support body, that is, the plane between the electrical conductor and the upper surface of the chip.
  • the maximum distance is greater than the maximum distance between the highest point of the arc and the plane of the upper surface of the chip.
  • the electrical conductor is a metal wire
  • the first end of the metal wire is connected to the external pad or the ground pad in the die pad
  • the second end of the metal wire is connected to the external pad.
  • the shortest distance from the conductor to the upper surface 41 of the molding body 4 is the distance from the highest point of the arc of the metal wire to the upper surface 41 of the molding body 4, and the shortest distance from the upper surface 41 of the molding body 4 is the arc of the wire bonding.
  • the distance from the highest point of the line to the upper surface 41 of the molding body 4, the distance from the highest point of the arc of the metal wire to the upper surface 41 of the molding body 4 is smaller than the distance from the highest point of the arc of the wire to the upper surface 41 of the molding body 4; That is, the maximum distance between the conductor and the upper surface 21 of the chip 2 is greater than the maximum distance between the wire and the upper surface 21 of the chip 2.
  • the arc highest point 311 of the metal wire 301 is greater than the distance from the lead frame 11 by the distance from the highest point 611 of the electric bonding wire 601 to the lead frame 11; that is, the metal wire 301
  • the distance between the highest point 311 of the arc and the plane of the upper surface 21 of the chip 2 is greater than the distance between the highest point 611 of the electric bonding wire 601 and the plane of the upper surface 21 of the chip 2.
  • the diameter of the metal wire may be greater than or equal to 0.5 mil.
  • the metal block is connected to the external pad of the support or the connection in the die pad Ground pad.
  • the metal block is connected to the outer pad of the support; the shortest distance from the conductor to the upper surface 41 of the mold body 4 is the upper surface 32 of the metal block 31.
  • the distance from the upper surface 41 of the molding body 4 to the upper surface 41 of the molding body 4 is the distance from the highest point of the arc of the wire to the upper surface 41 of the molding body 4, and the upper surface 32 of the metal block 31.
  • the distance from the upper surface 41 of the molding body 4 is smaller than the distance from the highest point of the arc of the wire to the upper surface 41 of the molding body 4; that is, the distance from the upper surface 32 of the metal block 31 to the plane of the upper surface 21 of the chip 2.
  • the distance from the upper surface 32 of the metal block 31 to the lead frame 11 is greater than the distance from the highest point 611 of the electric bonding wire 601 to the lead frame 11, that is, the upper surface 32 of the metal block 31 and the upper surface of the chip 2.
  • the distance of the plane of the surface 21 is greater than the distance between the highest point 611 of the electric bonding wire 601 and the plane of the upper surface 21 of the chip 2.
  • step 103 the support, the chip, and the electrical conductor are packaged, and a molded body is formed.
  • the support body is placed in a mold, and the plastic sealant is injected to form a plastic seal body after the plastic sealant is cured.
  • the plastic seal body please refer to FIG. Wherein, since the maximum distance between the conductor and the support body during soldering in step 102 is greater than the maximum distance between the wire and the support body, the shortest distance from the conductor to the upper surface of the molded body is less than that of the wire to the formed body. The shortest distance from the upper surface of the molded body.
  • the maximum distance between the conductor and the support is greater than or equal to 10 micrometers, and the difference between the wire and the maximum distance of the support is greater than or equal to 10 micrometers, so that the plastic body is wired to the plastic body 4.
  • the difference between the shortest distance of the upper surface 41 and the shortest distance of the conductor to the upper surface 41 of the molding body 4 is greater than or equal to 10 ⁇ m to better derive static electricity.
  • the present embodiment can be implemented in cooperation with the first embodiment and the fourth embodiment.
  • First embodiment, phase mentioned in the fourth embodiment The technical details are still valid in the embodiment, and the technical effects that can be achieved in the first embodiment and the fourth embodiment are also implemented in the embodiment. To reduce the repetition, details are not described herein again. Accordingly, the related art details mentioned in the embodiment can also be applied to the first embodiment and the fourth embodiment.
  • the electrical conductors added to the prior art are metal wires or metal blocks, which are all existing materials and do not affect the packaging process. Therefore, the actual added cost is only less than one percent. , has good economic benefits.
  • the electrical conductor connected to the external pad of the support or the ground pad in the die pad is disposed in the plastic body, and the shortest distance from the electrical conductor to the upper surface of the molded body is less than that of the prior art.
  • the chip package structure is derived from the external pad or the ground pad by the electrical conductor, and the chip failure caused by the electrostatic discharge is greatly reduced on the basis of substantially no increase in the cost of the chip package.
  • the eighth embodiment of the present application relates to a chip packaging method.
  • the embodiment is an improvement based on the seventh embodiment.
  • the main improvement is that in the embodiment, after forming the plastic body, the upper surface of the plastic body is formed. The treatment is performed such that the second end of the electrical conductor is exposed to the upper surface of the molded body.
  • Steps 201 to 203 are substantially the same as steps 101 to 103.
  • the main difference is that step 204 is added in this embodiment, as follows:
  • step 204 the upper surface of the molding body is treated to expose the electrical conductor.
  • the upper surface of the molding body is appropriately sanded so that the second end of the conductor is exposed on the upper surface of the molding body.
  • the electrical conductor is a metal wire, which is based on the chip package structure of FIG. Sanding causes the metal wire 301, the metal wire 302, and the metal wire 303 to be ground to be exposed on the upper surface 41 of the package 4.
  • the electrical conductor is a metal block, and the upper surface 41 of the plastic body 4 is polished on the basis of the chip package structure of FIG. 5A (for example, the chip package structure of FIG. 5A is not limited thereto).
  • the upper surface 32 of the metal block 31 and the upper surface 41 of the molding body 4 are in the same plane.
  • at least one electrical conductor may be directly connected to the step 102 (step 202 in this embodiment).
  • the present embodiment can be implemented in cooperation with the second embodiment and the fifth embodiment.
  • the related technical details mentioned in the second embodiment and the fifth embodiment are still effective in this embodiment, and the technical effects that can be achieved in the second embodiment and the fifth embodiment can also be implemented in this embodiment. In order to reduce duplication, we will not repeat them here. Accordingly, the related art details mentioned in this embodiment can also be applied to the second embodiment and the fifth embodiment.
  • the second end of the electrical conductor is exposed to the upper surface of the molding body so as to be quickly formed by the electrical conductor when the static electricity reaches the upper surface of the molding body (not yet entering the molding body).
  • the second end enters the electrical conductor to be derived.
  • the ninth embodiment of the present application relates to a chip packaging method.
  • the embodiment is an improvement on the basis of the seventh embodiment.
  • the main improvement is that when the conductor is a metal wire, the metal wire is made during the molding process.
  • the upper surface of the molded body is tangent.
  • Step 301 the chip is disposed on the upper surface of the support, and the chip pad of the upper surface of the chip is connected to the external pad of the support by wire bonding.
  • step 101 in the seventh embodiment is substantially the same as step 101 in the seventh embodiment, and details are not described herein again.
  • Step 302 connecting the first end of the metal line to the ground pad in the external pad or the die pad, and connecting the second end of the metal line to the external pad.
  • the metal line 302 is connected to the external pad 12 and the ground pad in the die pad 22 .
  • the metal wire when the metal wire is connected between any two external pads 12, it is arranged that the metal wire straddles the upper surface 21 of the chip 2.
  • the metal line 303 and the metal line 304 in the figure all span the upper surface 21 of the chip 2, except that the positions and lengths of the two projections on the upper surface 21 of the chip 2 are different, that is, the projection area of the metal line 303 is long and The other side extending from one side to the side of the strip; the projected area of the metal line 304 is shorter and located at one corner of the upper surface 21 of the chip 2.
  • the highest point of the metal line is located within a region directly above the upper surface 21 of the chip 2, or a metal wire that does not span the upper surface 21 of the chip 2 (for example)
  • the metal line 301) is closer to the area directly above the upper surface 21 of the chip 2; for example, the highest point of the metal line 303 is located directly above the upper surface 21 of the chip 2; the highest point of the metal line 301 is metal
  • the highest point of the line 304 is located outside the area directly above the upper surface 21 of the chip 2, but the highest point of the metal line 304 is closer to the area immediately above the upper surface 21 of the chip 2 than the highest point of the metal line 301.
  • the path of the highest point of the metal wire (for example, the metal wire 303, the metal wire 304) is relative to the path reaching the highest point of the metal wire (for example, the metal wire 301) that does not straddle the upper surface 21 of the chip 2 Relatively close, the static electricity can be derived more quickly and efficiently, and the probability that the static electricity reaches the upper surface 21 of the chip 2 to damage the chip 2 is reduced (the longer the path of the static electricity reaching the highest point of the metal wire, the greater the probability of error).
  • Step 303 in the molding process, compressing the upper surface of the molding body so that the metal wire is tangent to the upper surface of the molding body.
  • the metal wire is provided to be tangent to the upper surface 41 of the molded body 4.
  • the metal wire 301, the metal wire 302, and the metal wire 303 are both tangent to the upper surface 41 of the molding body 4.
  • the present embodiment can be implemented in cooperation with the third embodiment.
  • the technical details mentioned in the third embodiment are still effective in this embodiment, and the technical effects that can be achieved in the third embodiment can also be implemented in this embodiment. To reduce repetition, details are not described herein again. Accordingly, the related art details mentioned in the embodiment can also be applied to the third embodiment.
  • this embodiment provides another specific arrangement of the metal wire, the metal wire being tangent to the upper surface of the plastic body, that is, the distance between the metal wire and the upper surface of the plastic body is small, thereby The static electricity can be led to enter the metal wire to be led out when the metal wire reaches the upper surface of the molding body and just enters the molding body, and the metal wire is tangential to the upper surface of the molding body.

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  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
  • Wire Bonding (AREA)

Abstract

一种芯片封装结构及方法、电子设备。芯片封装结构包括：支撑体、芯片（2）、至少一导电体以及用于塑封支撑体、芯片、导电体的塑封体（4）；芯片设置于支撑体的上表面，芯片的上表面（21）形成有芯片焊盘（22），且芯片焊盘通过打线连接至支撑体的外部焊盘（12）；导电体连接于外部焊盘或芯片焊盘中的接地焊盘，且导电体至塑封体的上表面（41）的最短距离小于打线至塑封体的上表面的最短距离。在基本不增加芯片封装的成本基础上，大幅减少静电释放导致的芯片失效问题。

Description

芯片封装结构及方法、电子设备 技术领域
本申请涉及半导体封装技术领域，特别涉及一种芯片封装结构及方法、电子设备。
背景技术
对电子零部件以及IC封装而言，抗ESD(Electro-Static discharge，静电释放)击穿是一个非常重要的电学指标。从芯片封装体外部产生静电，首先达到封装体表面，然后穿过封装体的塑封层，到达芯片表面，便会击穿芯片的功能电路，造成芯片功能性失效。由于电子芯片在生产、存储、运输及使用过程中，静电无处不在，ESD问题导致的器件失效所占的比重非常大。
发明人发现现有技术至少存在以下问题：现有的芯片封装体中，一般会在芯片内部设计抗ESD击穿保护电路或ESD静电通路，让到达芯片封装体表面的静电可以通过设计的通路导出芯片封装体而不会击穿芯片的功能电路。然而，由于ESD静电来源的多样性以及模式特性的不同，静电并不会完全按照设计的通路导出芯片封装体，若静电未被导出芯片封装体，则仍会击穿芯片表面的功能电路。
发明内容
本申请部分实施例的目的在于提供一种芯片封装结构及方法、电子设备，在基本不增加芯片封装的成本基础上，大幅减少静电释放导致的芯片失效问题。
本申请实施例提供了一种芯片封装结构，包括：支撑体、芯片、至少一导电体以及用于塑封支撑体、芯片、导电体的塑封体；芯片设置于支撑体的上表面，芯片的上表面形成有芯片焊盘，且芯片焊盘通过打线连接至支撑体的外部焊盘；导电体连接于外部焊盘或芯片焊盘中的接地焊盘，且导电体至塑封体的上表面的最短距离小于打线至塑封体的上表面的最短距离。
本申请实施例还提供了一种电子设备，包括至少一个上述的芯片封装结构。
本申请实施例还提供了一种芯片封装方法包括：将芯片设置于支撑体的上表面，并通过打线将芯片的上表面的芯片焊盘连接至支撑体的外部焊盘；将至少一导电体连接于外部焊盘或芯片焊盘中的接地焊盘，且导电体与支撑体的最大距离大于打线与支撑体的最大距离；对支撑体、芯片、导电体进行封装，并形成塑封体；其中，导电体至塑封体的上表面的最短距离小于打线至塑封体的上表面的最短距离。
本申请实施例相对于现有技术而言，在塑封体内设置连接于支撑体的外部焊盘或芯片焊盘中的接地焊盘的导电体，且导电体至塑封体的上表面的最短距离小于打线至塑封体的上表面的最短距离；即导电体较芯片、打线相比，更接近塑封体的上表面，使得静电达到塑封体的上表面并进入塑封体后首先接触到导电体，并通过导电体从外部焊盘或接地焊盘导出芯片封装结构，在基本不增加芯片封装的成本基础上，大幅减少静电释放导致的芯片失效问题。
另外，导电体的第一端连接于外部焊盘或芯片焊盘中的接地焊盘，导电体的第二端裸露于塑封体的上表面。本实施例设置导电体的第二端裸露于塑封体的上表面，以在静电达到塑封体的上表面时(尚未进入塑封体)，能够迅速由导电体的第二端进入导电体以被导出。
另外，导电体为金属线，金属线的第一端连接于外部焊盘或芯片焊盘中的接地焊盘，金属线的第二端连接于外部焊盘。本实施例提供了导电为金属线时的一种具体设置方式。
另外，金属线的第一端连接于外部焊盘，且金属线的一部分投影在芯片的上表面。本实施例中，金属线的第一端与第二端均连接于外部焊盘，且金属线横跨芯片的上表面，金属线的这种设置方式可以进一步减小静电达到芯片的上表面损坏芯片的机率。
另外，金属线与塑封体的上表面相切。本实施例提供了金属线的另一种具体设置方式，金属线与塑封体的上表面相切，即金属线与塑封体的上表面的距离很小，从而能使得静电在到达塑封体的上表面并在刚进入塑封体时，迅速由金属线上与塑封体的上表面相切位置进入金属线以被导出。
另外，金属线的直径大于或等于0.5密耳。
另外，打线至塑封体的上表面的最短距离和导电体至塑封体的上表面的最短距离的差值大于或等于10微米，以更好的导出静电。
另外，导电体为金属线或金属块。
附图说明
一个或多个实施例通过与之对应的附图中的图片进行示例性说明，这些 示例性说明并不构成对实施例的限定，附图中具有相同参考数字标号的元件表示为类似的元件，除非有特别申明，附图中的图不构成比例限制。
图1是根据本申请第一实施例中的芯片封装结构的剖面示意图；
图2是根据本申请第一实施例中的芯片封装结构的立体示意图；
图3是根据本申请第二实施例中的芯片封装结构的剖面示意图；
图4是根据本申请第三实施例中的芯片封装结构的剖面示意图；
图5A是根据本申请第四实施例中的金属块连接于外部焊盘的芯片封装结构的剖面示意图；
图5B是根据本申请第四实施例中的金属块连接于接地焊盘的芯片封装结构的剖面示意图；
图6是根据本申请第五实施例中的芯片封装结构的剖面示意图；
图7是根据本申请第六实施例中的芯片封装方法的具体流程图；
图8是根据本申请第七实施例中的芯片封装方法的具体流程图；
图9是根据本申请第八实施例中的芯片封装方法的具体流程图。
具体实施例
为了使本申请的目的、技术方案及优点更加清楚明白，以下结合附图及实施例，对本申请部分实施例进行进一步详细说明。应当理解，此处所描述的具体实施例仅仅用以解释本申请，并不用于限定本申请。
本申请第一实施例涉及一种芯片封装结构，应用于电子设备，电子设备例如为手机、平板电脑等。芯片的封装形式可以为QFN(Quad Flat No-lead Package，方形扁平无引脚封装)、QFP(Plastic Quad Flat Package，方型扁平式 封装)、LGA(Land Grid Array，栅格阵列封装)、BGA(Ball Grid Array，焊球阵列封装)等，然本实施例对此不作任何限制。
本实施例中，芯片封装结构包括：支撑体、芯片、至少一导电体以及用于塑封支撑体、芯片、导电体的塑封体；芯片设置于支撑体的上表面，芯片的上表面形成有芯片焊盘，且芯片焊盘通过打线连接至支撑体的外部焊盘；导电体连接于外部焊盘或芯片焊盘中的接地焊盘，且导电体至塑封体的上表面的最短距离小于打线至塑封体的上表面的最短距离。
相对于现有技术而言，在塑封体内设置连接于支撑体的外部焊盘或芯片焊盘中的接地焊盘的导电体，且导电体至塑封体的上表面的最短距离小于打线至塑封体的上表面的最短距离；即导电体较芯片、打线相比，更接近塑封体的上表面，使得静电达到塑封体的上表面并进入塑封体后首先接触到导电体，并通过导电体从外部焊盘或接地焊盘导出芯片封装结构，在基本不增加芯片封装的成本基础上，大幅减少静电释放导致的芯片失效问题。下面对本实施例的芯片封装结构的实现细节进行具体的说明，以下内容仅为方便理解提供的实现细节，并非实施本方案的必须。
本实施例中，以导电体为金属线为例进行说明，金属线的直径可以大于或等于0.5密耳，金属线例如为金线、铜线、铝线或银线等，然本实施例金属线的种类以及直径不作任何限制。
请参考图1、2，芯片封装结构包括支撑体、芯片2、至少一导电体以及塑封体4。图中金属线301、金属线302、金属线303以及金属线304均为导电体。
塑封体4用于塑封支撑体、芯片2以及导电体。塑封体4可由EMC (Epoxy Molding Compound，环氧树脂模塑料)构成，然本实施例对此不作任何限制。
请参考图1，支撑体可以为引线框架、基板、金属框架或非金属框架等，图1中以支撑体为引线框架为例，其包括框架主体11以及位于框架主体11外围的多个外部焊盘12，外部焊盘12即作为芯片封装结构的外部引脚；其中，外部焊盘12与框架主体11的位置关系不限于此，框架主体11上也设有多个外部焊盘12；另外，框架主体11与外部焊盘12可采用相同的电气材料，然不限于此，也可以采用不同的电气材料。
需要说明的是，本实施例以及之后的实施例中均以支撑体为引线框架为例，然本实施例对支撑体的具体类型不作任何限制。
芯片2设置于支撑体的上表面，具体为芯片2通过粘接胶层5固定于框架主体11，芯片2的上表面21形成有多个芯片焊盘22，芯片焊盘22即为芯片2的功能引脚或接地引脚，芯片焊盘22通过打线连接至支撑体的外部焊盘12，从而使得芯片可以与外部通信。其中，打线的一端连接于芯片2的上表面21的芯片焊盘22上，因此，打线的弧线最高点高于芯片2的上表面21。其中，芯片焊盘22中的接地焊盘即为芯片的接地引脚。请参考图2，图中示意出了3根打线，分别为电气焊线601、电气焊线602、电气焊线603，芯片焊盘22通过各电气焊线连接至支撑体的外部焊盘12，各电气焊线的弧线最高点高于芯片2的上表面21，以电气焊线601为例，其弧线最高点611高于芯片2的上表面21。
本实施例中，导电体至塑封体4的上表面41的最短距离为金属线的弧线最高点至塑封体4的上表面41的距离，打线至塑封体4的上表面41的最短 距离为打线的弧线最高点至塑封体4的上表面41的距离，金属线的弧线最高点至塑封体4的上表面41的距离小于打线的弧线最高点至塑封体4的上表面41的距离；亦即，金属线与芯片2的上表面21所在平面的最大距离大于打线与芯片2的上表面21所在平面的最大距离，以使静电达到塑封体4的上表面41并进入塑封体4后首先接触到金属线，并通过金属线从外部焊盘12或接地焊盘导出芯片封装结构。请参考图1，任一金属线弧线最高点距离上表面41的距离，小于电气焊线601的弧线最高点611距离上表面41的距离线，以金属线301为例，金属线301的弧线最高点311与上表面41的距离H1小于电气焊线601的弧线最高点611距离上表面41的距离H2；即，金属线301的弧线最高点311与芯片2的上表面21所在平面的距离H3大于电气焊线601的弧线最高点611与芯片2的上表面21所在平面的距离H4。
较佳的，打线的弧线最高点至塑封体4的上表面41的距离和金属线的弧线最高点至塑封体4的上表面41的距离的差值大于或等于10微米，即，电气焊线601的弧线最高点611距离上表面41的距离H2与金属线301的弧线最高点311距离上表面41的距离H1的差值大于或等于10微米，H2-H1≥10微米，以更好的导出静电。
本实施例中，金属线的第一端连接于外部焊盘12或芯片焊盘22中的接地焊盘，金属线的第二端连接于外部焊盘12，即，金属线连接于任意两个外部焊盘12之间或连接于芯片焊盘22与外部焊盘12之间，当金属线连接于芯片焊盘22时，连接的该芯片焊盘22为接地焊盘；请参考图1，以金属线302为例，金属线302连接于外部焊盘12与芯片2的接地焊盘。
较佳的，请参考图2，当金属线连接于任意两个外部焊盘12之间时，设 置为：金属线横跨芯片2的上表面21。图中金属线303、金属线304均横跨芯片2的上表面21，不同之处在于两者投影在芯片2的上表面21的位置和长度均不同，即金属线303的投影区域较长且从一条边延伸至与该条边相对的另一条边；金属线304的投影区域较短且位于芯片2的上表面21的一个边角处。其中，当金属线横跨芯片2的上表面21时，金属线的最高点位于芯片2的上表面21的正上方区域之内、或较未横跨芯片2的上表面21的金属线(例如，金属线301)来说更接近芯片2的上表面21的正上方区域；例如，金属线303的最高点位于芯片2的上表面21的正上方区域之内；金属线301的最高点与金属线304的最高点均位于芯片2的上表面21的正上方区域之外，但是金属线304的最高点较金属线301的最高点更接近芯片2的上表面21的正上方区域。当静电从芯片2的上表面21的正上方区域(即塑封体4的上表面41对应于芯片2的上表面21的区域)进入塑封体4内时，静电到达横跨芯片2的上表面21的金属线(例如金属线303、金属线304)的最高点的路径，相对于到达未横跨芯片2的上表面21的金属线(例如，金属线301)的最高点的路径而言，会相对近一点，从而可以更快更有效地导出静电，减小了静电达到芯片2的上表面21损坏芯片2的机率(静电到达金属线的最高点的路径越长，失误的概率越大)。
需要说明的是，图2中仅示意性描述金属线横(金属线303、金属线304)跨芯片2上表面21的位置，然本实施例对此不做任何限制。
需要说明的是，本实施例中的各附图仅示意性表示出导电体(金属线)的数目，然本实施例对导电体的数目不作任何限制。
本申请第二实施例涉及一种芯片封装结构，本实施例是在第一实施例基 础上的改进，主要改进之处在于：请参考图3，导电体(金属线)的第二端裸露于塑封体4的上表面41。
本实施例中，金属线的第一端连接于外部焊盘12或芯片焊盘22中的接地焊盘，金属线的第二端裸露于塑封体4的上表面41，金属线的弧线最高点至塑封体4的上表面41的距离为零，小于打线的弧线最高点至塑封体4的上表面41的距离，请参考图3，为在图1的芯片封装结构的基础上对塑封体4的上表面41进行打磨，使得金属线301、金属线302以及金属线303被磨断，从而裸露在封装体4的上表面41。
本实施例相对于第一实施例而言，设置金属线的第二端裸露于塑封体的上表面，以在静电达到塑封体的上表面时(尚未进入塑封体)，能够迅速由金属线的第二端进入金属线，继而从金属线连接的外部焊盘或接地焊盘被导出芯片封装结构。
本申请第三实施例涉及一种芯片封装结构，本实施例是在第一实施例基础上的改进，主要改进之处在于：请参考图4，设置导电体(金属线)与塑封体的上表面相切。
本实施例中，金属线的弧线最高点越接近塑封体4的上表面41，其导出静电的效果越好，较佳的，设置金属线与塑封体4的上表面41相切，此时，金属线的弧线最高点至塑封体4的上表面41的距离接近于零，小于打线的弧线最高点至塑封体4的上表面41的距离。请参考图4，金属线301、金属线302以及金属线303均与塑封体4的上表面41相切，然不限于此，也可以是其中部分金属线与塑封体4的上表面41相切，本实施例对此不做任何限制。
本实施例相对于第一实施例而言，提供了金属线的另一种具体设置方式， 金属线与塑封体的上表面相切，即金属线与塑封体的上表面的距离很小，从而能使得静电在到达塑封体的上表面并在刚进入塑封体时，迅速由金属线上与塑封体的上表面相切位置进入金属线以被导出。
本申请第四实施例涉及一种芯片封装结构，本实施例与第一实施例大致相同，主要不同之处在于：本实施例中，请参考图5A、图5B，导电体为金属块。
当导电体为金属块时，其可以连接于支撑体的外部焊盘或芯片焊盘中的接地焊盘，具体如下：
方式一、金属块连接于支撑体的外部焊盘，请参考图5A，金属块31设置于支撑体的上表面，具体为金属块31设置于支撑体(以支撑体为引线框架为例，然不以此为限)的框架主体11上，且金属块31连接于支撑体的外部焊盘，即，连接于框架主体11上的任意一外部焊盘12，以将静电导出到芯片封装结构的外部。需要说明的是，图中以金属块31连接于框架主体11上的外部焊盘12为例，然不限于此，金属块31可以连接于支撑体的任一外部焊盘，然本实施例对此不作任何限制。
方式二、金属块连接于芯片焊盘中的接地焊盘，请参考图5B，金属块33设置于芯片2的上表面21，其连接的芯片焊盘22为接地焊盘，从而能够将静电导出到芯片封装结构的外部。
本实施例中，导电体至塑封体4的上表面41的最短距离为金属块的上表面距离塑封体4的上表面41的距离，打线至塑封体4的上表面41的最短距离为打线的弧线最高点至塑封体4的上表面41的距离，金属块的上表面距离塑封体4的上表面41的距离小于打线的弧线最高点至塑封体4的上表面41的 距离；亦即，金属块的上表面与芯片2的上表面21所在平面的距离大于打线的弧线最高点与芯片2的上表面21所在平面的距离。以图5A中的芯片封装结构为例，金属块31的上表面32距离塑封体4的上表面41的距离小于电气焊线601的弧线最高点611距离上表面41的距离，金属块31的上表面32与芯片2的上表面21所在平面的距离大于电气焊线601的弧线最高点611与芯片2的上表面21所在平面的距离。
较佳的，打线的弧线最高点至塑封体4的上表面41的距离和金属块的上表面距离塑封体4的上表面41的距离的差值大于或等于10微米。以图5A中的芯片封装结构为例，电气焊线601的弧线最高点611距离上表面41的距离与金属块31的上表面32距离塑封体4的上表面41的距离的差值大于或等于10微米，以更好的导出静电。
需要说明的是，图5A、图5B中只是示意性描述金属块的形状、数目以及位置，然本实施例对此不作任何限制。
本申请第五实施例涉及一种芯片封装结构，本实施例是在第四实施例基础上的改进，主要改进之处在于：请参考图6，导电体(金属块)的第二端裸露于塑封体的上表面。
本实施例中，金属块的上表面越接近塑封体4的上表面41，其导出静电的效果越好。较佳的，金属块的第一端连接于外部焊盘12，金属块的第二端裸露于塑封体4的上表面41。请参考图6，为在图5A的芯片封装结构(以图5A的芯片封装结构为例，然不以此为限)的基础上对塑封体4的上表面41进行打磨，以使金属块31的上表面32与塑封体4的上表面41的处于同一个平面，在静电达到塑封体4的上表面41时(尚未进入塑封体)，能够迅速由金属块31 的上表面32进入金属块31，继而从金属块31连接的外部焊盘12被导出芯片封装。
本实施例相对于第四实施例而言，设置金属块的第二端裸露于塑封体的上表面，以在静电达到塑封体的上表面时(尚未进入塑封体)，能够迅速由金属块的第二端进入金属块，继而从金属块连接的外部焊盘被导出芯片封装结构。
本申请第六实施例涉及一种电子设备，例如为手机、平板电脑等。电子设备包括至少一个第一实施例至第五实施例中任一所述的芯片封装结构。
本实施例相对于现有技术而言，在塑封体内设置连接于支撑体的外部焊盘或芯片焊盘中的接地焊盘的导电体，且导电体至塑封体的上表面的最短距离小于打线至塑封体的上表面的最短距离；即导电体较芯片、打线相比，更接近塑封体的上表面，使得静电达到塑封体的上表面并进入塑封体后首先接触到导电体，并通过导电体从外部焊盘或接地焊盘导出芯片封装结构，在基本不增加芯片封装的成本基础上，大幅减少静电释放导致的芯片失效问题。
本申请第七实施例涉及一种芯片封装方法，应用于对芯片进行封装，芯片的封装形式可以为QFN(Quad Flat No-lead Package，方形扁平无引脚封装)、QFP(Plastic Quad Flat Package，方型扁平式封装)、LGA(Land Grid Array，栅格阵列封装)、BGA(Ball Grid Array，焊球阵列封装)等，然本实施例对此不作任何限制。
本实施例的芯片封装方法的具体流程如图7所示。
步骤101，将芯片设置于支撑体的上表面，并通过打线将芯片的上表面的芯片焊盘连接至支撑体的外部焊盘。
具体而言，通过粘接胶将芯片粘接在支撑体的上表面，请参考图1，以支 撑体为引线框架为例，其包括框架主体11以及多个外部焊盘12，框架主体11上也设有多个外部焊盘12，芯片2通过粘接胶层5固定于框架主体11，并通过打线将芯片2的上表面21的芯片焊盘22连接至支撑体的外部焊盘12；因此，打线的弧线最高点高于芯片2的上表面21所在平面，即，电气焊线601的弧线最高点611高于芯片2的上表面21所在平面。
步骤102，将至少一导电体连接于外部焊盘或芯片焊盘中的接地焊盘。
具体而言，导电体可以为金属线或金属块，在焊接时，需使得导电体与支撑体的最大距离大于打线与支撑体的最大距离，即，使导电体与芯片的上表面所在平面的最大距离大于打线的弧线最高点与芯片的上表面所在平面的最大距离。
导电体为金属线时，金属线的第一端连接于外部焊盘或芯片焊盘中的接地焊盘，金属线的第二端连接于外部焊盘。导电体至塑封体4的上表面41的最短距离为金属线的弧线最高点至塑封体4的上表面41的距离，打线至塑封体4的上表面41的最短距离为打线的弧线最高点至塑封体4的上表面41的距离，金属线的弧线最高点至塑封体4的上表面41的距离小于打线的弧线最高点至塑封体4的上表面41的距离；亦即，导电体与芯片2的上表面21的最大距离大于打线与芯片2的上表面21的最大距离。请参考图1，以金属线301为例，金属线301的弧线最高点311距离引线框架11的距离大于电气焊线601的弧线最高点611距离引线框架11的距离；即，金属线301的弧线最高点311与芯片2的上表面21所在平面的距离大于电气焊线601的弧线最高点611与芯片2的上表面21所在平面的距离。其中，金属线的直径可以大于或等于0.5密耳。
导电体为金属块时，金属块连接于支撑体的外部焊盘或芯片焊盘中的接 地焊盘。以图5A的芯片封装结构为例(然不以此为限)，金属块连接于支撑体的外部焊盘；导电体至塑封体4的上表面41的最短距离为金属块31的上表面32距离塑封体4的上表面41的距离，打线至塑封体4的上表面41的最短距离为打线的弧线最高点至塑封体4的上表面41的距离，金属块31的上表面32距离塑封体4的上表面41的距离小于打线的弧线最高点至塑封体4的上表面41的距离；亦即，金属块31的上表面32与芯片2的上表面21所在平面的距离大于打线的弧线最高点与芯片2的上表面21所在平面的距离。请参考图5A，金属块31的上表面32距离引线框架11的距离大于电气焊线601的弧线最高点611距离引线框架11的距离，即，金属块31的上表面32与芯片2的上表面21所在平面的距离大于电气焊线601的弧线最高点611与芯片2的上表面21所在平面的距离。
步骤103，对支撑体、芯片、导电体进行封装，并形成塑封体。
具体而言，在经过步骤101与步骤102后，将支撑体放入模具中，并注入塑封胶，在塑封胶固化后形成塑封体，塑封体的具体结构请参考图1。其中，由于在步骤102中焊接时导电体与支撑体的最大距离大于打线与支撑体的最大距离，因此，形成的塑封体中，导电体至塑封体的上表面的最短距离小于打线至塑封体的上表面的最短距离。较佳的，在步骤102焊接时，使得导电体与支撑体的最大距离与打线与支撑体的最大距离的差值大于或等于10微米，从而使得塑封体中，打线至塑封体4的上表面41的最短距离和导电体至塑封体4的上表面41的最短距离的差值大于或等于10微米，以更好的导出静电。
由于第一实施例、第四实施例与本实施例相互对应，因此本实施例可与第一实施例、第四实施例互相配合实施。第一实施例、第四实施例中提到的相 关技术细节在本实施例中依然有效，在第一实施例、第四实施例中所能达到的技术效果在本实施例中也同样可以实现，为了减少重复，这里不再赘述。相应地，本实施例中提到的相关技术细节也可应用在第一实施例、第四实施例中。
本实施例中，相对于现有技术增加的导电体为金属线或金属块，都是现有的材料，并且不会对封装工艺有影响，因此，实际增加的成本只有百分之一不到，具有较好的经济效益。
本实施例相对于现有技术而言，在塑封体内设置连接于支撑体的外部焊盘或芯片焊盘中的接地焊盘的导电体，且导电体至塑封体的上表面的最短距离小于打线至塑封体的上表面的最短距离；即导电体较芯片、打线相比，更接近塑封体的上表面，使得静电达到塑封体的上表面并进入塑封体后首先接触到导电体，并通过导电体从外部焊盘或接地焊盘导出芯片封装结构，在基本不增加芯片封装的成本基础上，大幅减少静电释放导致的芯片失效问题。
本申请第八实施例涉及一种芯片封装方法，本实施例是在第七实施例基础上的改进，主要改进之处在于：本实施例中，在形成塑封体后，对塑封体的上表面进行处理，使得导电体的第二端裸露于塑封体的上表面。
本实施例的芯片封装方法的具体流程如图8所示。
其中，步骤201至步骤203与步骤101至步骤103大致相同，主要不同之处在于，本实施例中增加了步骤204，具体如下：
步骤204，对塑封体的上表面进行处理，以裸露出导电体。
具体而言，在形成塑封体后，对塑封体的上表面进行适当的打磨处理，以使导电体的第二端裸露于塑封体的上表面。
请参考图3，导电体为金属线，为在图1的芯片封装结构的基础上进行 打磨，使得金属线301、金属线302以及金属线303被磨断，从而裸露在封装体4的上表面41。
请参考图6，导电体为金属块，为在图5A的芯片封装结构(以图5A的芯片封装结构为例，然不以此为限)的基础上对塑封体4的上表面41进行打磨，以使金属块31的上表面32与塑封体4的上表面41的处于同一个平面，然不限于此，也可以直接在步骤102(本实施例中步骤202)将至少一导电体连接于外部焊盘或芯片焊盘中的接地焊盘时，使得金属块31的上表面与塑封体4的上表面41的处于同一个平面，然本实施例对此不作任何限制。
由于第二实施例、第五实施例与本实施例相互对应，因此本实施例可与第二实施例、第五实施例互相配合实施。第二实施例、第五实施例中提到的相关技术细节在本实施例中依然有效，在第二实施例、第五实施例中所能达到的技术效果在本实施例中也同样可以实现，为了减少重复，这里不再赘述。相应地，本实施例中提到的相关技术细节也可应用在第二实施例、第五实施例中。
本实施例相对于第七实施例而言，设置导电体的第二端裸露于塑封体的上表面，以在静电达到塑封体的上表面时(尚未进入塑封体)，能够迅速由导电体的第二端进入导电体以被导出。
本申请第九实施例涉及一种芯片封装方法，本实施例是在第七实施例基础上的改进，主要改进之处在于：在导电体为金属线时，在塑封过程中，使得金属线与塑封体的上表面相切。
本实施例的芯片封装方法的具体流程如图9所示。
步骤301，将芯片设置于支撑体的上表面，并通过打线将芯片的上表面的芯片焊盘连接至支撑体的外部焊盘。
具体而言，与第七实施例中的步骤101大致相同，在此不再赘述。
步骤302，将金属线的第一端连接于外部焊盘或芯片焊盘中的接地焊盘，将金属线的第二端连接于外部焊盘。
具体而言，请参考图1，以金属线302为例，金属线302连接于外部焊盘12与芯片焊盘22中的接地焊盘。较佳的，请参考图2，当金属线连接于任意两个外部焊盘12之间时，设置为：金属线横跨芯片2的上表面21。图中金属线303、金属线304均横跨芯片2的上表面21，不同之处在于两者投影在芯片2的上表面21的位置和长度均不同，即金属线303的投影区域较长且从一条边延伸至与该条边相对的另一条边；金属线304的投影区域较短且位于芯片2的上表面21的一个边角处。其中，当金属线横跨芯片2的上表面21时，金属线的最高点位于芯片2的上表面21的正上方区域之内、或较未横跨芯片2的上表面21的金属线(例如，金属线301)来说更接近芯片2的上表面21的正上方区域；例如，金属线303的最高点位于芯片2的上表面21的正上方区域之内；金属线301的最高点与金属线304的最高点均位于芯片2的上表面21的正上方区域之外，但是金属线304的最高点较金属线301的最高点更接近芯片2的上表面21的正上方区域。当静电从芯片2的上表面21的正上方区域(即塑封体4的上表面41对应于芯片2的上表面21的区域)进入塑封体4内时，静电到达横跨芯片2的上表面21的金属线(例如金属线303、金属线304)的最高点的路径，相对于到达未横跨芯片2的上表面21的金属线(例如，金属线301)的最高点的路径而言，会相对近一点，从而可以更快更有效地导出静电，减小了静电达到芯片2的上表面21损坏芯片2的机率(静电到达金属线的最高点的路径越长，失误的概率越大)。
步骤303，在塑封过程中，对塑封体的上表面进行压缩，以使得金属线与塑封体的上表面相切。
具体而言，在将支撑体放入模具中，并注入塑封胶后，利用模具对尚未固化的塑封胶进行压缩，从而使得金属线与塑封体的上表面相切。金属线的弧线最高点越接近塑封体4的上表面41，其导出静电的效果越好，本实施例中设置金属线与塑封体4的上表面41相切。请参考图4，金属线301、金属线302以及金属线303均与塑封体4的上表面41相切，然不限于此，也可以是其中部分金属线与塑封体4的上表面41相切，本实施例对此不做任何限制。
由于第三实施例与本实施例相互对应，因此本实施例可与第三实施例互相配合实施。第三实施例中提到的相关技术细节在本实施例中依然有效，在第三实施例中所能达到的技术效果在本实施例中也同样可以实现，为了减少重复，这里不再赘述。相应地，本实施例中提到的相关技术细节也可应用在第三实施例中。
本实施例相对于第七实施例而言，提供了金属线的另一种具体设置方式，金属线与塑封体的上表面相切，即金属线与塑封体的上表面的距离很小，从而能使得静电在到达塑封体的上表面并在刚进入塑封体时，迅速由金属线上与塑封体的上表面相切位置进入金属线以被导出。
本领域的普通技术人员可以理解，上述各实施例是实现本申请的具体实施例，而在实际应用中，可以在形式上和细节上对其作各种改变，而不偏离本申请的精神和范围。

Claims (17)

  1. 一种芯片封装结构，其特征在于，包括：支撑体、芯片、至少一导电体以及用于塑封所述支撑体、所述芯片、所述导电体的塑封体；
    所述芯片设置于所述支撑体的上表面，所述芯片的上表面形成有芯片焊盘，且所述芯片焊盘通过打线连接至所述支撑体的外部焊盘；
    所述导电体连接于所述外部焊盘或所述芯片焊盘中的接地焊盘，且所述导电体至所述塑封体的上表面的最短距离小于所述打线至所述塑封体的上表面的最短距离。
  2. 如权利要求1所述的芯片封装结构，其特征在于，所述导电体的第一端连接于所述外部焊盘或所述芯片焊盘中的接地焊盘，所述导电体的第二端裸露于所述塑封体的上表面。
  3. 如权利要求1所述的芯片封装结构，其特征在于，所述导电体为金属线，所述金属线的第一端连接于所述外部焊盘或所述芯片焊盘中的接地焊盘，所述金属线的第二端连接于所述外部焊盘。
  4. 如权利要求3所述的芯片封装结构，其特征在于，所述金属线的第一端连接于所述外部焊盘，且所述金属线的一部分投影在所述芯片的上表面。
  5. 如权利要求3所述的芯片封装结构，其特征在于，所述金属线与所述塑封体的上表面相切。
  6. 如权利要求3-5任一项所述的芯片封装结构，其特征在于，所述金属线的直径大于或等于0.5密耳。
  7. 如权利要求1所述的芯片封装结构，其特征在于，所述打线至所述塑封体的上表面的最短距离和所述导电体至所述塑封体的上表面的最短距离的差值大于或等于10微米。
  8. 如权利要求1或2所述的芯片封装结构，其特征在于，所述导电体为金属线或金属块。
  9. 一种电子设备，其特征在于，包括至少一个如权利要求1至8中任一项所述的芯片封装结构。
  10. 一种芯片封装方法，其特征在于，包括：
    将芯片设置于支撑体的上表面，并通过打线将所述芯片的上表面的芯片焊盘连接至所述支撑体的外部焊盘；
    将至少一导电体连接于所述外部焊盘或所述芯片焊盘中的接地焊盘，且所述导电体与所述支撑体的最大距离大于所述打线与所述支撑体的最大距离；
    对所述支撑体、所述芯片、所述导电体进行封装，并形成塑封体；其中，所述导电体至所述塑封体的上表面的最短距离小于所述打线至所述塑封体的上表面的最短距离。
  11. 如权利要求10所述的芯片封装方法，其特征在于，在所述对所述支撑体、所述芯片、所述导电体进行封装，并形成塑封体之后，还包括：
    对所述塑封体的上表面进行处理，以裸露出所述导电体。
  12. 如权利要求10所述的芯片封装方法，其特征在于，所述导电体为金属线，所述将至少一导电体的至少一端连接于所述外部焊盘或所述芯片焊盘中的接地焊盘，具体包括：
    将所述金属线的第一端连接于所述外部焊盘或所述芯片焊盘中的接地焊盘，将所述金属线的第二端连接于所述外部焊盘。
  13. 如权利要求12所述的芯片封装方法，其特征在于，所述对所述支撑体、所述芯片、所述导电体进行封装，并形成塑封体，具体包括：
    在塑封过程中，对所述塑封体的上表面进行压缩，以使得所述金属线与所述塑封体的上表面相切。
  14. 如权利要求12所述的芯片封装方法，其特征在于，所述金属线的第一端连接于所述外部焊盘，且所述金属线的一部分投影在所述芯片的上表面。
  15. 如权利要求12所述的芯片封装方法，其特征在于，所述金属线的直径大于或等于0.5密耳。
  16. 如权利要求10所述的芯片封装方法，其特征在于，所述打线至所述塑封体的上表面的最短距离和所述导电体至所述塑封体的上表面的最短距离的差值大于或等于10微米。
  17. 如权利要求10或11所述的芯片封装方法，其特征在于，所述导电体为金属线或金属块。
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