TWI307546B - Semiconductor package and fabrication method thereof - Google Patents

Semiconductor package and fabrication method thereof Download PDF

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Publication number
TWI307546B
TWI307546B TW95134271A TW95134271A TWI307546B TW I307546 B TWI307546 B TW I307546B TW 95134271 A TW95134271 A TW 95134271A TW 95134271 A TW95134271 A TW 95134271A TW I307546 B TWI307546 B TW I307546B
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Taiwan
Prior art keywords
semiconductor package
package structure
lead frame
carrier
memory card
Prior art date
Application number
TW95134271A
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Chinese (zh)
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TW200814248A (en
Inventor
En Min Jow
Original Assignee
En Min Jow
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Publication date
Application filed by En Min Jow filed Critical En Min Jow
Priority to TW95134271A priority Critical patent/TWI307546B/en
Priority to US11/592,214 priority patent/US20080067641A1/en
Priority to JP2007002514A priority patent/JP2008072077A/en
Publication of TW200814248A publication Critical patent/TW200814248A/en
Application granted granted Critical
Publication of TWI307546B publication Critical patent/TWI307546B/en

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item

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  • Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
  • Encapsulation Of And Coatings For Semiconductor Or Solid State Devices (AREA)

Description

1307546 九、發明說明： 【發明所屬之技術領域】 本發明係有關一種半導體封裝結構及其製法，特別是一種 具有凹槽之半導體封裝結構及其製法。 【先前技術】1307546 IX. Description of the Invention: [Technical Field] The present invention relates to a semiconductor package structure and a method of fabricating the same, and more particularly to a semiconductor package structure having a recess and a method of fabricating the same. [Prior Art]

一般產業界半導體封裝的方式如薄型小尺寸封裝（TSOP) 型式、微型小尺寸封裝(MSOP)及1/4小尺寸封裝（QSOP)等封 裝技術常應用於消費性電子產品内之記憶裝置或製成記憶卡 等’如第1圖所示為習知具記憶功能的封裝體之結構剖視圖， 導線架100依序裝設控制元件（controller comp〇nent)200、快閃 記憶晶片（flash memory)300及被動元件400元件，再利用封膠 體500密封形成單一之封裝體，封裝體最後經由電性測試，分 類良品及不良品。 上述之封裝體因密封成一體成型之結構，封膠體將控制元 件200、快閃記憶晶片300及被動元件400包覆在—起，再進 行電性測試，一方面，封裝過程中無法瞭解先行得知各Ic元 件或製程所造成電性不良的原因，而只能於封裝完後進行電性 測試’若電性測試為不㈣各1c元件及其封裝材料必二要報 廢造成生產成本及時間的增加；另一方面，在檢驗電性不良的 封裝體時’因封職之封裝體，不易檢視得知封裝體内部^性 ’進而造成良率無法提高’因此如何克服上述問題 疋目前業界所急迫需要的。 【發明内容】 係利用封膠體於封 入被動元件時，封 為了解決上述問題，本發明目的之一， 膠時形成凹槽用於置人被動元件，且於未置 1307546 ' 裝體前可先行電性測試後再決定是否置入被動元件，避免電性 - 不良之封裝體置入被動元件。 本發明之又一目的係利用封裝膠體在塑封晶片時形成凹 槽，用以檢視所置入被動元件的連接狀況。 為了達到上述目的，本發明提供一種半導體封裝結構，包 - 含一導線架，其係為複數個内引腳、複數個外引腳及至少一承 載座所組成；至少一晶片，其係設置於導線架之承載座並電性 連接導線架；至少一控制元件，其係設置於導線架之承載座並 電性連接導線架；至少一凹槽，設置於封膠體下方任一位置並 _ 凹入至承載座表面；及至少一被動元件，設置凹槽内並連接每 一内引腳及複數個外引腳。 為了達到上述目的，本發明提供一種半導體封裝製法，其 係提供一導線架、至少一快閃記憶晶片及至少一控制元件連接 於導線架之一承載區上；提供一封膠體包覆導線架之複數個内 引腳、承載區、快閃記憶晶片及控制元件而封膠體不包覆導線 架之複數個外引腳並於封膠體形成至少一凹槽，及提供被動元 件於凹槽内並電性連接導線架。 • 係利用下列步驟製成底下藉由具體實施例配合所附的圖 式詳加說明，當更容易瞭解本創作之目的、技術内容、特點及 其所達成之功效。 【實施方式】 第2圖所示為依據本發明一實施例具凹槽之封裝體剖視 圖。於本實施例中，封裝體10具有導線架20、控制元件30 及快閃記憶晶片40，其中導線架20係由多個内引腳22、外引 腳24及承載座26所組成，且控制元件30及快閃記憶晶片40 1307546 設置於承載座26。封裝體10塗佈封膠體50,並包覆控制元件 30、快閃記憶晶片40、内引腳22及承載座26，而外引腳24 則不被封膠體50所包覆並露出封膠體50外。又，封膠體50 具有未封膠之區域形成凹槽60,並且凹槽60設置於封膠體50 任一位置，此外封膠體50之凹槽60曝露出部分導線架20表 面，用於置入被動元件70並且被動元件70與導線架20電性 連接；承載座26設置多個引線80分別電性連接内引腳22、 該快閃記憶晶片40及該控制元件30。上述封膠體50之材質 係由環氧樹脂（epoxy)為主要構成材料而導線架20係由金屬所 製成。 又，如第3圖所示為依據本發明之另一實施例，說明封裝 體10上方及下方分別對稱設置凹槽60及62以便於檢視凹槽 60内的被動元件70與導線架20連接狀態。根據上述實施例 之精神，封裝體10之凹槽60及62依據電路設計的需求，設 置於封裝體10上方及下方任一位置並於凹槽60安裝被動元件 70。本發明之封裝體10適用於數位相機(DC)、個人數位助理 (PDA)或行動電話等各類電子產品之儲存媒介或加工製成安全 數位（SD)電子記憶卡、多媒體(MMC)電子記憶卡、壓縮快閃（CF) 電子記憶卡、記憶體條(MS)電子記憶卡、智慧媒體（SM)電子 記憶卡、尖端數位(XD)電子記憶卡、迷你多媒體(RS-MMC)電 子記憶卡、迷你安全數位（mini-SD)電子記憶卡及迷你快閃 (Trans Flash)電子記憶卡。 第4A圖及第4B圖所示為依據本發明具凹槽之封裝步驟 流程圖。如第4A圖所示，首先提供導線架20，並於導線架 20上方依序設置控制元件30及快閃記憶晶片40並利用打線 方式分別將引線80 —端電性連接内引腳22、控制元件30及 快閃記憶晶片40而另一端連接承載座26。 1307546 接續上述，如第4B圖所示，利用封膠模具進行封膠製程 使封膠體50包覆導線架20之快閃記憶晶片40及控制元件 30，其中封膠模具為上模92及下模94之結構，並分別於上模 92及下模94結構分別設置凸塊96及98,當進行封膠製程時， 凸塊96及98會分別抵觸導線架20上方及下方，致使封膠時 產生夾持作用，防止封膠體50完全包覆，該封膠體灌入於該 模具内後形成凹槽60及62，接著再置入被動元件70於凹槽 60中並電性連接導線架20，即完成如第3圖所示之封裝體結 構。依據本發明實施例之精神，上模92或下模94設置單一凸 塊96於封膠時形成凹槽60再置入被動元件70,即完成如第2 圖所示之封裝體結構。 根據上述之實施例，完成之封裝體10經由電性測試，若 其測試結果為電性不正常，可以將封裝體10先行報廢，避免 習知技術之封裝體將控制元件、閃光記憶晶片及被動元件整體 封裝後再作電性測試，如此可先行將不正常的封裝體報廢減少 不必要的加工時間及節省材料之成本支出；另一方面，本發明 之凹槽60及62係可利用一蓋板（圖中未示）於凹槽60及62 上可防止微塵（particle)直接掉落於凹槽60及62内，造成封裝 體10電性不良之疑慮。 綜合上述，本發明提出一種半導體封裝結構及其製法，係 利用封膠體時形成凹槽用於置入被動元件，且於未置入被動元 件時，封裝體前可先行電性測試後再將通過電性測試之封裝體 置入被動元件，因此防止不良品置入被動元件且凹槽内之被動 元件的連接狀況，便於分析造成不良品之原因。 以上所述之實施例僅係為說明本發明之技術思想及特 點，其目的在使熟習此項技藝之人士能夠瞭解本發明之内容並 據以實施，當不能以之限定本發明之專利範圍，即大凡依本發 1307546 明所揭示之精神所作之均等變化或修飾，仍應涵蓋在本發明之 專利範圍内。 【圖式簡單說明】 第1圖所示為習知具記憶功能的封裝體之結構剖視圖。 第2圖所示為依據本發明一實施例具凹槽結構之封裝體的剖 視圖。 第3圖所示為根據本發明另一實施例具凹槽結構之封裝體的 剖視圖。 第4A圖及第4B圖所示為依據本發明具凹槽之封裝步驟流程 圖。 【主要元件符號說明】 100 導線架 200 控制元件 300 快閃記憶晶片 400 被動元件 500 封膠體 10 封裝體 20 導線架 22 内引腳 24 外引腳 26 承載座 1307546 30 控制元件 40 快閃記憶 50 封膠體 60、62 凹槽 70 被動元件 80 引線 92 上模 94 下模 96、98 凸塊General industrial semiconductor packaging methods such as thin small package (TSOP) type, micro small size package (MSOP) and 1/4 small package (QSOP) are commonly used in memory devices or systems in consumer electronics. As a memory card, etc., as shown in FIG. 1 is a structural cross-sectional view of a conventional memory function package, the lead frame 100 is sequentially provided with a control component (controller comp〇nent) 200 and a flash memory 300 (flash memory). And the passive component 400 component is sealed by the encapsulant 500 to form a single package, and the package is finally classified into a good product and a defective product through electrical testing. The above-mentioned package is sealed into an integrally formed structure, and the encapsulant encapsulates the control element 200, the flash memory chip 300 and the passive component 400, and then performs electrical testing. On the one hand, the package process cannot be understood first. Know the cause of electrical defects caused by Ic components or processes, and only perform electrical testing after packaging. If the electrical test is not (4) each 1c component and its packaging materials must be scrapped to cause production cost and time. On the other hand, when testing the poorly-performing package, it is difficult to check the internality of the package due to the sealed package, which leads to the failure to improve the yield. Therefore, how to overcome the above problems is urgent in the industry. needs. SUMMARY OF THE INVENTION In order to solve the above problems when sealing a passive component by a sealant, one of the objects of the present invention is to form a groove for placing a passive component during the glue, and to perform power before the 1307546' body is installed. After the sex test, it is decided whether to place the passive component to avoid the electrical-poor package being placed into the passive component. Still another object of the present invention is to form a recess in the molding of the wafer by means of the encapsulant for viewing the connection state of the passive component placed. In order to achieve the above object, the present invention provides a semiconductor package structure comprising: a lead frame comprising a plurality of inner leads, a plurality of outer leads and at least one carrier; at least one chip disposed on The carrier of the lead frame is electrically connected to the lead frame; at least one control component is disposed on the carrier of the lead frame and electrically connected to the lead frame; at least one groove is disposed at any position below the sealing body and is recessed To the surface of the carrier; and at least one passive component, the recess is disposed and each inner pin and the plurality of outer pins are connected. In order to achieve the above object, the present invention provides a semiconductor package manufacturing method, which provides a lead frame, at least one flash memory chip, and at least one control element connected to one of the lead frames of the lead frame; and provides a gel coated lead frame a plurality of inner pins, a carrying area, a flash memory chip and a control component, and the sealing body does not cover the plurality of outer leads of the lead frame and forms at least one groove in the sealing body, and provides a passive component in the groove and is electrically Sexual connection lead frame. • Use the following steps to make a detailed description of the specific examples and the accompanying drawings, so that it is easier to understand the purpose, technical content, features and effects of the creation. [Embodiment] Fig. 2 is a cross-sectional view showing a package having a groove according to an embodiment of the present invention. In this embodiment, the package 10 has a lead frame 20, a control element 30, and a flash memory chip 40. The lead frame 20 is composed of a plurality of inner leads 22, outer leads 24 and a carrier 26, and is controlled. The component 30 and the flash memory chip 40 1307546 are disposed on the carrier 26. The package 10 is coated with the encapsulant 50 and covers the control element 30, the flash memory chip 40, the inner lead 22 and the carrier 26, while the outer lead 24 is not covered by the encapsulant 50 and exposes the encapsulant 50. outer. Moreover, the encapsulant 50 has an unsealed region to form a recess 60, and the recess 60 is disposed at any position of the encapsulant 50, and the recess 60 of the encapsulant 50 exposes a portion of the lead frame 20 for passive insertion. The component 70 and the passive component 70 are electrically connected to the lead frame 20; the carrier 26 is provided with a plurality of leads 80 electrically connected to the inner lead 22, the flash memory chip 40 and the control element 30, respectively. The material of the above-mentioned sealant 50 is made of epoxy as a main constituent material and the lead frame 20 is made of metal. Moreover, as shown in FIG. 3, in accordance with another embodiment of the present invention, the recesses 60 and 62 are symmetrically disposed above and below the package body 10 to facilitate the connection of the passive component 70 and the lead frame 20 in the viewing recess 60. . According to the spirit of the above embodiment, the recesses 60 and 62 of the package 10 are disposed at any position above and below the package 10 and the passive component 70 is mounted in the recess 60 according to the requirements of the circuit design. The package 10 of the present invention is suitable for storage media of various electronic products such as a digital camera (DC), a personal digital assistant (PDA) or a mobile phone, or processed into a secure digital (SD) electronic memory card, multimedia (MMC) electronic memory. Card, compressed flash (CF) electronic memory card, memory stick (MS) electronic memory card, smart media (SM) electronic memory card, sophisticated digital (XD) electronic memory card, mini multimedia (RS-MMC) electronic memory card , mini secure digital (mini-SD) electronic memory card and mini flash (Trans Flash) electronic memory card. 4A and 4B are flow charts showing the steps of encapsulating a groove in accordance with the present invention. As shown in FIG. 4A, the lead frame 20 is first provided, and the control element 30 and the flash memory chip 40 are sequentially disposed above the lead frame 20, and the lead 80 is electrically connected to the inner lead 22 by a wire bonding method, and the control is respectively controlled. The component 30 and the flash memory chip 40 are connected to the carrier 26 at the other end. 1307546 Continuing the above, as shown in FIG. 4B, the sealing process is performed by the sealing mold, so that the sealing body 50 covers the flash memory chip 40 and the control element 30 of the lead frame 20, wherein the sealing mold is the upper mold 92 and the lower mold. The structure of 94, and the protrusions 96 and 98 are respectively arranged on the upper mold 92 and the lower mold 94. When the sealing process is performed, the bumps 96 and 98 respectively abut the upper and lower sides of the lead frame 20, so that the sealing is generated. The clamping action prevents the sealing body 50 from being completely covered. After the sealing body is poured into the mold, the grooves 60 and 62 are formed, and then the passive component 70 is placed in the groove 60 and electrically connected to the lead frame 20, that is, Complete the package structure as shown in Figure 3. According to the spirit of the embodiment of the present invention, the upper mold 92 or the lower mold 94 is provided with a single protrusion 96 to form a recess 60 in the sealing and then placed in the passive component 70, that is, the package structure as shown in FIG. 2 is completed. According to the above embodiment, the completed package 10 is electrically tested. If the test result is electrically abnormal, the package 10 can be scrapped first, so that the package of the prior art can avoid the control element, the flash memory chip and the passive. After the components are packaged as a whole, the electrical test is performed, so that the abnormal package can be scrapped first to reduce unnecessary processing time and save the cost of materials; on the other hand, the grooves 60 and 62 of the present invention can utilize a cover. The plates (not shown) on the grooves 60 and 62 prevent the particles from falling directly into the grooves 60 and 62, causing the electrical defects of the package 10 to be unreasonable. In summary, the present invention provides a semiconductor package structure and a method for fabricating the same, which is formed by forming a recess for inserting a passive component when the sealant is used, and when the passive component is not inserted, the package can be passed before the electrical test and then passed. The package of the electrical test is placed in the passive component, thereby preventing the defective component from being placed into the passive component and the connection state of the passive component in the groove, thereby facilitating analysis of the cause of the defective product. The embodiments described above are merely illustrative of the technical spirit and the features of the present invention, and the objects of the present invention can be understood by those skilled in the art, and the scope of the present invention cannot be limited thereto. Equivalent changes or modifications made by the spirit of the present disclosure are still to be included in the scope of the present invention. BRIEF DESCRIPTION OF THE DRAWINGS Fig. 1 is a cross-sectional view showing the structure of a conventional package having a memory function. Fig. 2 is a cross-sectional view showing a package having a groove structure according to an embodiment of the present invention. Fig. 3 is a cross-sectional view showing a package having a groove structure according to another embodiment of the present invention. 4A and 4B are flow diagrams showing the packaging steps of the groove according to the present invention. [Main component symbol description] 100 lead frame 200 control element 300 flash memory chip 400 passive component 500 encapsulant 10 package 20 lead frame 22 inner pin 24 outer pin 26 carrier 1307546 30 control element 40 flash memory 50 Colloid 60, 62 Groove 70 Passive component 80 Lead 92 Upper die 94 Lower die 96, 98 Bump

Claims (1)

1307546 十、申請專利範圍： 1.一種半導體封裝結構，包含： 導線木，其係由複數個内引腳、複數個外引腳及至少 所 組成； 至乂晶片，其係設置於該導線架之該承載座； ^少一控制元件’其係、設置於該導線架之該承載座； 封膠體，其係包覆於該導線架、該晶片、該内引腳及該控制元件； 至乂凹槽’ 5史置於5亥封膠體任一位置並曝露出部分該導線架表 面；及 至少—被動元件，設置於該凹槽内之該導線架表面且該被動元件電 性連接該導線架。 2.如凊求項1所述之半導體封裝結構，其中該晶片係為快閃記憶晶 片。 3·如請求項1所述之半導體封裝結構，其中該封裝膠體係由環氧樹 脂所構成。 4. 如明求項1所述之半導體封裝結構，其中該導線架係由金屬材質 所構成。 5. 如請求項丨所述之半導體封裝結構，其中該些外引腳露出該封膠 I 體外。 6. 如請求項1所述之半導體封I結構，其中該承載座設置複數 個引線分別電性連接該些内弓丨腳、該晶片及該控制元件。 7_如請求項1所述之半導體封裝結構，其中該半導體封裝結構 適用於一電子產品之一儲存媒介，該電子產品之該儲存媒介包 含數位相機(DC)、個人數位助理（PDA)及行動電話。 8_如請求項1所述之半導體封裝結構，該半導體封裝結構適用 於一電子記憶卡，該電子記憶卡包含安全數位(SD)電子記憶卡、多 媒體(MMC)電子記憶卡、壓縮快閃(cf)電子記憶卡、記憶體條(Ms)電 子3己憶卡、智慧媒體(SM)電子記憶卡、尖端數位(X]))電子記憶卡、迷 11 1307546 你多媒體(RS-MMC)電子記憶卡、迷你安全數位電子記憶卡及 迷你快閃(Trans Flash)電子記憶卡。 9.一種半導體封裝結構，包含： 一導線架，其係由複數個内引腳、複數個外引腳及至少一承載座所 組成； 至少一晶片’其係設置於該導線架之該承載座； 至少一控制元件，其係設置於該導線架之該承載座； 一封膠體，其係包覆於該承載座、該些内引腳、該晶片及該控制元 件； 複數個凹槽，分別對稱設置於該封膠體上方及下方任一位置並曝露 出部分該導線架表面；及 至少一被動元件，設置於該些凹槽内之該導線架表面且該被動元件 電性連接該導線架。 10·如請求項9所述之半導體封裝結構’其中該晶片係為快閃記憶 晶片。 11·如叫求項9所述之半導體封裝結構，其中該封裝膠體係由環氧 樹脂所構成。 12.如請求項9所述之半導體封裝結構，其中該導線架係由金屬材 質所構成。 13·如請求項9所述之半導體封裝結構，其中該些外弓丨聊露出該封膠 14·如請求項9所述之半導體封裝結構，其中該承栽座設置複彰 個引線分別電性連接該些内引腳、該晶片及該控制元件。 15::求項9所述之半導體封裝結構’其中該半導體封裝結招 2於1子產品之-儲存媒介，該電子產品之該儲存媒介自 3數位相機（DC)、個人數位助理（pDA)及行動電話。 16·如請求項9所述之半導體封裝結構，如請求項丨 體封裴結構，其中該半導體封裝結構適用於—電子產^之一倍 12 1307546 =介’《子產k該儲存媒介包含數位相 位助理（PDA)及行動電話。 個人數 Π.-種半導體封裝方法，其步驟包含： 提供一導線架； 供至少—快閃記憶晶片及至少—控制元件連接於該導線架之—承 曰以-封膠體包覆該導_之複數_⑽、該承賴、該快閃 晶片及該控制疋件並於該封膠體形成至少一凹槽；及 ‘·、 设置糧動7L件於該凹槽内之該導線架並電性連接該導線架。 18.如請求項Π所述之半導體封裝結構，其中包龍導線架之 載區、該些内引腳、該快閃記憶晶片及該控制耕之前，利用^ 將複數個引線-端分別電性連接該些内引腳、該控制元件ς 快閃記憶晶片而另一端連接該承載座。 Λ 力f求項17所述之半導體封裝結構，其中利用—模具包覆該 ¥、-泉狀該承載區 '該些内引腳、該快閃記憶晶片及該 膠體灌入於顧具内。 T ^ 月求項19所述之半導體封裝結構，其中該模具設置至少一 凸塊，用於成型該封膠體之該凹槽。1307546 X. Patent application scope: 1. A semiconductor package structure comprising: a wire wood, which is composed of a plurality of inner pins, a plurality of outer pins and at least; and a wafer, which is disposed on the lead frame The carrier is provided with a control unit disposed on the carrier of the lead frame, and a sealant covering the lead frame, the wafer, the inner lead and the control element; The groove '5' is placed at any position of the 5 keling gel and exposes part of the lead frame surface; and at least the passive component is disposed on the lead frame surface in the groove and the passive component is electrically connected to the lead frame. 2. The semiconductor package structure of claim 1, wherein the wafer is a flash memory wafer. 3. The semiconductor package structure of claim 1, wherein the encapsulant system is composed of an epoxy resin. 4. The semiconductor package structure of claim 1, wherein the lead frame is made of a metal material. 5. The semiconductor package structure of claim 1, wherein the outer leads are exposed outside the sealant I. 6. The semiconductor package I structure of claim 1, wherein the carrier is provided with a plurality of leads electrically connected to the inner bow, the wafer and the control element. The semiconductor package structure of claim 1, wherein the semiconductor package structure is applicable to a storage medium of an electronic product, the storage medium of the electronic product comprising a digital camera (DC), a personal digital assistant (PDA), and an action phone. 8_ The semiconductor package structure according to claim 1, wherein the semiconductor package structure is applicable to an electronic memory card comprising a secure digital (SD) electronic memory card, a multimedia (MMC) electronic memory card, and a compression flash ( Cf) electronic memory card, memory stick (Ms) electronic 3 memory card, smart media (SM) electronic memory card, sophisticated digital (X])) electronic memory card, fan 11 1307546 your multimedia (RS-MMC) electronic memory Card, mini secure digital electronic memory card and mini flash (Trans Flash) electronic memory card. A semiconductor package structure comprising: a lead frame, which is composed of a plurality of inner leads, a plurality of outer leads, and at least one carrier; at least one wafer is disposed on the carrier of the lead frame At least one control component is disposed on the carrier of the lead frame; a glue body covering the carrier, the inner leads, the wafer and the control component; a plurality of grooves, respectively Symmetrically disposed at any position above and below the encapsulant and exposing a portion of the lead frame surface; and at least one passive component disposed on the leadframe surface in the recesses and electrically connected to the leadframe. 10. The semiconductor package structure of claim 9, wherein the wafer is a flash memory chip. The semiconductor package structure of claim 9, wherein the encapsulant system is composed of an epoxy resin. The semiconductor package structure of claim 9, wherein the lead frame is made of a metal material. 13. The semiconductor package structure of claim 9, wherein the outer bow reveals the encapsulant 14. The semiconductor package structure according to claim 9, wherein the carrier is provided with a reinforced lead wire respectively. Connecting the inner leads, the wafer, and the control element. 15: The semiconductor package structure of claim 9, wherein the semiconductor package is a storage medium of a sub-product, the storage medium of the electronic product is from a digital camera (DC), a personal digital assistant (pDA) And mobile phone. The semiconductor package structure according to claim 9, wherein the semiconductor package structure is suitable for - the electronic product is one of the times 12 1307546 = "the production of the storage medium contains digital Phase Assistant (PDA) and mobile phone. The invention relates to a semiconductor packaging method, the method comprising: providing a lead frame; providing at least a flash memory chip and at least a control element connected to the lead frame - the cover is covered with a sealant a plurality of _(10), the reliant, the flash chip and the control member and forming at least one groove in the sealant; and '·, providing the wire guide 7L in the groove and electrically connecting the lead frame The lead frame. 18. The semiconductor package structure as claimed in claim 1, wherein the carrier area of the package of the package, the inner leads, the flash memory chip, and the control ploughing are performed by using a plurality of lead-ends respectively. The inner pins are connected, the control element 快 flash memory chip and the other end is connected to the carrier. The semiconductor package structure of claim 17, wherein the inner region, the flash memory chip, and the colloid are filled into the fixture by a mold. The semiconductor package structure of claim 19, wherein the mold is provided with at least one bump for molding the recess of the sealant.
TW95134271A 2006-09-15 2006-09-15 Semiconductor package and fabrication method thereof TWI307546B (en)

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TW95134271A TWI307546B (en) 2006-09-15 2006-09-15 Semiconductor package and fabrication method thereof
US11/592,214 US20080067641A1 (en) 2006-09-15 2006-11-03 Package semiconductor and fabrication method thereof
JP2007002514A JP2008072077A (en) 2006-09-15 2007-01-10 Semiconductor package structure and manufacturing method thereof

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