JP2008072077A - Semiconductor package structure and manufacturing method thereof - Google Patents

Semiconductor package structure and manufacturing method thereof Download PDF

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JP2008072077A
JP2008072077A JP2007002514A JP2007002514A JP2008072077A JP 2008072077 A JP2008072077 A JP 2008072077A JP 2007002514 A JP2007002514 A JP 2007002514A JP 2007002514 A JP2007002514 A JP 2007002514A JP 2008072077 A JP2008072077 A JP 2008072077A
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semiconductor package
package structure
mounting base
wire frame
card
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En-Min Jow
恩民 卓
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Jow En Min
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    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805Shape
    • H01L2224/4809Loop shape
    • H01L2224/48091Arched
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481Disposition
    • H01L2224/48151Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481Disposition
    • H01L2224/48151Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48247Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item

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  • Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
  • Encapsulation Of And Coatings For Semiconductor Or Solid State Devices (AREA)

Abstract

<P>PROBLEM TO BE SOLVED: To provide a semiconductor package structure and its manufacturing method. <P>SOLUTION: This semiconductor package structure and its manufacturing method comprise a wire frame 20, at least one chip 40, at least one controlling element 30, and at least one passive element 70. The chip and controlling element are mounted on the mounting base 26 of the wire frame, while a forming material 50 covers the wire frame, chip and controlling element, and forms a package object 10. The forming material installs at least one concave barrel 60, and the depth of the concave barrel is reached to the surface of the mounting base of the wire frame. The passive element is electrically connected to the wire frame inside the concave barrel. <P>COPYRIGHT: (C)2008,JPO&INPIT

Description

本発明は、半導体パッケージ構造、及び、その製法に関するものであって、特に、凹槽を有する半導体パッケージ構造、及び、その製法に関するものである。   The present invention relates to a semiconductor package structure and a manufacturing method thereof, and more particularly to a semiconductor package structure having a recessed tank and a manufacturing method thereof.

一般の半導体パッケージ方式、例えば、薄型スモールアウトラインパッケージ(TSOP)形式、マイクロスモールアウトラインパッケージ(MSOP)、及び、クオータスモールアウトラインパッケージ(QSOP)等のパッケージ技術は、家電製品内のメモリ装置に応用されたり、メモリカードに製作するものである。図1は、公知のメモリ功能を有するパッケージ体の構造断面図である。導線フレーム100は、順に、制御素子(controller component)200、フラッシュメモリ(flash memory)300、及び、受動素子400を装着し、更に、成型材料500により密封されて単一のパッケージ体を形成する。パッケージ体は、最後に、電気テストにより、良品と不良品に分類される。   Package technologies such as a general semiconductor package system, for example, a thin small outline package (TSOP) format, a micro small outline package (MSOP), and a quarter small outline package (QSOP) are applied to a memory device in a home appliance. , To be produced on a memory card. FIG. 1 is a structural cross-sectional view of a package body having a known memory function. The conductive wire frame 100 is sequentially mounted with a control element 200, a flash memory 300, and a passive element 400, and further sealed with a molding material 500 to form a single package. Finally, the package body is classified into a non-defective product and a defective product by an electrical test.

上述のパッケージ体は、密封により一体成型される構造なので、成型材料は制御素子200、フラッシュメモリ300、及び、受動素子400を一緒に包覆し、更に、電気テストを実行する。一方、パッケージ工程中、各IC素子、或いは、製造工程における電気性不良の原因を先に把握することができず、パッケージ終了後に電気テストを実行して、テストの結果が不良の場合、各IC素子、及び、パッケージ材料を破棄することになり、生産コスト、及び、時間が増加する。また、電気不良のパッケージ体が検出される時、成型後のパッケージ体は、パッケージ体内部の電気性不良の原因を察知するのが困難なので、歩留まりが向上できず、依って、上述の問題を克服することが求められている。   Since the above-described package body has a structure that is integrally molded by sealing, the molding material covers the control element 200, the flash memory 300, and the passive element 400 together, and further performs an electrical test. On the other hand, each IC element or the cause of the electrical failure in the manufacturing process cannot be grasped in advance during the packaging process, and an electrical test is performed after the packaging is completed. The device and the packaging material are discarded, and the production cost and time are increased. In addition, when a defective package body is detected, it is difficult to detect the cause of the electrical failure inside the package body after molding, so the yield cannot be improved. There is a need to overcome.

上述の問題を解決するため、本発明は、成型材料をパッケージする時、受動素子を置入する凹槽を形成し、且つ、受動素子を置入しない時、パッケージ体は先に電気テストしてから、受動素子を置入するかどうかを決定することができ、電気性不良のパッケージ体が受動素子を置入するのを回避することを目的とする。   In order to solve the above-mentioned problem, the present invention forms a concave tank in which a passive element is placed when packaging a molding material, and when the passive element is not placed, the package body is electrically tested first. Therefore, it is possible to determine whether or not a passive element is to be inserted, and it is an object to prevent a package body having poor electrical properties from inserting a passive element.

本発明は、更に、成型材料により、チップ装着時、凹槽を形成し、置入する受動素子の連接状況を検視することを目的とする。   A further object of the present invention is to form a concave tub with a molding material at the time of chip mounting and to examine the connection state of passive elements to be placed.

上述の目的を達成するため、本発明は、半導体パッケージ構造を提供し、複数の内ピン、複数の外ピン、及び、少なくとも一つの搭載ベース、からなる導線フレームと、導線フレームの搭載ベースに設置されると共に、導線フレームと電気的に接続する少なくとも一つのチップと、導線フレームの搭載ベースに設置されると共に、導線フレームに電気的に接続される少なくとも一つの制御素子と、成型材料の下方の任意の位置に設置されると共に、搭載ベース表面に凹入される少なくとも一つの凹槽と、凹槽内に設置されると共に、各内ピン、及び、複数の外ピンに連接される少なくとも一つの受動素子と、からなる。   In order to achieve the above object, the present invention provides a semiconductor package structure, and is installed on a lead frame comprising a plurality of inner pins, a plurality of outer pins, and at least one mounting base, and a mounting base of the lead frame. And at least one chip that is electrically connected to the lead frame, at least one control element that is installed on the mounting base of the lead frame and is electrically connected to the lead frame, and below the molding material. At least one recessed tank which is installed at an arbitrary position and is recessed into the mounting base surface, and at least one recessed tank which is installed in the recessed tank and connected to each inner pin and a plurality of outer pins And a passive element.

上述の目的を達成するため、本発明は、半導体パッケージ構造の製法を提供し、導線フレームを提供する工程と、少なくとも一つのフラッシュメモリ、及び、導線フレームの搭載ベース上に連接される少なくとも一つの制御素子を提供する工程と、導線フレームの複数の内ピン、搭載ベース、フラッシュメモリ、及び、制御素子を包覆し、導線フレームの複数の外ピンを包覆せず、少なくとも一つの凹槽を形成する成型材料を提供する工程と、凹槽内に位置し、導線フレームに電気的に接続する受動素子を提供する工程と、からなる。   To achieve the above object, the present invention provides a method of manufacturing a semiconductor package structure, providing a lead frame, at least one flash memory, and at least one connected to a mounting base of the lead frame. A step of providing a control element, and a plurality of inner pins of the lead wire frame, a mounting base, a flash memory, and a control element, and a plurality of outer pins of the lead wire frame are not covered; A step of providing a molding material to be formed; and a step of providing a passive element located in the concave tank and electrically connected to the lead frame.

本発明により、電気性不良のパッケージ体が受動素子を置入するのを回避することが可能である。   According to the present invention, it is possible to avoid a passive element from being placed in a package body having poor electrical properties.

図2は、本発明の実施例による凹槽を有するパッケージ体の断面図である。本実施例中、パッケージ体10は、導線フレーム20、制御素子30、及び、フラッシュメモリ40、を有する。導線フレーム20は、複数の内ピン22、外ピン24、及び、搭載ベース26、からなり、且つ、制御素子30、及び、フラッシュメモリ40は搭載ベース26に設置される。パッケージ体10は成型材料50を塗布し、制御素子30、フラッシュメモリ40、内ピン22、及び、搭載ベース26を包覆し、外ピン24は、成型材料50に包覆されず、成型材料50外に露出する。また、成型材料50は、成型材料のない領域を有して凹槽60を形成し、且つ、凹槽60は成型材料50の任意の位置に設置され、成型材料50の凹槽60は一部の導線フレーム20表面を露出し、受動素子70を置入すると共に、受動素子70と導線フレーム20は電気的に接続する。搭載ベース26は、内ピン22、フラッシュメモリ40、及び、制御素子30に電気的に接続する複数の引線80を設置する。成型材料50の材質はエポキシ(epoxy)を主要材料とし、導線フレーム20は金属からなる。   FIG. 2 is a cross-sectional view of a package body having a recessed tank according to an embodiment of the present invention. In the present embodiment, the package body 10 includes a conductive wire frame 20, a control element 30, and a flash memory 40. The conducting wire frame 20 includes a plurality of inner pins 22, outer pins 24, and a mounting base 26, and the control element 30 and the flash memory 40 are installed on the mounting base 26. The package body 10 applies the molding material 50 to cover the control element 30, the flash memory 40, the inner pin 22, and the mounting base 26, and the outer pin 24 is not covered by the molding material 50. Exposed outside. Moreover, the molding material 50 has the area | region without a molding material, forms the concave tank 60, and the concave tank 60 is installed in the arbitrary positions of the molding material 50, and the concave tank 60 of the molding material 50 is a part. The surface of the conductive wire frame 20 is exposed, the passive element 70 is inserted, and the passive element 70 and the conductive wire frame 20 are electrically connected. The mounting base 26 is provided with a plurality of drawn lines 80 that are electrically connected to the inner pins 22, the flash memory 40, and the control element 30. The molding material 50 is mainly made of epoxy, and the lead frame 20 is made of metal.

図3は、本発明のもう一つの実施例を示し、パッケージ体10上方、及び、下方にそれぞれ、凹槽60と62を対称設置し、凹槽60内の受動素子70と導線フレーム20の連接状態を検視しやすくしている。上述の実施例の精神によると、パッケージ体10の凹槽60と62は回路設計の要求により、パッケージ体10上方、及び、下方の任意の位置に設置され、凹槽60に受動素子70を装着する。本発明のパッケージ体10はデジタルカメラ、PDA、或いは、携帯電話等の各種電子製品の保存媒体に適用されるか、或いは、SDカード、マルチメディアカードMMC、コンパクトフラッシュ(登録商標)CFカード、メモリスティックMS、スマートメディアSMカード、XDカード、RS―MMC、ミニSDカード、及び、トランスフラッシュ等を製作する。   FIG. 3 shows another embodiment of the present invention, in which concave tanks 60 and 62 are symmetrically installed above and below the package body 10, respectively, and the passive element 70 and the conductor frame 20 in the concave tank 60 are connected. It makes it easy to examine the condition. According to the spirit of the above-described embodiment, the concave tanks 60 and 62 of the package body 10 are installed at arbitrary positions above and below the package body 10 according to the requirements of circuit design, and the passive element 70 is mounted on the concave tank 60. To do. The package 10 of the present invention is applied to a storage medium of various electronic products such as a digital camera, a PDA, or a mobile phone, or an SD card, a multimedia card MMC, a compact flash (registered trademark) CF card, a memory Manufactures stick MS, smart media SM card, XD card, RS-MMC, mini SD card, transformer flash, etc.

図4Aと図4Bは、本発明の凹槽を有するパッケージの工程を示す。図4Aで示されるように、まず、導線フレーム20を提供し、導線フレーム20上方は、順に、制御素子30、フラッシュメモリ40を設置し、ボンディングワイヤにより、引線80一端を内ピン22、制御素子30、及び、フラッシュメモリ40に電気的に接続し、もう一端は搭載ベース26に連接する。   4A and 4B show a process of a package having a concave tub according to the present invention. As shown in FIG. 4A, first, the conductor frame 20 is provided, and the control element 30 and the flash memory 40 are sequentially installed above the conductor frame 20, and one end of the drawn line 80 is connected to the inner pin 22 and the control element by a bonding wire. 30 and the flash memory 40, and the other end is connected to the mounting base 26.

図4Bで示されるように、金型によりパッケージ工程を実行し、成型材料50が導線フレーム20のフラッシュメモリ40、及び、制御素子30を包覆し、金型は、上金型92、及び、下金型94の構造で、それぞれ、凸ブロック96、98を設置する。パッケージ工程実行時、凸ブロック96、98は、それぞれ、導線フレーム20上方と下方に抵触し、パッケージ時の挟持作用を生成し、成型材料50が完全に包覆するのを防止する。成型材料を金型に注入した後、凹槽60、62を形成し、続いて、受動素子70を凹槽60中に置入すると共に、導線フレーム20に電気的に接続して、図3で示されるようなパッケージ体構造が完成する。本発明の実施例の精神により、上金型92と下金型94は単一の凸ブロック96を設置し、パッケージ時、凹槽60を形成してから、受動素子70を置入し、図2で示されるようなパッケージ体構造が完成する。   As shown in FIG. 4B, a packaging process is performed by a mold, and the molding material 50 covers the flash memory 40 and the control element 30 of the lead frame 20, and the mold includes an upper mold 92 and Convex blocks 96 and 98 are installed in the structure of the lower mold 94, respectively. When the packaging process is executed, the convex blocks 96 and 98 conflict with the conductive wire frame 20 above and below, respectively, to generate a clamping action at the time of packaging, and prevent the molding material 50 from being completely covered. After injecting the molding material into the mold, the concave tanks 60 and 62 are formed, and then the passive element 70 is placed in the concave tank 60 and electrically connected to the conductor frame 20 in FIG. The package structure as shown is completed. According to the spirit of the embodiment of the present invention, the upper mold 92 and the lower mold 94 are provided with a single convex block 96, and when the package is formed, the concave tank 60 is formed, and then the passive element 70 is inserted. 2 completes the package structure.

上述の実施例によると、完成したパッケージ体10は、電気テストを経て、結果が不正常である場合、パッケージ体10を廃棄し、公知技術のパッケージ体が、制御素子、フラッシュメモリ、及び、受動素子をパッケージしてから電気テストをするのではないので、不要な加工時間を減少させ、及び、材料の節約が可能である。また、本発明の凹槽60、62は、蓋体(図示しない)を凹槽60、62上に設置し、粒子が凹槽60、62内に侵入し、パッケージ体10の電気不良の原因になるのを防止する。   According to the above-described embodiment, the completed package body 10 undergoes an electrical test, and if the result is not normal, the package body 10 is discarded, and the package body of the known technology includes the control element, the flash memory, and the passive body. Since the electrical test is not performed after the device is packaged, unnecessary processing time can be reduced and material can be saved. In addition, the recessed tanks 60 and 62 of the present invention have lids (not shown) installed on the recessed tanks 60 and 62, and particles enter the recessed tanks 60 and 62, causing an electrical failure of the package body 10. To prevent becoming.

上述のように、本発明は半導体パッケージ構造、及び、その製法を提出し、成型材料を利用する時、凹槽を形成して受動素子を置入し、且つ、受動素子を置入しない時、パッケージ体は先に電気テストをして、テストをパスしたパッケージ体が受動素子を置入するので、不良品が受動素子を置入せず、且つ、凹槽内の受動素子の連接状況が分析しやすく、不良品の原因になるのを防止することができる。   As described above, the present invention submits a semiconductor package structure and a manufacturing method thereof, and when a molding material is used, when a passive element is placed by forming a concave tank, and when a passive element is not placed, The package body conducts an electrical test first, and the package body that passes the test places the passive element, so the defective product does not place the passive element, and the connection status of the passive element in the concave tank is analyzed. It is easy to do, and it can prevent that it becomes a cause of inferior goods.

本発明では好ましい実施例を前述の通り開示したが、これらは決して本発明に限定するものではなく、当該技術を熟知する者なら誰でも、本発明の精神と領域を脱しない範囲内で各種の変動や潤色を加えることができ、従って本発明の保護範囲は、特許請求の範囲で指定した内容を基準とする。   In the present invention, preferred embodiments have been disclosed as described above. However, the present invention is not limited to the present invention, and any person who is familiar with the technology can use various methods within the spirit and scope of the present invention. Variations and moist colors can be added, so the protection scope of the present invention is based on what is specified in the claims.

公知のメモリ功能を有するパッケージ体の構造断面図である。It is structure sectional drawing of the package body which has a well-known memory performance. 本発明の実施例による凹槽を有するパッケージ体の断面図である。It is sectional drawing of the package body which has a concave tank by the Example of this invention. 本発明のもう一つの実施例による凹槽を有するパッケージ体の断面図である。FIG. 6 is a cross-sectional view of a package body having a recessed tank according to another embodiment of the present invention. 本発明による凹槽を有するパッケージ工程を示す図である。It is a figure which shows the package process which has a concave tank by this invention. 本発明による凹槽を有するパッケージ工程を示す図である。It is a figure which shows the package process which has a concave tank by this invention.

符号の説明Explanation of symbols

100 導線フレーム
200 制御素子
300 フラッシュメモリ
400 受動素子
500 成型材料
10 パッケージ体
20 導線フレーム
22 内ピン
24 外ピン
26 搭載ベース
30 制御素子
40 フラッシュメモリ
50 成型材料
60、62 凹槽
70 受動素子
80 引線
92 上金型
94 下金型
96、98 凸ブロック
DESCRIPTION OF SYMBOLS 100 Conductive frame 200 Control element 300 Flash memory 400 Passive element 500 Molding material 10 Package body 20 Conductive frame 22 Inner pin 24 Outer pin 26 Mounted base 30 Control element 40 Flash memory 50 Molding material 60, 62 Recessed tank 70 Passive element 80 Drawing line 92 Upper die 94 Lower die 96, 98 Convex block

Claims (20)

半導体パッケージ構造であって、
複数の内ピン、複数の外ピン、及び、少なくとも一つの搭載ベース、からなる導線フレームと、
前記導線フレームの前記搭載ベースに設置される少なくとも一つのチップと、
前記導線フレームの前記搭載ベースに設置される少なくとも一つの制御素子と、
前記導線フレーム、前記チップ、前記内ピン、及び、前記制御素子を包覆する成型材料と、
前記成型材料の下方の任意の位置に設置されると共に、一部の前記導線フレームを露出する少なくとも一つの凹槽と、
前記凹槽内の前記導線フレーム表面に設置されると共に、前記導線フレームに電気的に連接される少なくとも一つの受動素子と、
からなることを特徴とする半導体パッケージ構造。
A semiconductor package structure,
A conductive wire frame comprising a plurality of inner pins, a plurality of outer pins, and at least one mounting base;
At least one chip installed on the mounting base of the conducting wire frame;
At least one control element installed on the mounting base of the conducting wire frame;
A molding material covering the conductor frame, the chip, the inner pin, and the control element;
At least one recessed tank that is installed at an arbitrary position below the molding material and exposes part of the conductor frame;
At least one passive element installed on the surface of the conductive wire frame in the concave tank and electrically connected to the conductive wire frame;
A semiconductor package structure comprising:
前記チップはフラッシュメモリであることを特徴とする請求項1に記載の半導体パッケージ構造。   The semiconductor package structure according to claim 1, wherein the chip is a flash memory. 前記成型材料はエポキシからなることを特徴とする請求項1に記載の半導体パッケージ構造。   The semiconductor package structure according to claim 1, wherein the molding material is made of epoxy. 前記導線フレームは金属材質からなることを特徴とする請求項1に記載の半導体パッケージ構造。   The semiconductor package structure according to claim 1, wherein the conductive wire frame is made of a metal material. 前記外ピンは前記成型材料から露出することを特徴とする請求項1に記載の半導体パッケージ構造。   The semiconductor package structure according to claim 1, wherein the outer pin is exposed from the molding material. 前記搭載ベースは複数の引線を設置し、それぞれ、前記内ピン、前記チップ、及び、前記制御素子に電気的に接続することを特徴とする請求項1に記載の半導体パッケージ構造。   2. The semiconductor package structure according to claim 1, wherein the mounting base is provided with a plurality of drawn wires and electrically connected to the inner pin, the chip, and the control element, respectively. 前記半導体パッケージ構造は、電子製品の保存媒体に適用され、前記電子製品の前記保存媒体は、デジタルカメラ、PDA、及び、携帯電話を含むことを特徴とする請求項1に記載の半導体パッケージ構造。   2. The semiconductor package structure according to claim 1, wherein the semiconductor package structure is applied to a storage medium of an electronic product, and the storage medium of the electronic product includes a digital camera, a PDA, and a mobile phone. 前記半導体パッケージ構造は、電子メモリに適用され、前記電子メモリは、SDカード、MMCカード、CFカード、MS、SMカード、XDカード、RS―MMCカード、ミニSDカード、及び、トランスフラッシュを含むことを特徴とする請求項1に記載の半導体パッケージ構造。   The semiconductor package structure is applied to an electronic memory, and the electronic memory includes an SD card, an MMC card, a CF card, an MS, an SM card, an XD card, an RS-MMC card, a mini SD card, and a transflash. The semiconductor package structure according to claim 1. 半導体パッケージ構造であって、
複数の内ピン、複数の外ピン、及び、少なくとも一つの搭載ベース、からなる導線フレームと、
前記導線フレームの前記搭載ベースに設置される少なくとも一つのチップと、
前記導線フレームの前記搭載ベースに設置される少なくとも一つの制御素子と、
前記搭載ベース、前記チップ、前記内ピン、及び、前記制御素子を包覆する成型材料と、
前記成型材料の上方、及び、下方の任意の位置に対称設置されると共に、一部の前記導線フレーム表面を露出する少なくとも複数の凹槽と、
前記凹槽内の前記導線フレーム表面に設置されると共に、前記導線フレームに電気的に連接される少なくとも一つの受動素子と、
からなることを特徴とする半導体パッケージ構造。
A semiconductor package structure,
A conductive wire frame comprising a plurality of inner pins, a plurality of outer pins, and at least one mounting base;
At least one chip installed on the mounting base of the conducting wire frame;
At least one control element installed on the mounting base of the conducting wire frame;
A molding material covering the mounting base, the chip, the inner pin, and the control element;
And at least a plurality of recessed tanks that are symmetrically installed at arbitrary positions above and below the molding material and expose a part of the surface of the conductor frame;
At least one passive element installed on the surface of the conductive wire frame in the concave tank and electrically connected to the conductive wire frame;
A semiconductor package structure comprising:
前記チップはフラッシュメモリであることを特徴とする請求項9に記載の半導体パッケージ構造。   The semiconductor package structure according to claim 9, wherein the chip is a flash memory. 前記成型材料はエポキシからなることを特徴とする請求項9に記載の半導体パッケージ構造。   The semiconductor package structure according to claim 9, wherein the molding material is made of epoxy. 前記導線フレームは金属材質からなることを特徴とする請求項9に記載の半導体パッケージ構造。   The semiconductor package structure according to claim 9, wherein the conductive wire frame is made of a metal material. 前記外ピンは前記成型材料から露出することを特徴とする請求項9に記載の半導体パッケージ構造。   The semiconductor package structure according to claim 9, wherein the outer pin is exposed from the molding material. 前記搭載ベースは複数の引線を設置し、それぞれ、前記内ピン、前記チップ、及び、前記制御素子に電気的に接続することを特徴とする請求項9に記載の半導体パッケージ構造。   10. The semiconductor package structure according to claim 9, wherein the mounting base is provided with a plurality of drawn wires and electrically connected to the inner pin, the chip, and the control element, respectively. 前記半導体パッケージ構造は、電子製品の保存媒体に適用され、前記電子製品の前記保存媒体は、デジタルカメラ、PDA、及び、携帯電話を含むことを特徴とする請求項9に記載の半導体パッケージ構造。   The semiconductor package structure according to claim 9, wherein the semiconductor package structure is applied to a storage medium of an electronic product, and the storage medium of the electronic product includes a digital camera, a PDA, and a mobile phone. 前記半導体パッケージ構造は、電子メモリに適用され、前記電子メモリは、SDカード、MMCカード、CFカード、MS、SMカード、XDカード、RS―MMCカード、ミニSDカード、及び、トランスフラッシュを含むことを特徴とする請求項9に記載の半導体パッケージ構造。   The semiconductor package structure is applied to an electronic memory, and the electronic memory includes an SD card, an MMC card, a CF card, an MS, an SM card, an XD card, an RS-MMC card, a mini SD card, and a transflash. The semiconductor package structure according to claim 9. 半導体パッケージ方法であって、前記方法は、
導線フレームを提供する工程と、
少なくとも一つのフラッシュメモリ、及び、前記導線フレームの搭載ベース上に連接される少なくとも一つの制御素子を提供する工程と、
前記導線フレームの複数の内ピン、前記搭載ベース、前記フラッシュメモリ、及び、前記制御素子を包覆し、少なくとも一つの凹槽を形成する成型材料を提供する工程と、
前記凹槽内の前記導線フレームに位置し、前記導線フレームに電気的に接続する受動素子を提供する工程と、
からなることを特徴とする半導体パッケージ方法。
A semiconductor packaging method, the method comprising:
Providing a conductor frame;
Providing at least one flash memory and at least one control element connected to a mounting base of the conductor frame;
Providing a molding material that covers the plurality of inner pins of the conductive wire frame, the mounting base, the flash memory, and the control element, and forms at least one concave tank;
Providing a passive element located on the lead frame in the recessed tank and electrically connected to the lead frame;
A semiconductor package method comprising:
前記導線フレームの前記搭載ベース、前記内ピン、前記フラッシュメモリ、前記制御素子を包覆する前、ワイヤーボンディングにより、複数の引線の一端がそれぞれ、前記内ピン、前記制御素子、前記フラッシュメモリに電気的に接続し、もう一端が前記搭載ベースに連接されることを特徴とする請求項17に記載の半導体パッケージ方法。   Before covering the mounting base, the inner pin, the flash memory, and the control element of the conductive wire frame, one end of a plurality of drawn wires is electrically connected to the inner pin, the control element, and the flash memory, respectively, by wire bonding. The semiconductor package method according to claim 17, further comprising connecting the other end to the mounting base. 金型により、前記導線フレームの前記搭載ベース、前記内ピン、前記フラッシュメモリ、及び、前記制御素子を包覆し、前記成型材料を前記金型内に注入することを特徴とする請求項17に記載の半導体パッケージ方法。   18. The mold according to claim 17, wherein the mold covers the mounting base, the inner pin, the flash memory, and the control element of the conductive wire frame, and the molding material is injected into the mold. The semiconductor package method as described. 前記金型は、少なくとも一つの凸ブロックを設置し、前記成型材料の前記凹槽を成型することを特徴とする請求項19に記載の半導体パッケージ方法。   20. The semiconductor package method according to claim 19, wherein the mold is provided with at least one convex block, and the concave tank of the molding material is molded.
JP2007002514A 2006-09-15 2007-01-10 Semiconductor package structure and manufacturing method thereof Pending JP2008072077A (en)

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Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2015103790A (en) * 2013-11-28 2015-06-04 株式会社東海理化電機製作所 Lead frame structure and manufacturing method of the same
JP2021190522A (en) * 2020-05-28 2021-12-13 三菱電機株式会社 Semiconductor device

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2015103790A (en) * 2013-11-28 2015-06-04 株式会社東海理化電機製作所 Lead frame structure and manufacturing method of the same
JP2021190522A (en) * 2020-05-28 2021-12-13 三菱電機株式会社 Semiconductor device
JP7308793B2 (en) 2020-05-28 2023-07-14 三菱電機株式会社 semiconductor equipment

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