CN100505246C - Semi-conductor packaging structure and producing method thereof - Google Patents
Semi-conductor packaging structure and producing method thereof Download PDFInfo
- Publication number
- CN100505246C CN100505246C CNB2006101420104A CN200610142010A CN100505246C CN 100505246 C CN100505246 C CN 100505246C CN B2006101420104 A CNB2006101420104 A CN B2006101420104A CN 200610142010 A CN200610142010 A CN 200610142010A CN 100505246 C CN100505246 C CN 100505246C
- Authority
- CN
- China
- Prior art keywords
- lead frame
- semiconductor package
- control element
- chip
- adhesive body
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
Links
Images
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32245—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
- H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73265—Layer and wire connectors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/73—Means for bonding being of different types provided for in two or more of groups H01L24/10, H01L24/18, H01L24/26, H01L24/34, H01L24/42, H01L24/50, H01L24/63, H01L24/71
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/181—Encapsulation
- H01L2924/1815—Shape
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
- H01L2924/191—Disposition
- H01L2924/19101—Disposition of discrete passive components
- H01L2924/19105—Disposition of discrete passive components in a side-by-side arrangement on a common die mounting substrate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
- H01L2924/191—Disposition
- H01L2924/19101—Disposition of discrete passive components
- H01L2924/19107—Disposition of discrete passive components off-chip wires
Abstract
The invention discloses a semiconductor package structure and a method for manufacturing the same. The semiconductor package structure comprises a lead frame, at least one chip, at least one control element and at least one passive element, wherein, the chip and the control element are arranged on a carrying seat of the lead frame; a sealing colloid which warps the lead frame, the chip and the control element to form a package body. The package body is provided with a groove which runs deeply to the surface of the carrying seat of the lead frame, with the passive element which is electrically connected with the lead frame arranged on side. The invention the package body is subject to electric property test before the passive element is position in, and then the passive element is arranged in the package body past the electric property test, thereby preventing the passive to be positioned in a defective product and facilitating the analysis of the causes of the defective product.
Description
Technical field
The present invention relates to a kind of semiconductor package and method for making thereof, particularly relate to a kind of semiconductor package and method for making thereof with groove.
Background technology
The mode of general industrial circle semiconductor packages such as thin-type small-size encapsulation (TSOP) pattern, miniature small size encapsulation (MSOP) and 1/4 small size encapsulation encapsulation technologies such as (QSOP) often are applied to the memory storage in the consumption electronic products or make memory card etc., be illustrated in figure 1 as the structure cutaway view of packaging body of the tool memory function of prior art, lead frame 100 is installed control element (controller component) 200 in regular turn, flash chip (flash memory) 300 and passive device 400 elements, utilize adhesive body 500 sealings to form single packaging body again, packaging body is at last via testing electrical property, to sort out non-defective unit and defective products.
Above-mentioned packaging body is because of being sealed to integrated structure, and adhesive body is coated togather control element 200, flash chip 300 and passive device 400, carries out testing electrical property again.On the one hand, can't understand in the encapsulation process and learn that in advance each IC element or processing procedure cause electrically bad reason, and can only after having encapsulated, carry out testing electrical property, if testing electrical property is bad, then each IC element and encapsulating material thereof must be scrapped, and cause the increase of production cost and time; On the other hand, when the electrically bad packaging body of check, because of the packaging body after the sealing, electrically bad reason of package interior is learnt in difficult detection, and then causes qualification rate to improve, therefore how to overcome the problems referred to above and be present industry institute urgently need.
Summary of the invention
In order to address the above problem, one of the object of the invention, be to utilize adhesive body when sealing, to form groove to be used to insert passive device, and when not inserting passive device, whether the decision again of can going ahead of the rest before the packaging body behind the testing electrical property inserts passive device, inserts passive device to avoid electrically bad packaging body.
Another purpose of the present invention is to utilize adhesive body to form groove when the plastic packaging chip, in order to detect the connection state of the passive device of inserting.
In order to achieve the above object, the invention provides a kind of semiconductor package, comprise a lead frame, it is formed by pin, a plurality of outer pin and at least one load bearing seat in a plurality of; At least one chip, it is arranged at the load bearing seat of lead frame and electrically connects lead frame; At least one control element, it is arranged at the load bearing seat of lead frame and electrically connects lead frame; At least one groove is arranged at adhesive body arbitrary position, below and recessed to the load bearing seat surface; And at least one passive device, be provided with in the groove and connect pin and a plurality of outer pin in each.
In order to achieve the above object, the invention provides a kind of semiconductor packages method for making, it provides on the supporting region that a lead frame, at least one flash chip and at least one control element be connected in lead frame; A plurality of interior pin, supporting region, flash chip and the control element of one adhesive body coated wire frame are provided, and the adhesive body a plurality of outer pin of coated wire frame not, and form at least one groove, and provide passive device in groove and electrically connect lead frame in adhesive body.
The present invention through the following steps specific embodiment and cooperate the appended accompanying drawing that shows to illustrate in detail, when the effect that is easier to understand purpose of the present invention, technology contents, characteristics and is reached.
Description of drawings
Fig. 1 is the structure cutaway view of the packaging body of prior art tool memory function.
Fig. 2 is one embodiment of the invention, the cutaway view of the packaging body of tool groove structure.
Fig. 3 is an another embodiment of the present invention, the cutaway view of the packaging body of tool groove structure.
Fig. 4 A and Fig. 4 B are the encapsulation step flow chart of tool groove of the present invention.
Symbol description among the figure
100 lead frames
200 control elements
300 flash chips
400 passive devices
500 adhesive bodies
10 packaging bodies
20 lead frames
Pin in 22
24 outer pins
26 load bearing seats
30 control elements
40 flash chips
50 adhesive bodies
60,62 grooves
70 passive devices
80 lead-in wires
92 patrixes
94 counterdies
96,98 projections
Embodiment
Figure 2 shows that packaging body cutaway view according to one embodiment of the invention tool groove.In present embodiment, packaging body 10 has lead frame 20, control element 30 and flash chip 40, and wherein lead frame 20 is made up of pins 22, outer pin 24 and load bearing seat 26 in a plurality of, and control element 30 and flash chip 40 are arranged at load bearing seat 26.Packaging body 10 coating adhesive bodies 50, and coat control element 30, flash chip 40, interior pin 22 and load bearing seat 26, outer pin 24 is not then coated by adhesive body 50 and exposes outside the adhesive body 50.Again, the zone that adhesive body 50 has not sealing forms groove 60, and groove 60 is arranged at adhesive body 50 arbitrary positions, and the groove 60 of adhesive body 50 exposes part lead frame 20 surfaces in addition, is used to insert passive device 70 and passive device 70 and electrically connects with lead frame 20; Load bearing seat 26 is provided with a plurality of lead-in wires 80 and electrically connects interior pin 22, this flash chip 40 and this control element 30 respectively.The material of above-mentioned adhesive body 50 is made by metal for main composition material lead frame 20 by epoxy resin (epoxy).
Again, be illustrated in figure 3 as, illustrate that packaging body 10 tops and below are symmetrical arranged groove 60 and 62 respectively so that the passive device 70 and lead frame 20 connection status in the detecting groove 60 according to another embodiment of the present invention.According to the spirit of the foregoing description, the groove 60 of packaging body 10 and 62 demands according to circuit design are arranged at the arbitrary position in packaging body 10 tops and below and in groove 60 passive device 70 are installed.Packaging body 10 of the present invention is applicable to digital camera (DC), the storing media of each electronic product such as PDA(Personal Digital Assistant) or mobile phone or be processed into secure digital (SD) electronic memory card, multimedia (MMC) electronic memory card, compact flash (CF) electronic memory card, memory bar (MS) electronic memory card, smart media (SM) electronic memory card, most advanced and sophisticated numeral (XD) electronic memory card, mini multimedia (RS-MMC) electronic memory card, mini secure digital (mini-SD) electronic memory card and mini quickflashing (Trans Flash) electronic memory card.
Fig. 4 A and Fig. 4 B are depicted as the encapsulation step flow chart according to tool groove of the present invention.Shown in Fig. 4 A, lead frame 20 at first is provided, and in lead frame 20 tops control element 30 and flash chip 40 are set in regular turn and utilize the routing mode will go between respectively 80 1 ends electrically connect in pin 22, control element 30 and flash chip 40 and other end connection load bearing seat 26.
It is above-mentioned to continue, shown in Fig. 4 B, utilize dies with epoxy compound to carry out flash chip 40 and control element 30 that manufacture procedure of adhesive makes adhesive body 50 coated wire framves 20, wherein dies with epoxy compound is the structure of patrix 92 and counterdie 94, and projection 96 and 98 are set respectively respectively at patrix 92 and counterdie 94 structures, when carrying out manufacture procedure of adhesive, projection 96 and 98 can conflict respectively lead frame 20 tops and below, produce clamping action when causing sealing, prevent that adhesive body 50 from coating fully, this adhesive body pours in this mould the back and forms groove 60 and 62, then inserts passive device 70 again in groove 60 and electrically connect lead frame 20, promptly finishes package body structure as shown in Figure 3.According to the spirit of the embodiment of the invention, patrix 92 or counterdie 94 are provided with single projection 96 and form groove 60 insert passive device 70 again when sealing, promptly finish package body structure as shown in Figure 2.
According to the above embodiments, the packaging body of finishing 10 is via testing electrical property, if its test result is for electrically undesired, packaging body 10 can be scrapped in advance, avoid to remake testing electrical property after control element, flash of light memory chip and the passive device overall package in the prior art, improvement of the present invention can be about to abnormal packaging body earlier and be scrapped the cost expenditure that reduces unnecessary process time and save material; On the other hand, groove 60 of the present invention and 62 can utilize a cover plate (not shown) to be located on groove 60 and 62, can prevent that micronic dust (particle) from directly dropping in groove 60 and 62, causes packaging body 10 electrical bad doubts.
Comprehensively above-mentioned, the present invention proposes a kind of semiconductor package and method for making thereof, form groove when utilizing adhesive body and be used to insert passive device, and when not inserting passive device, can go ahead of the rest before the packaging body and will insert passive device by the packaging body of testing electrical property again behind the testing electrical property, therefore prevent that defective products from inserting the connection state of the passive device in passive device and the groove, be convenient to analyze the reason that causes defective products.
Above-described embodiment only is explanation technological thought of the present invention and characteristics, its purpose makes the personage who has the knack of this skill can understand content of the present invention and is implementing according to this, when can not with qualification claim of the present invention, promptly the equalization of doing according to disclosed spirit generally changes or modifies, and must be encompassed in the claim of the present invention.
Claims (20)
1. semiconductor package comprises:
One lead frame, it is made up of pin, a plurality of outer pins and at least one load bearing seat in a plurality of;
At least one chip, it is arranged at this load bearing seat of this lead frame;
At least one control element, it is arranged at this load bearing seat of this lead frame;
One adhesive body, it is coated on this lead frame, this chip, pin and this control element in this;
At least one groove is arranged at the arbitrary position of this adhesive body and exposes this lead frame surface of part; And
At least one passive device, this lead frame surface and this passive device of being arranged in this groove electrically connect this lead frame.
2. semiconductor package as claimed in claim 1, wherein this chip is a flash chip.
3. semiconductor package as claimed in claim 1, wherein this adhesive body is made of epoxy resin.
4. semiconductor package as claimed in claim 1, wherein this lead frame is made of metal material.
5. semiconductor package as claimed in claim 1, wherein said outer pin exposes outside this adhesive body.
6. semiconductor package as claimed in claim 1, wherein this load bearing seat is provided with a plurality of lead-in wires and electrically connects described interior pin, this chip and this control element respectively.
7. semiconductor package as claimed in claim 1, wherein this semiconductor package is applicable to a storing media of electronic product, the storing media of this electronic product comprises the storing media of digital camera, personal digital assistant and mobile phone.
8. semiconductor package as claimed in claim 1, this semiconductor package is applicable to multiple electronic memory card, and these electronic memory cards comprise SD electronic memory card, MMC electronic memory card, CF electronic memory card, MS electronic memory card, SM electronic memory card, XD electronic memory card, RS-MMC electronic memory card, mini-SD electronic memory card and TransFlash electronic memory card.
9. semiconductor package comprises:
One lead frame, it is made up of pin, a plurality of outer pins and at least one load bearing seat in a plurality of;
At least one chip, it is arranged at this load bearing seat of this lead frame;
At least one control element, it is arranged at this load bearing seat of this lead frame;
One adhesive body, it is coated on this load bearing seat, pin, this chip and this control element in those;
A plurality of grooves are symmetricly set in this adhesive body top and arbitrary position, below respectively and expose this lead frame surface of part; And
At least one passive device be arranged at the lead frame surface in the described groove, and this passive device electrically connects this lead frame.
10. semiconductor package as claimed in claim 9, wherein this chip is a flash chip.
11. semiconductor package as claimed in claim 9, wherein this adhesive body is made of epoxy resin.
12. semiconductor package as claimed in claim 9, wherein this lead frame is made of metal material.
13. semiconductor package as claimed in claim 9, wherein said outer pin exposes outside this adhesive body.
14. semiconductor package as claimed in claim 9, wherein this load bearing seat is provided with a plurality of lead-in wires and electrically connects pin, this chip and this control element in those respectively.
15. semiconductor package as claimed in claim 9, wherein this semiconductor package is applicable to a storing media of electronic product, and the storing media of this electronic product comprises the storing media of digital camera, personal digital assistant and mobile phone.
16. as claim 1 or 9 described semiconductor packages, wherein this semiconductor package is applicable to a storing media of electronic product, the storing media of this electronic product comprises the storing media of digital camera, personal digital assistant and mobile phone.
17. a method for packaging semiconductor, its step comprises:
One lead frame is provided;
Provide on the supporting region that at least one flash chip and at least one control element be connected in this lead frame;
Coat pin, this supporting region, this flash chip and this control element in this lead frame a plurality of with an adhesive body, and form at least one groove in this adhesive body; And
One passive device this lead frame in this groove is set, and electrically connects this lead frame.
18. method for packaging semiconductor as claimed in claim 17, wherein coat before this supporting region of this lead frame, a plurality of interior pin, this flash chip and this control element, utilize the routing mode that a plurality of lead-in wire one ends are electrically connected pin in these, this control element and this flash chip respectively, and the other end connect this load bearing seat.
19. method for packaging semiconductor as claimed in claim 17 wherein utilize a mould to coat the supporting region of described lead frame, interior pin, flash chip and control element, and adhesive body pours in this mould.
20. method for packaging semiconductor as claimed in claim 19, wherein this mould is provided with at least one projection, is used for this groove of this adhesive body of moulding.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CNB2006101420104A CN100505246C (en) | 2006-09-30 | 2006-09-30 | Semi-conductor packaging structure and producing method thereof |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CNB2006101420104A CN100505246C (en) | 2006-09-30 | 2006-09-30 | Semi-conductor packaging structure and producing method thereof |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN101154650A CN101154650A (en) | 2008-04-02 |
| CN100505246C true CN100505246C (en) | 2009-06-24 |
Family
ID=39256195
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CNB2006101420104A Expired - Fee Related CN100505246C (en) | 2006-09-30 | 2006-09-30 | Semi-conductor packaging structure and producing method thereof |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN100505246C (en) |
Families Citing this family (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101335221B (en) * | 2008-07-30 | 2010-06-02 | 江苏长电科技股份有限公司 | Slotted metal plate type novel semi-conductor package method |
| JP5672678B2 (en) * | 2009-08-21 | 2015-02-18 | Tdk株式会社 | Electronic component and manufacturing method thereof |
| CN101866902B (en) * | 2010-06-18 | 2012-02-29 | 日月光封装测试(上海)有限公司 | Semiconductor packaging structure, lead frame and chip holder thereof |
| CN102231371B (en) * | 2011-05-30 | 2014-04-09 | 深圳市江波龙电子有限公司 | Semiconductor chip and storage device |
| WO2012163100A1 (en) * | 2011-05-30 | 2012-12-06 | 深圳市江波龙电子有限公司 | Semiconductor chip and storage device |
| CN103249271A (en) * | 2013-03-21 | 2013-08-14 | 深圳市新国都技术股份有限公司 | Plastic casing structure provided with protective circuit, as well as forming die and manufacture method thereof |
-
2006
- 2006-09-30 CN CNB2006101420104A patent/CN100505246C/en not_active Expired - Fee Related
Also Published As
| Publication number | Publication date |
|---|---|
| CN101154650A (en) | 2008-04-02 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN100505246C (en) | Semi-conductor packaging structure and producing method thereof | |
| CN100592509C (en) | Semiconductor device and capsule type semiconductor package | |
| US7985618B2 (en) | Semiconductor device has encapsulant with chamfer such that portion of substrate and chamfer are exposed from encapsulant and remaining portion of surface of substrate is covered by encapsulant | |
| EP2362416B1 (en) | Multi-die module | |
| US8637978B2 (en) | System-in-a-package based flash memory card | |
| US8884415B2 (en) | IC package with stainless steel leadframe | |
| CN103474406A (en) | Copper-free flat packaging piece of AAQFN frame product and manufacturing process thereof | |
| US20110084374A1 (en) | Semiconductor package with sectioned bonding wire scheme | |
| US20110198740A1 (en) | Semiconductor storage device and manufacturing method thereof | |
| US8952514B2 (en) | Semiconductor package | |
| US20130323885A1 (en) | Method of manufacturing high-capacity semiconductor package | |
| CN107895703B (en) | Multipurpose nonlinear semiconductor packaging body assembly line | |
| US20090134504A1 (en) | Semiconductor package and packaging method for balancing top and bottom mold flows from window | |
| CN200986917Y (en) | Open type semiconductor package structure | |
| CN101165890A (en) | Semiconductor package structure and manufacture method thereof | |
| US20060012040A1 (en) | Semiconductor package | |
| CN207690781U (en) | QFN encapsulating structures, the QFN encapsulating structures of fingerprint recognition and the smart mobile phone with it | |
| CN102044445B (en) | Method for manufacturing lead frame of no-lead semiconductor package (QFN) | |
| TWI307546B (en) | Semiconductor package and fabrication method thereof | |
| US20080067641A1 (en) | Package semiconductor and fabrication method thereof | |
| CN101461061A (en) | Semiconductor device | |
| KR20060123909A (en) | Non-horizontal array molding method for semiconductor package | |
| CN103354226B (en) | Stack packaged device | |
| JP3130639U (en) | Semiconductor package structure | |
| US20070063311A1 (en) | Rewiring Substrate Strip Having a Plurality of Semiconductor Component Positions |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C06 | Publication | ||
| PB01 | Publication | ||
| C10 | Entry into substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| C14 | Grant of patent or utility model | ||
| GR01 | Patent grant | ||
| ASS | Succession or assignment of patent right |
Owner name: APTOS TECHNOLOGY CO., LTD. Free format text: FORMER OWNER: ZHUO ENMIN Effective date: 20150511 |
|
| C41 | Transfer of patent application or patent right or utility model | ||
| TR01 | Transfer of patent right |
Effective date of registration: 20150511 Address after: Taiwan County, Hsinchu, China Hukou Zhongxing village, Guangfu Road, No. 5, building 65 Patentee after: Aptos Technology Inc. Address before: Hsinchu City, Taiwan, China Patentee before: Zhuo Enmin |
|
| CF01 | Termination of patent right due to non-payment of annual fee |
Granted publication date: 20090624 Termination date: 20150930 |
|
| EXPY | Termination of patent right or utility model |