CN101335221B - Slotted metal plate type novel semi-conductor package method - Google Patents
Slotted metal plate type novel semi-conductor package method Download PDFInfo
- Publication number
- CN101335221B CN101335221B CN2008100215046A CN200810021504A CN101335221B CN 101335221 B CN101335221 B CN 101335221B CN 2008100215046 A CN2008100215046 A CN 2008100215046A CN 200810021504 A CN200810021504 A CN 200810021504A CN 101335221 B CN101335221 B CN 101335221B
- Authority
- CN
- China
- Prior art keywords
- semi
- groove
- metallic plate
- metal plate
- chip bearing
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
Images
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/93—Batch processes
- H01L24/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
- H01L24/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
- H01L21/683—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping
- H01L21/6835—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32245—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
- H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73265—Layer and wire connectors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/91—Methods for connecting semiconductor or solid state bodies including different methods provided for in two or more of groups H01L2224/80 - H01L2224/90
- H01L2224/92—Specific sequence of method steps
- H01L2224/922—Connecting different surfaces of the semiconductor or solid-state body with connectors of different types
- H01L2224/9222—Sequential connecting processes
- H01L2224/92242—Sequential connecting processes the first connecting process involving a layer connector
- H01L2224/92247—Sequential connecting processes the first connecting process involving a layer connector the second connecting process involving a wire connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/93—Batch processes
- H01L2224/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
- H01L2224/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01005—Boron [B]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01078—Platinum [Pt]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01082—Lead [Pb]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/181—Encapsulation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
- H01L2924/191—Disposition
- H01L2924/19101—Disposition of discrete passive components
- H01L2924/19105—Disposition of discrete passive components in a side-by-side arrangement on a common die mounting substrate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/30—Technical effects
- H01L2924/301—Electrical effects
- H01L2924/30107—Inductance
Abstract
The invention relates to a novel encapsulating method for groove metal plate type semiconductors, which is mainly used for four-face footless flat patch-typed encapsulating of semiconductors. The method comprises the technical steps as follows: a metal plate is taken; metal layers are coated on the front face and the reverse face of the metal plate; the whole metal plate is separated into individual block-shaped functional pins and chip bearing bases; a metal plate provided with a groove is taken; the prepared block-shaped functional pins and the chip bearing bases are respectively implanted into corresponding grooves on the metal plate provided with the groove by an adhesive material; driven elements and chips are implanted on the functional pins and the chip bearing bases; a metal wire beating operation is carried out to the semi-finished products which are implanted with chips; the front faces of the semi-finished products after wire beating are encapsulated by a plastic sealing body; the metal plates provided with the groove at the reverse face of the semi-finished products are removed after printing; the semi-finished products are subjected to a separating operation for forming individual semiconductor encapsulated elements. The method of the invention has lower cost in materials, no chemical substance pollution and better reliability.
Description
(1) technical field
The present invention relates to a kind of method for packaging semiconductor, being mainly used in semi-conductive four sides does not have the flat SMD encapsulation of pin.Belong to the semiconductor packaging field.
(2) background technology
Traditional four sides does not have that the flat SMD encapsulation of pin adopts be at the good whole piece framework of penetration etching basic enterprising luggage sheet, routing, method for packaging semiconductor such as seal.This semiconductor packages of carrying out on the good whole piece frame foundation of penetration etching mainly has the following disadvantages:
1,, need stick one deck special glue at the back side of whole piece framework and bring the problem that produces the plastic packaging material flash when avoiding the enveloping semiconductor operation, and then increase material cost because framework is the penetration etching.
2, the lead frame after the penetration etching rocks because of the low easily generation of frame structure intensity when routing procedure, and then has influence on the interconnected stability of routing, for reliability of products is buried secret worry.
Produce flash when preventing to seal though 3 have taked special glue to bring, when the perfusion plastic packaging material, still can break through adhesive surface because of the problem of injection pressure, cause framework back side flash.Therefore usually use lower injection pressure in order to dwindle the flash area, this causes again that plastic packaging material is too loose, water absorption is high and has influence on reliability of products.
4, because the use of special adhesive tape has chemical substance and comes out the surface that pollutes chip and framework from adhesive tape, and then has influence on follow-up load, routing operation when operation.
5, have because of the viscosity of adhesive tape when removing adhesive tape on the pin that stickum remains in the lead frame back side sealing the back, and then the welding performance when having influence on follow-up surface mount.
(3) summary of the invention
The objective of the invention is to overcome above-mentioned deficiency, provide that a kind of material cost is lower, the better slotted metal plate type novel semi-conductor package method of unfailing performance.
The object of the present invention is achieved like this: a kind of slotted metal plate type novel semi-conductor package method is characterized in that described method mainly comprises following processing step:
---get a slice metallic plate,
---described metallic plate just, the back of the body two sides plate metal level,
---the described full wafer metallic plate that plates metal level is separated into the function pin and the chip bearing base of independent one by one bulk, and carries out class wrapping according to described profile and preserve, standby,
---get the metallic plate that a slice has groove, the shape of described groove is according to the size respective design of described function pin and chip bearing base,
---the function pin of preprepared bulk and chip bearing base are implanted to corresponding grooves place on the described metallic plate that has a groove respectively with bonding material,
---implant passive device on the described function pin that is coated with metal level, described passive device is resistance, electric capacity or inductance,
---on the described chip bearing base that is coated with metal level, implant chip,
---the semi-finished product of finishing chip implantation operation are played the metal wire operation,
---will be the routing described semi-finished product front of finishing carry out plastic-sealed body and seal operation, and carry out plastic-sealed body and seal the back curing operation,
---the described semi-finished product front after sealing curing prints the identification operation,
---remove the metallic plate that has groove at the described semi-finished product back side after printing, the metallic plate that has groove can give over to follow-up recycling,
---the function pin at the described semi-finished product back side behind the metallic plate that has groove and the back side of chip bearing base are removed in cleaning,
---the described semi-finished product after will cleaning carry out the cutting and separating operation, form one by one independently semiconductor packages components and parts.
Method for packaging semiconductor of the present invention is compared with the semiconductor packages components and parts that traditional employing penetration framework is made, and has following advantage:
1, the use that has a metallic plate of groove has strengthened whole structural strength better, has solved the interconnected unsettled hidden danger of routing in the former traditional handicraft.
Even 2 injection pressures are big again, owing to have the use of the metallic plate of groove, thus plastic packaging material also can't bore the generation that metallic plate has been avoided flash, has strengthened the reliability of products energy.
3, function pin and chip bearing base adopt the mode that is pre-formed and classifies and preserve, and have greatly improved the utilance of metal material, the generation of waste material when having reduced the general frame moulding, and then reduced material cost.
4, function pin and chip bearing base adopt the mode of the implantation day after tomorrow to be bonded on the metallic plate, the groove location that only need change on the metallic plate at different encapsulating structures gets final product, thereby strengthened the flexibility of package interior structure, also reduced the development cost of new product simultaneously.
5, the metallic plate that has a groove can be recycled, and has improved the utilance of material, also meets environmental protection requirement.
(4) description of drawings
Fig. 1～Figure 11 is technological process of production figure of the present invention.
Among the figure: metallic plate 1, metal level 2, function pin 3, chip bearing base 4, the metallic plate 5 that has groove, bonding material 6, chip 7, metal wire 8, plastic-sealed body 9, passive device 10.
(5) embodiment
The slotted metal plate type novel semi-conductor package method that the present invention relates to, this method mainly comprises following processing step:
---get a slice metallic plate 1, as Fig. 1,
---described metallic plate 1 just, the back of the body two sides plate metal level 2, as Fig. 2,
---mode die-cut with physics or chemical etching is separated into the function pin 3 and the chip bearing base 4 of independent one by one bulk with the full wafer metallic plate, and carries out class wrapping according to described profile and preserve, and is standby, as Fig. 3,
---get the metallic plate 5 that a slice has groove, the shape of described groove is according to the size respective design of described function pin 3 and chip bearing base 4, as Fig. 4,
---with at the bottom of the function pin 3 of preprepared bulk and the chip bearing 4 be implanted to corresponding grooves place on the described metallic plate 5 that has a groove respectively with bonding material 6 (glue special), as Fig. 5,
---implant passive device 10 on the described function pin 3 that is coated with metal level, described passive device 10 is resistance, electric capacity or inductance, as Fig. 6,
---on the described chip bearing base 4 that is coated with metal level, implant chip 7, as Fig. 6,
---the semi-finished product of finishing chip implantation operation are played metal wire 8 operations, as Fig. 7,
---will be the routing described semi-finished product front of finishing carry out plastic-sealed body 9 and seal operation, and carry out plastic-sealed body and seal the back curing operation, as Fig. 8,
---the described semi-finished product front after sealing curing prints the identification operation,
---remove the metallic plate that has groove 5 at the described semi-finished product back side after printing, as Fig. 9,
---clean with chemical agent, remove the function pin at the described semi-finished product back side behind the metallic plate that has groove and the back side of chip bearing base, chemical agent has alcohol, acetone etc., as Figure 10,
---the described semi-finished product after will cleaning carry out the cutting and separating operation, form one by one independently semiconductor packages components and parts, as Figure 11.
Claims (1)
1. slotted metal plate type novel semi-conductor package method is characterized in that described method mainly comprises following processing step:
---get a slice metallic plate,
---described metallic plate just, the back of the body two sides plate metal level,
---the described full wafer metallic plate that plates metal level is separated into the function pin and the chip bearing base of independent one by one bulk, and carries out class wrapping according to described profile and preserve, standby,
---get the metallic plate that a slice has groove, the shape of described groove is according to the size respective design of described function pin and chip bearing base,
---the function pin of preprepared bulk and chip bearing base are implanted to corresponding grooves place on the described metallic plate that has a groove respectively with bonding material,
---implant passive device on the described function pin that is coated with metal level, described passive device is resistance, electric capacity or inductance,
---on the described chip bearing base that is coated with metal level, implant chip,
---the semi-finished product of finishing chip implantation operation are played the metal wire operation,
---will be the routing described semi-finished product front of finishing carry out plastic-sealed body and seal operation, and carry out plastic-sealed body and seal the back curing operation,
---the described semi-finished product front after sealing curing prints the identification operation,
---remove the metallic plate that has groove at the described semi-finished product back side after printing,
---the function pin at the described semi-finished product back side behind the metallic plate that has groove and the back side of chip bearing base are removed in cleaning,
---the described semi-finished product after will cleaning carry out the cutting and separating operation, form one by one independently semiconductor packages components and parts.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN2008100215046A CN101335221B (en) | 2008-07-30 | 2008-07-30 | Slotted metal plate type novel semi-conductor package method |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN2008100215046A CN101335221B (en) | 2008-07-30 | 2008-07-30 | Slotted metal plate type novel semi-conductor package method |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN101335221A CN101335221A (en) | 2008-12-31 |
| CN101335221B true CN101335221B (en) | 2010-06-02 |
Family
ID=40197699
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN2008100215046A Active CN101335221B (en) | 2008-07-30 | 2008-07-30 | Slotted metal plate type novel semi-conductor package method |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN101335221B (en) |
Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101150108A (en) * | 2007-10-31 | 2008-03-26 | 日月光半导体制造股份有限公司 | Semiconductor encapsulation structure |
| CN101154650A (en) * | 2006-09-30 | 2008-04-02 | 卓恩民 | Semi-conductor packaging structure and producing method thereof |
| CN101335218A (en) * | 2008-07-30 | 2008-12-31 | 江苏长电科技股份有限公司 | Metal plate type novel semiconductor packaging method |
-
2008
- 2008-07-30 CN CN2008100215046A patent/CN101335221B/en active Active
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101154650A (en) * | 2006-09-30 | 2008-04-02 | 卓恩民 | Semi-conductor packaging structure and producing method thereof |
| CN101150108A (en) * | 2007-10-31 | 2008-03-26 | 日月光半导体制造股份有限公司 | Semiconductor encapsulation structure |
| CN101335218A (en) * | 2008-07-30 | 2008-12-31 | 江苏长电科技股份有限公司 | Metal plate type novel semiconductor packaging method |
Non-Patent Citations (2)
| Title |
|---|
| JP特开2003-347449A 2003.12.05 |
| JP特开平7-240479A 1995.09.12 |
Also Published As
| Publication number | Publication date |
|---|---|
| CN101335221A (en) | 2008-12-31 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN101335218A (en) | Metal plate type novel semiconductor packaging method | |
| CN102344110B (en) | Quad flat non-leaded package structure and method of micro electro mechanical system device | |
| MY152738A (en) | Method of making foil based semiconductor package | |
| CN101110406A (en) | Multiple chip packaging structure and its packaging method | |
| CN100565828C (en) | The glue sealing method of sensor chip | |
| KR20090028492A (en) | Integrated circuit package system with leads separated from a die paddle | |
| CN102376656A (en) | Foundation island-free packaging structure without pins on four surfaces and manufacturing method thereof | |
| CN101335221B (en) | Slotted metal plate type novel semi-conductor package method | |
| CN100568476C (en) | Slotted metal plate type semi-conductor package method | |
| CN102862946A (en) | Structure of plastic packaging premolding of hollow packaging | |
| CN106711098B (en) | IC plastic capsulation structure and preparation method thereof | |
| CN103730426A (en) | Air cavity type packaging structure and method | |
| CN105140138A (en) | Electromagnetic shielding encapsulation method and encapsulation structure | |
| CN100568477C (en) | Metal plate type semiconductor packaging method | |
| CN103606539A (en) | Frame-based flat package adopting opening-optimization technology and manufacturing process thereof | |
| CN107845600B (en) | A kind of bonded wafer level packaging structure and its process flow | |
| CN206388695U (en) | A kind of encapsulating structure of chip | |
| CN108878299A (en) | The preparation method of frame clsss integrated circuit Plastic Package is carried out by laser | |
| CN100433304C (en) | Basilar plate strip for transparent package | |
| CN101483168B (en) | Molding mode SIM card encapsulation construction based on metal frame and encapsulation method thereof | |
| CN209515637U (en) | A kind of power module architectures | |
| CN206864462U (en) | A kind of sorting-type storage chip encapsulating structure | |
| CN209071313U (en) | Chip package structure with six face formula protective layers | |
| CN206516614U (en) | SIP encapsulates rubber moulding and sealed in unit | |
| CN205406514U (en) | Preformed seals wafer -level package structure of lead frame |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C06 | Publication | ||
| PB01 | Publication | ||
| C10 | Entry into substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| C14 | Grant of patent or utility model | ||
| GR01 | Patent grant |