CN101165890A - Semiconductor package structure and manufacture method thereof - Google Patents
Semiconductor package structure and manufacture method thereof Download PDFInfo
- Publication number
- CN101165890A CN101165890A CNA2006101320322A CN200610132032A CN101165890A CN 101165890 A CN101165890 A CN 101165890A CN A2006101320322 A CNA2006101320322 A CN A2006101320322A CN 200610132032 A CN200610132032 A CN 200610132032A CN 101165890 A CN101165890 A CN 101165890A
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- China
- Prior art keywords
- semiconductor package
- pin portion
- chip
- passive device
- supporting member
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
- H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
- H01L2224/491—Disposition
- H01L2224/4912—Layout
- H01L2224/49175—Parallel arrangements
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73265—Layer and wire connectors
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01079—Gold [Au]
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/11—Device type
- H01L2924/14—Integrated circuits
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/181—Encapsulation
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/30—Technical effects
- H01L2924/301—Electrical effects
- H01L2924/30107—Inductance
Abstract
The semiconductor encapsulation structure comprises: a wire carrier, a chip, an encapsulation gel and a passive component located at the external pin area and the one of the support leg of the wire carrier; wherein, the passive3 component is exposed from the sealing gel; after the chip is encapsulated, the passive component is configured.
Description
Technical field
The present invention relates to a kind of semiconductor packaging, particularly a kind of semiconductor package of tool passive device and manufacture method thereof.
Background technology
Along with the density of manufacture of semiconductor development of technology and integrated circuit constantly increases, the pin of packaging element is more and more many, and is also more and more fast to the requirement of speed, makes to make that volume is little, speed reaches highdensity packaging element soon and become trend.
Along with the increase of electronic package configuration speed, become very important problem gradually from the noise of DC power supply circuit and ground path.Therefore, the general normal passive device that utilizes as electric capacity (capacitance), reduces power supply supply noise.Fig. 1 illustrates the cutaway view of the semiconductor package with passive device of prior art, and it comprises a lead frame 100, a chip 300, a passive device 200 and a packaging body 400.Wherein lead frame 100 comprises a chip bearing 102; Then, chip 300 is fixedly set on the chip bearing 102 with passive device 200; Come, packing colloid 400 coating chips 300, passive device 200 and part lead frame 100 be at last via testing electrical property again, classification non-defective unit and defective products.
Yet, in above-mentioned encapsulating structure, after chip 200 encapsulates with passive device 300, carry out testing electrical property again, if the testing electrical property result be bad, then each element (comprising chip 300 and passive device 200) and encapsulating material (for example packaging body 400) thereof must be scrapped and cause production cost and waste of time.On the other hand, when checking electrically bad packaging body,, be difficult for detecting electrically bad reason of package interior, be difficulty in fact so improve qualification rate by original structure because of it is a hermetically-sealed construction.Therefore, how to overcome the problems referred to above be present industry urgently need.
Summary of the invention
For addressing the above problem, one of the object of the invention provides a kind of semiconductor package and manufacture method thereof, and the mode of utilizing passive device to add is carried out the testing electrical property of chip earlier after Chip Packaging, whether decision is provided with passive device on packaging body again, can reduce passive device loss probability.
One of the object of the invention provides a kind of semiconductor package and manufacture method thereof, and Chip Packaging and passive device can be tested individually to improve the processing procedure reliability and to reduce production costs.
One of the object of the invention provides a kind of semiconductor package and manufacture method thereof, and passive device is arranged at outside the packing colloid, can directly detect the connection state of passive device, and damages passive device when avoiding packing colloid to irritate mould.
In order to achieve the above object, the semiconductor package of one embodiment of the invention comprises: a lead frame, contain a supporting member and a plurality of pin, and wherein arbitrary pin contains in one a pin portion and an outer pin portion; One chip is arranged on the supporting member, and utilizes a conduction Connection Element to electrically connect interior pin portion; One packing colloid, coating chip, conduction Connection Element and interior pin portion; And a passive device, electrically connect wantonly one or two outer pin portion.
In order to achieve the above object, the semiconductor package of another embodiment of the present invention comprises: a lead frame, contain a supporting member and a plurality of pin, and wherein supporting member has a plurality of feets, and arbitrary pin has in one a pin portion and an outer pin portion; One chip is arranged on one of feet end, and utilizes a conduction Connection Element to electrically connect interior pin portion; One packing colloid, coating chip, conduction Connection Element, interior pin portion and part feet; And a passive device, electrically connect arbitrary feet that exposes and arbitrary outer pin portion at least one of them.
In order to achieve the above object, the semiconductor package fabrication method of further embodiment of this invention comprises: a lead frame is provided, and it contains a supporting member and a plurality of pin, and wherein arbitrary pin contains in one a pin portion and an outer pin portion; One chip is set on supporting member, and electrically connects chip and interior pin portion; Form a packing colloid coating chip, conduction Connection Element and the interior pin portion of part; And a passive device is set on outer pin portion and supporting member at least wherein arbitrary.
Accompanying drawing illustrates in detail shown in below will and cooperating by specific embodiment, so that the effect that is easier to understand purpose of the present invention, technology contents, characteristics and is reached.
Description of drawings
Fig. 1 is the chip-packaging structure cutaway view of prior art.
Fig. 2 is the structure cutaway view of one of the present invention embodiment semiconductor package.
Fig. 3 A is the vertical view of first embodiment of the present invention semiconductor package.
Fig. 3 B is the vertical view of another embodiment of the present invention semiconductor package.
Fig. 4 A is the vertical view of second embodiment of the present invention semiconductor package.
Fig. 4 B is the vertical view of another embodiment of the present invention semiconductor package.
Fig. 5 A, Fig. 5 B and Fig. 5 C are each step structure cutaway view of semiconductor package manufacture method of one embodiment of the invention.
Symbol description among the figure:
20 lead frames
22 supporting members
24 pins
Pin portion in 25
26 outer pin portions
30 chips
40 conduction Connection Elements
50 packing colloids
60 passive devices
100 lead frames
102 chip bearings
200 passive devices
300 chips
400 packaging bodies
The A zone
Embodiment
It is described in detail as follows, and it is non-in order to limit the present invention that an explanation is only done in described preferred embodiment.
Figure 2 shows that the cutaway view of the semiconductor package of one of the present invention embodiment.In present embodiment, semiconductor package comprises a lead frame 20, a chip 30, a packing colloid (molding compound) 50 and one passive device 60.As shown in Figure 2, lead frame 20 contains a supporting member 22 and a plurality of pins 24, and wherein arbitrary pin 24 contains in one a pin portion 25 and an outer pin portion 26; Chip 30 in a suitable manner, for example bonding method is arranged on the supporting member 22, and utilize a conduction Connection Element 40 electrically connect in pin portion 25; One packing colloid 50, the interior pin portion 25 of coating chip 30, conduction Connection Element 40 and lead frame 20, in an embodiment, the material of packing colloid 50 comprises epoxy resin (epoxy); And a passive device 60, electrically connect the outer pin portion 26 of wantonly two lead frames 20, wherein passive device 60 comprises that resistance, electric capacity and inductance are wherein arbitrary.
The above-mentioned explanation that continues, in an embodiment, conduction Connection Element 40 is made of plurality of leads, electrically connects interior pin portion 25 on the active surface of chip 30 and the lead frame 20 in the mode of routing (wire bonding).Wherein Yin Xian material comprise gold (Au) metal, copper (Cu) matter and aluminium (Al) matter material at least one of them.
Continue with reference to figure 3A, be the vertical view of the semiconductor package of the first embodiment of the present invention.As shown in Figure 3A, lead frame 20 comprises supporting member 22 and plural pin 24, pin portion 25 and outer pin portion 26 in wherein pin 24 can be divided into, and in this embodiment, supporting member 22 is a chip bearing, in order to carry supporting chip 30.And chip 30 utilizes the interior pin portion 25 of a conduction Connection Element 40 and lead frame 20 to electrically connect with transmission information.And the regional A in the icon is shown as pre-packaged zone, packing colloid 50 (please refer to Fig. 2) but the interior pin portion 25 of coating chip 30, conduction Connection Element 40 and lead frame 20 do not polluted with protection chip 30 and conduction Connection Element 40 by extraneous grit.In addition, as shown in Figure 3A, passive device 60 is arranged in the wantonly two outer pin portions 26 of lead frame 20, and wherein passive device 60 can be arranged at the upper surface and the lower surface wherein arbitrary (being arranged at upper surface in graphic) of outer pin portion 26, and passive device 60 is exposed to outside the packing colloid 50.Because passive device 60 is arranged at outside the packing colloid 50, thus the connection state of passive device 60 can directly be detected thereafter, and packing colloid 50 damage passive devices 60 when avoiding irritating molded journey.
In another embodiment, shown in Fig. 3 B, the supporting member 22 of lead frame 20 can also be made of a plurality of feet.Utilize feet support bearing chip 30, wherein the position of feet, size, number is neither exceeds with the person of illustrating in scheming, other is any reaches the supporting mechanism that above-mentioned effect causes the firm carries chips 30 of feet of lead frame 20, also is category of the present invention place.
Please refer to Fig. 4 A, be the vertical view of the semiconductor package of the second embodiment of the present invention.Be that with the first embodiment difference supporting member of lead frame 20 has the position difference that a plurality of feets are provided with support bearing chip 30 and passive device 60.It is described in detail as follows, and chip 30 is arranged on one of feet end, and utilizes conduction Connection Element 40 to electrically connect the interior pin portion 25 of lead frames 20 with turning circuit.As shown in the figure, regional A is shown as pre-packaged zone, packing colloid 50 (please refer to Fig. 2) but the interior pin portion 25 and part feet of coating chip 30, conduction Connection Element 40, lead frame 20.According to the design of required lead frame 20 circuits, passive device 60 can be electrically connected in arbitrary feet that exposes and the arbitrary outer pin portion 26.Wherein, the feet that exposes can be the projection of an outstanding feet as illustrating among the figure, but is not limited thereto, so long as the feet that non-encapsulated colloid 50 coats also can carry passive device, is also contained by category of the present invention.All the other and the first embodiment something in common just repeat no more herein.In an embodiment, according to different feet designs, passive device 60 also can be arranged on the wantonly two adjacent feets, shown in Fig. 4 B.
Fig. 5 A, Fig. 5 B and Fig. 5 C are depicted as the structural representation of the semiconductor package manufacture method of one of the present invention embodiment.Shown in Fig. 5 A, at first, one lead frame 20 is provided, it contains a supporting member 22 and a plurality of pins 24, wherein arbitrary pin 24 contains in one a pin portion 25 and an outer pin portion 26, and the regional A in the icon is shown as pre-packaged zone, and in an embodiment, supporting member 22 can be the chip bearing or is made of plural feet; Then, shown in Fig. 5 B, one chip 30 is set in a suitable manner on supporting member 22, and electrically connect chip 30 and interior pin portion 25, in an embodiment, proper method comprises that the film or the dielectric epoxy resin that utilize viscose glue, tool viscosity fixedly are attached at chip 30 on the supporting member 22; Come again, shown in Fig. 5 C, with proper method, for example irritate the mould mode, form inner members such as a packing colloid 50 coating chips 30, conduction Connection Element 40 and interior pin portion 25, can make inner member and extraneous airtight isolation and avoid being subjected to foreign impacts or pollution, its at home and abroad pin portion 26 expose packing colloid 50, conveniently being welded on the circuit board, and then carry out 30 intended function of chip; At last, with proper method, for example the surface adhering technology (surface mounttechnology, SMT), one passive device 60 (as shown in Figure 2) is set at least wherein arbitrary of outer pin portion 26 and supporting member 22, to form structure cutaway view as shown in Figure 2.Can according to different designs the pin 24 of lead frame 20 be struck out required form, for example L type, J type or I type or the like thereafter.In an embodiment, also can carry out carrying out again behind the pin 24 punching press processing procedures SMT processing procedure of passive device 60 (as shown in Figure 2) earlier, its both orders can be decided according to actual conditions.
The above-mentioned explanation that continues, in an embodiment, chip 30 utilizes a conduction Connection Element 40, and lead-in wire for example is with routing mode and 25 electric connections of interior pin portion.In another embodiment, before passive device 60 is set, comprises more and carry out a packaging and testing step that wherein packaging and testing step comprises whether the electrical transmission of chip 30 is good after the test package.Treat that testing electrical property is normal, upper surface or the lower surface of passive device 60 in outer pin portion 26 is set again, thus, can reduce passive device loss probability.
According to above-mentioned, one of feature of the present invention can be arranged at feet, the outer pin portion of lead frame according to different circuit design passive devices or stride and establish in feet and the outer pin portion, even, passive device can be arranged at any electric property and expose the outer protuberance of packing colloid, wherein passive device can be arranged at the upper surface or the lower surface of lead frame, suitable elasticity on the processing procedure.In addition, one of feature of the present invention is provided with passive device again behind the chip testing electrical property, can improve the consume probability of process rate and minimizing passive device.
Comprehensively above-mentioned, semiconductor package of the present invention and manufacture method thereof, the mode of utilizing passive device to add can be carried out testing electrical property earlier after Chip Packaging, and whether decision is provided with passive device on packaging body again, can reduce passive device loss probability.Again, Chip Packaging and passive device can be tested individually and can improve the processing procedure reliability and reduce production costs.Moreover, passive device is arranged at outside the packing colloid, can directly detect the connection state of passive device, and damage passive device when avoiding packing colloid to irritate mould.
Above-described embodiment only is explanation technological thought of the present invention and characteristics, its purpose makes the personage who has the knack of this skill can understand content of the present invention and is implementing according to this, when can not with qualification claim of the present invention, promptly the equalization of doing according to disclosed spirit generally changes or modifies, and must be encompassed in the claim of the present invention.
Claims (23)
1. semiconductor package comprises:
One lead frame contains a supporting member and a plurality of pin, and wherein arbitrary pin contains in one a pin portion and an outer pin portion;
One chip is arranged on this supporting member, and utilizes a conduction Connection Element to electrically connect described interior pin portion;
One packing colloid coats this chip, this conduction Connection Element and described interior pin portion; And
One passive device electrically connects arbitrary two outer pin portions.
2. semiconductor package as claimed in claim 1, wherein this supporting member is a chip bearing.
3. semiconductor package as claimed in claim 1, wherein this supporting member is made of a plurality of feet.
4. semiconductor package as claimed in claim 1, wherein this passive device is exposed to outside this packing colloid.
5. semiconductor package as claimed in claim 1, wherein this conduction Connection Element comprises plurality of leads.
6. semiconductor package as claimed in claim 5, the material of wherein said lead-in wire comprise metal, copper or aluminium matter.
7. semiconductor package as claimed in claim 1, wherein the material of this packing colloid comprises epoxy resin.
8. semiconductor package as claimed in claim 1, wherein to comprise resistance, electric capacity and inductance wherein arbitrary for this passive device.
9. semiconductor package comprises:
One lead frame contains a supporting member and a plurality of pin, and wherein this supporting member has a plurality of feets, and arbitrary pin has in one a pin portion and an outer pin portion;
One chip is arranged on one of described feet end, and utilizes a conduction Connection Element to electrically connect described interior pin portion;
One packing colloid coats this chip, this conduction Connection Element, described interior pin portion and feet partly; And
One passive device, electrically connect arbitrary be exposed to the outer feet of packing colloid and arbitrary outer pin portion at least one of them.
10. semiconductor package as claimed in claim 9, wherein this passive device is exposed to outside this packing colloid.
11. semiconductor package as claimed in claim 9, wherein this passive device is arranged on wantonly one or two feet.
12. semiconductor package as claimed in claim 9, wherein this passive device is arranged in arbitrary these feets and arbitrary these outer pin portions.
13. semiconductor package as claimed in claim 9, wherein this conduction Connection Element comprises plurality of leads.
14. semiconductor package as claimed in claim 13, the material of wherein said lead-in wire comprise metal, copper or aluminium matter.
15. semiconductor package as claimed in claim 9, wherein this packing colloid material comprises epoxy resin.
16. semiconductor package as claimed in claim 9, wherein to comprise resistance, electric capacity and inductance wherein arbitrary for this passive device.
17. a semiconductor package manufacture method comprises:
One lead frame is provided, and it contains a supporting member and a plurality of pin, and wherein arbitrary pin contains in one a pin portion and an outer pin portion;
One chip is set on this supporting member, and electrically connects this chip and interior pin portion;
Form the interior pin portion that a packing colloid coats this chip, this conduction Connection Element and part; And
One passive device is set outside these on pin portion and this supporting member at least wherein arbitrary.
18. semiconductor package manufacture method as claimed in claim 17 wherein is provided with this chip and comprises the film or the dielectric epoxy resin that utilize viscose glue, tool viscosity in the method on this supporting member and fixedly be attached on this supporting member.
19. semiconductor package manufacture method as claimed in claim 17, the method that wherein electrically connects this chip and described interior pin portion comprises the routing mode of utilizing.
20. semiconductor package manufacture method as claimed in claim 17, the method that wherein forms this packing colloid comprises the mould mode of irritating.
21. semiconductor package manufacture method as claimed in claim 17, more be contained in this passive device is set before, carry out a packaging and testing step.
22. semiconductor package manufacture method as claimed in claim 21, wherein this packaging and testing step comprises the electrical of this chip of test.
23. semiconductor package manufacture method as claimed in claim 17 wherein is provided with this passive device at least wherein arbitrary method of pin portion and this supporting member outside these and comprises the surface adhering technology.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CNA2006101320322A CN101165890A (en) | 2006-10-19 | 2006-10-19 | Semiconductor package structure and manufacture method thereof |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CNA2006101320322A CN101165890A (en) | 2006-10-19 | 2006-10-19 | Semiconductor package structure and manufacture method thereof |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN101165890A true CN101165890A (en) | 2008-04-23 |
Family
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Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CNA2006101320322A Pending CN101165890A (en) | 2006-10-19 | 2006-10-19 | Semiconductor package structure and manufacture method thereof |
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| CN (1) | CN101165890A (en) |
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101834165A (en) * | 2010-05-07 | 2010-09-15 | 北京中庆微数字设备开发有限公司 | Integrated circuit chip package body |
| CN101847615A (en) * | 2010-05-12 | 2010-09-29 | 北京中庆微数字设备开发有限公司 | Integrated circuit chip package |
| CN101894822A (en) * | 2010-05-28 | 2010-11-24 | 日月光封装测试(上海)有限公司 | Lead frame band construction for semiconductor packaging |
| CN110047815A (en) * | 2015-02-18 | 2019-07-23 | 日月光半导体制造股份有限公司 | Semiconductor device packages |
-
2006
- 2006-10-19 CN CNA2006101320322A patent/CN101165890A/en active Pending
Cited By (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101834165A (en) * | 2010-05-07 | 2010-09-15 | 北京中庆微数字设备开发有限公司 | Integrated circuit chip package body |
| CN101834165B (en) * | 2010-05-07 | 2016-03-02 | 北京中庆微数字设备开发有限公司 | A kind of integrated circuit chip package |
| CN101847615A (en) * | 2010-05-12 | 2010-09-29 | 北京中庆微数字设备开发有限公司 | Integrated circuit chip package |
| CN101847615B (en) * | 2010-05-12 | 2016-02-03 | 北京中庆微数字设备开发有限公司 | Integrated circuit chip package |
| CN101894822A (en) * | 2010-05-28 | 2010-11-24 | 日月光封装测试(上海)有限公司 | Lead frame band construction for semiconductor packaging |
| CN101894822B (en) * | 2010-05-28 | 2012-07-04 | 日月光封装测试(上海)有限公司 | Lead frame band construction for semiconductor packaging |
| CN110047815A (en) * | 2015-02-18 | 2019-07-23 | 日月光半导体制造股份有限公司 | Semiconductor device packages |
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