CN205484689U - Failure analysis system - Google Patents
Failure analysis system Download PDFInfo
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- CN205484689U CN205484689U CN201521030739.3U CN201521030739U CN205484689U CN 205484689 U CN205484689 U CN 205484689U CN 201521030739 U CN201521030739 U CN 201521030739U CN 205484689 U CN205484689 U CN 205484689U
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- hole
- foil
- support plate
- metal probe
- failure analysis
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Abstract
The utility model discloses a failure analysis system, its test fixture includes the bottom plate, support plate and splint, the support plate is the layered structure, it is equipped with the perpendicular through -hole of evenly arranging to run through the support plate, two opposite flanks that run through every layer of support plate are provided with the horizontal through -hole of one deck, be equipped with in the perpendicular through -hole and be used for the connecting piece be connected with the pin by the survey chip, the connecting piece includes foil and first metal probe, first metal probe cover is equipped with elastomeric element, still include the second metal probe, and elastomeric element is fixed in wall department within the perpendicular through -hole, when being arranged in the support plate upper surface by the survey chip, splint are gently pressed on being surveyed the chip, it presses on foil to be surveyed the pin of chip, elastomeric element is the compressed together, and first metal probe and second metal probe electric connection, the test board, the test machine selectively with second metal probe electric connection to output test signal. The utility model relates to a chip that can extensively be applicable to various packaging structure carries out failure analysis's test equipment.
Description
Technical field
This utility model relates to chip failure analysis technical field, particularly relates to a kind of chip that can be widely used in various encapsulating structure and carries out the test equipment of failure analysis.
Background technology
In general, integrated circuit lost efficacy inevitable during developing, producing and use, along with product quality and reliability requirement are improved constantly by people, failure analysis work also seems more and more important, analyzed by chip failure, Integrated circuit designers can be helped to find the defect in design, not the mating or design and the problem such as improper in operation of technological parameter.The meaning of failure analysis mainly shows specifically, and the meaning of failure analysis is mainly manifested in the following aspects: failure analysis determines that the necessary means of chip failure mechanism.Failure analysis is the information that effective fault diagnosis provides necessity.Failure analysis is the design that design engineer updated or repaired chip, and be allowed to more coincide with design specification the feedback information providing necessary.Failure analysis can assess the effectiveness of different test vector, provides necessary supplementing for production test, submits necessary information basis for validation test process optimization.Failure analysis key step and content chip Kaifeng: remove IC sealing, keep the intact of chip functions simultaneously, keep die, bond pads, bond wires or even lead-frame injury-free, prepares for next step chip failure analysis experiment.SEM scanning electron microscope/EDX component analysis: include material structure analysis/Observation of Defects, elementary composition conventional micro-zone analysis, accurately measurement component size etc..Probe test: obtain the internal signal of telecommunication of IC with microprobe efficiently and easily.Radium-shine cutting: with micro laser beam line disconnection or specific region, chip upper strata.
During improving product yield, Production Engineer needs to carry out defective product electrically and physical failure analysis, thus diagnoses product.Analyzed by electrical property failure, often can find out defect position on domain, for the concrete condition of clear and definite defect, need to carry out physical failure analysis, mainly include delamination, focused ion bundle, scanning electron microscope (TEM), VC location technology and defect chemistry component analysis.Electrical property failure analysis is the premise of physical failure analysis, and physical failure analysis result is purpose and the evidence of electrical property failure analysis.In failure analysis, each step work fit applications is indispensable.
In order to determine physical failure analysis and electrical property failure analysis, need each pin of chip is attached test, and in detection industry, often run into the chip of various sizes and encapsulated type, every kind of chip needs to make fixture before test, this is a job the most loaded down with trivial details, it is therefore necessary to develops a kind of chip that can be widely used in various encapsulating structure and carries out the test equipment of failure analysis.
Utility model content
The purpose of this utility model is to provide a kind of chip that can be widely used in various encapsulating structure and carries out the test equipment of failure analysis.
To achieve these goals, the technical scheme that this utility model provides is: provide a kind of failure analysis system, including:
nullTest fixture，Described test fixture includes base plate、Support plate and clamping plate，Described support plate is hierarchy，Run through described support plate upper surface、Lower surface is provided with the vertical through hole being evenly arranged，The two relative side running through every layer of described support plate is provided with one layer of horizontal through hole，And described vertical through hole is arranged in a crossed manner with described horizontal through hole，The connector for being connected it is provided with the pin of chip under test in described vertical through hole，Described connector includes the foil being located at described support plate upper surface and the first metal probe being connected under described foil，Described first metal probe is arranged with elastomeric element，Also include the second metal probe being interspersed in described horizontal through hole，And described elastomeric element is fixed at the inwall of described vertical through hole，When chip under test is placed in described support plate upper surface，Described clamping plate are gently pressed on described chip under test，The pin of chip under test is pressed on described foil，Described elastomeric element is compressed together，And described second metal probe is selectively electrically connected with described first metal probe from described support plate side；
Tester table, described test machine is selectively electrically connected with described second metal probe, and exports test signal.
It is located at described support plate upper surface described foil dimpling.
Being additionally provided with some metal columns on described base plate, described metal column is electrically connected with described second probe, and described tester table is selectively electrically connected with arbitrary described metal column.
Described foil is structure as a whole with described first metal probe, and described elastomeric element is the boss that lower end has to described vertical through hole inwall direction projection, and described elastomeric element is spring, and described spring upper end contacts at the lower surface of described foil, described lower spring end is sticked at described vertical through hole inwall by described boss.
It is provided with electro-magnetic screen layer in described vertical through hole, and is coated with coarse insulation layer structure at described vertical through hole inwall.
Described vertical through hole is divided into upper and lower two sections, and the epimere internal diameter of described vertical through hole is slightly larger than hypomere internal diameter, and between hypomere and epimere, form ledge structure, and described spring upper end contacts at the lower surface of described foil, described lower spring end is sticked on described ledge structure.
Described vertical through hole is up big and down small round table-like structure, and described spring upper end contacts at the lower surface of described foil, and described lower spring end is sticked at described vertical through hole inwall.
Described clamping plate include cleat body and may connect to the fixed plate of described cleat body bottom, and described fixed plate offers fixing groove according to the profile of chip under test, and chip under test is embedded in described fixing groove, and described fixed plate is threadeded fixing with described cleat body.
Also include high power photographic head, described high power photographic head is located at above described clamping plate, and described cleat body and fixed plate are highly transparent structure, when described clamping plate are gently pressed on described chip under test and are pressed on described foil by the pin of chip under test, can be the best with contacting of described foil by the pin of described high power photographic head observation chip under test.
Described foil is brushed with for the tin paste layer or conductive silver slurry layer with chip under test pin good contact.
Compared with prior art, this utility model failure analysis system, due in described support plate, run through described support plate upper surface and lower surface is provided with the vertical through hole being evenly arranged, therefore, when chip under test is positioned on described support plate, the either chip of which kind of encapsulated type, all pin can be placed on the described foil on described vertical through hole, described foil is owing to being electrically connected with described first metal probe, during the most described foil pressurized, described first metal probe is connected with described second metal probe, and corresponding described second metal probe only need to be electrically connected with by described tester table, then can be to chip under test input test signal.Therefore, this utility model is the test equipment that a kind of scope of application can tested different chips is the widest, highly shortened the research and development time of test equipment and reduces the development cost of equipment.
By description below and combine accompanying drawing, this utility model will become more fully apparent, and these accompanying drawings are used for explaining embodiment of the present utility model.
Accompanying drawing explanation
Fig. 1 is the schematic diagram of this utility model one embodiment of failure analysis system.
Fig. 2 is the structural representation of an embodiment of the base plate of failure analysis system as shown in Figure 1.
Fig. 3 is the structural representation of an embodiment upper surface of the support plate of failure analysis system as shown in Figure 1.
Fig. 4 is the structural representation of an embodiment side of the support plate of failure analysis system as shown in Figure 1.
Fig. 5 is the structural representation of an embodiment of the connector of failure analysis system as shown in Figure 1.
Fig. 6 is the schematic diagram of the cross section structure of an embodiment of the vertical through hole of failure analysis system as shown in Figure 1.
Fig. 7 is the schematic diagram of the cross section structure of another embodiment of the vertical through hole of failure analysis system as shown in Figure 1.
Detailed description of the invention
With reference now to accompanying drawing, describing embodiment of the present utility model, element numbers similar in accompanying drawing represents similar element.As it has been described above, as shown in figs. 1-7, failure analysis system 1CC that this utility model embodiment provides, including:
nullTest fixture 1，Described test clip 1 tool includes base plate 10、Support plate 11 and clamping plate 12，Described support plate 11 is hierarchy，In embodiment as shown in Figures 3 and 4，Described support plate 11 is point six Rotating fields，And any one side is the most as shown in Figure 4，Run through described support plate 11 upper surface、Lower surface is provided with the vertical through hole 110 being evenly arranged，The two relative side running through every layer of described support plate 11 is provided with one layer of horizontal through hole 110b，And described vertical through hole 110 is arranged in a crossed manner with described horizontal through hole 110b，The connector 111 for being connected it is provided with the pin of chip under test in described vertical through hole 110，Described connector 111 includes the foil 1110 being located at described support plate 11 upper surface and the first metal probe 1111 being connected under described foil 1110，Described first metal probe 1111 is arranged with elastomeric element，Also include the second metal probe (not showing on figure) can being interspersed in described horizontal through hole 110b，And described elastomeric element is fixed on described vertical through hole 110 inwall，When chip under test 2 is placed in described support plate 11 upper surface，Described clamping plate 12 are gently pressed on described chip under test 2，The pin of chip under test 2 is pressed on described foil 1110，Described elastomeric element is compressed together，And described second metal probe is selectively electrically connected with described first metal probe 1111 from described support plate 11 side；In the present embodiment, described vertical through hole 110 and horizontal through hole 110b that described support plate 11 is arranged are all arrays, in these two arrays, vertical through hole 110 and the size of horizontal through hole 110b and quantity also can pre-set, and arrange according to the spacing between structure and the pin of the pin of the most common chip.nullIt should be noted that，Owing to the encapsulating structure of the chip of currently available technology is typically: dual-inline package (DIP)、Little outline packages (SOP)、Small-sized package (SOJ)、Four sides lead-in wire flat package (QFP)、BGA (BGA) structure，Any of the above encapsulating structure，No matter which kind of encapsulates，Substantially can be divided into pin is arranged to common pin shape，Or BGA shape，Only need to guarantee pin and described foil 1110 good contact，And if when chip under test 2 is placed in described foil 1110，If the area of the thickest and described foil of pin is less than pin contact surface，This chip under test 2 a pin can be contacted two adjacent described foils 1110 simultaneously，Now，The most only need to be by two adjacent described foils 1110, one of them is electrically connected with described tester table 3，Do not hinder described tester table 3 to chip under test 2 output test signal.Furthermore, it is possible to need prefabricated described base plate 10 and described support plate 11 according to test.
Tester table 3, described test machine 3 is selectively electrically connected with described second metal probe, and exports test signal.Which kind of test signal described tester table 3 exports, it is common that the chip testing sent out out by hardware description language verilog is encouraged.
It should be noted that, owing to described support plate 11 is hierarchy, and every layer be equipped with opposite flank and be equipped with described horizontal through hole 110b, as shown in Figure 4, this support plate 11 is divided into six layers, therefore, when being inserted with described first metal probe 1111 on vertical through hole 110 one of them described, it has been at best able to 24 holes and has inserted to be electrically connected with described first probe 1111 for described second probe.And if the pin of chip under test 2 is abundant, in the case of the support plate of six Rotating fields is not enough, it is also possible to by increasing the number of plies of described support plate 11, to reach the purpose connected.And under general case, the external diameter of described second metal probe is greater than the external diameter of described first metal probe 1111, and one can be provided with for carrying out the bayonet socket of clamping with described first metal probe 1111 at the end of described second metal probe, allow described first metal probe be electrically connected with in being just placed in described bayonet socket, the most just enable to described first metal probe 1111 and electric connection is better achieved with described second metal probe.In addition, owing to each surface of described support plate 11 is all to have via-hole array, the purpose of through hole is to insert described first metal probe 1111 or the second metal probe, and the aperture of these through holes is all smaller, in actual production, perforate is preferably with laser boring, it is ensured that it is sufficiently small that aperture can be done.
In one embodiment, it is located at described support plate 11 upper surface described foil 1110 dimpling.The purpose arranged by described foil 1110 dimpling is that the pin enabling to chip under test 2 preferably contacts with described foil 1110, and it is bad to better discriminate between which part contact, such as whether there is the situation that a pin pushes down the described foil 1110 of correspondence the most over the ground in ratio.
In one embodiment, as in figure 2 it is shown, be additionally provided with metal column 102 on described base plate 10, described metal column is electrically connected with described second probe, and described tester table 3 is selectively electrically connected with arbitrary described metal column 102.Described metal column 102 can be threadingly attached on described base plate 10, can be unloaded down by described metal column 102 at ordinary times, be loaded onto again, be convenient for carrying and preserve when needs use.
In one embodiment, described foil 1110 is structure as a whole with described first metal probe 1111, and described elastomeric element is the boss 1113 that lower end has to described vertical through hole 110 inwall direction projection, and described elastomeric element is spring 1112, and described spring 1112 upper end contacts at the lower surface of described foil 1110, described spring 1112 lower end is sticked at described vertical through hole 110 inwall by described boss 1113.
In one embodiment, it is provided with electro-magnetic screen layer in described vertical through hole 110, and is coated with coarse insulation layer structure at described vertical through hole 110 inwall.By arranging described electro-magnetic screen layer, can mutually shield the electromagnetic interference between adjacent described first metal probe 1111, and described insulation layer structure is able to ensure that between described first metal probe 1111 and described support plate 11 holding insulation, coarse interior wall construction then can ensure that described boss 1113 can be sticked at described vertical through hole 110 inwall well.
In one embodiment, it is illustrated in figure 5 the schematic diagram of the cross section structure of an embodiment of vertical through hole 110.Described vertical through hole 110 is divided into upper and lower two sections, and the epimere internal diameter of described vertical through hole 110 is slightly larger than hypomere internal diameter, and between hypomere and epimere, form ledge structure 1101, and described spring 1112 upper end contacts at the lower surface of described foil 1110, described spring 1112 lower end is sticked on described ledge structure 1101.It it is i.e. the epimere that described spring 1112 is limited in described vertical through hole 110, in the present embodiment, described vertical through hole 110 epimere and hypomere must assure that as coaxial configuration, and due to described vertical through hole 110 upper and lower two sections for die sinking can be separated, then fixing or threaded fixing by pasting.
In one embodiment, it is illustrated in figure 6 the cross section structure schematic diagram of another embodiment of vertical through hole 110.Described vertical through hole 110 is up big and down small round table-like structure, and described spring 1112 upper end contacts at the lower surface of described foil 1110, and described spring 1112 lower end is sticked at described vertical through hole 110 inwall.The present embodiment is compared in embodiment as shown in Figure 5, and its processing and making process is eased, but higher to the mechanical property requirements of described support plate 11 material, needs more robust material.
In one embodiment, as shown in Figure 1, described clamping plate 12 include cleat body 121 and may connect to the fixed plate 122 of described cleat body 121 bottom, described fixed plate 122 offers fixing groove according to the profile of chip under test 2, and chip under test 2 is embedded in described fixing groove, described fixed plate 122 is threadeded fixing with described cleat body 121.By described clamping plate 12 being divided into two-part structure, therefore, every time for different model, the chip under test 2 of size, only described fixed plate 122 need to be transformed, it is possible to be effectively reduced development difficulty and the development cost of masterplate.
In one embodiment, as shown in Figure 1, also include high power photographic head 4, described high power photographic head 4 is located at above described clamping plate 12, and described cleat body 121 and fixed plate 122 are highly transparent structure, when described clamping plate 12 are gently pressed on described chip under test 2 and are pressed on described foil 1110 by the pin of chip under test 2, the pin of chip under test 2 can be observed by described high power photographic head 4 the best with contacting of described foil 1110.Described high power photographic head 4 must connect the computer combined with display and use, in addition, in the present embodiment, if running into small-sized chip under test 2, can directly fix with in described fixed plate 122 with it, be placed on described foil 1110, the most described fixed plate 122 does not connect described cleat body 121, directly observing thus by described high power photographic head 4 and be directed at, its effect is more preferable.
In one embodiment, described foil 1110 is brushed with for the tin paste layer or conductive silver slurry layer with chip under test 2 pin good contact.By described tin paste layer or conductive silver slurry layer, it is possible to the performance in electrical contact being greatly enhanced between chip under test 2 and described foil 1110.Applicant, in long-term operating process, finds that it is splendid for brushing described tin paste layer or conductive silver slurry layer to improve the effect of performance in electrical contact, is especially suitable for small size chip under test 2.
In conjunction with Fig. 1-7, compared with prior art, this utility model failure analysis system 100, due in described support plate 11, run through described support plate 11 upper surface and lower surface is provided with the vertical through hole 110 being evenly arranged, therefore, when chip under test 2 is positioned on described support plate 11, the either chip of which kind of encapsulated type, all pin can be placed on the described foil 1110 on described vertical through hole 110, described foil 1110 is owing to being electrically connected with described first metal probe 1111, during the most described foil 1110 pressurized, described first metal probe 1111 rises with described second metal probe and is connected, and corresponding described second metal probe only need to be electrically connected with by described tester table 3, then can be to chip under test 2 input test signal.Therefore, this utility model is the test equipment that a kind of scope of application can tested different chips is the widest, highly shortened the research and development time of test equipment and reduces the development cost of equipment.
Above disclosed it is only preferred embodiment of the present utility model, certainly can not limit the interest field of this utility model, the equivalent variations therefore made according to this utility model claim with this, still belong to the scope that this utility model is contained.
Claims (8)
1. a failure analysis system, the failure analysis for chip is tested, it is characterised in that including:
nullTest fixture，Described test fixture includes base plate、Support plate and clamping plate，Described support plate is hierarchy，Run through described support plate upper surface、Lower surface is provided with the vertical through hole being evenly arranged，The two relative side running through every layer of described support plate is provided with one layer of horizontal through hole，And described vertical through hole is arranged in a crossed manner with described horizontal through hole，The connector for being connected it is provided with the pin of chip under test in described vertical through hole，Described connector includes the foil being located at described support plate upper surface and the first metal probe being connected under described foil，Described first metal probe is arranged with elastomeric element，Also include the second metal probe can being interspersed in described horizontal through hole，And described elastomeric element is fixed at the inwall of described vertical through hole，When chip under test is placed in described support plate upper surface，Described clamping plate are gently pressed on described chip under test，The pin of chip under test is pressed on described foil，Described elastomeric element is compressed together，And described second metal probe is selectively electrically connected with described first metal probe from described support plate side；
Tester table, described test machine is selectively electrically connected with described second metal probe, and exports test signal；
It is located at described support plate upper surface described foil dimpling；
Being additionally provided with some metal columns on described base plate, described metal column is electrically connected with described second metal probe, and described tester table is selectively electrically connected with arbitrary described metal column.
2. failure analysis system as claimed in claim 1, it is characterized in that, described foil is structure as a whole with described first metal probe, and described elastomeric element is the boss that lower end has to described vertical through hole inwall direction projection, and described elastomeric element is spring, and described spring upper end contacts at the lower surface of described foil, described lower spring end is sticked at described vertical through hole inwall by described boss.
3. failure analysis system as claimed in claim 2, it is characterised in that be provided with electro-magnetic screen layer in described vertical through hole, and be coated with coarse insulation layer structure at described vertical through hole inwall.
4. failure analysis system as claimed in claim 2, it is characterized in that, described vertical through hole is divided into upper and lower two sections, and the epimere internal diameter of described vertical through hole is slightly larger than hypomere internal diameter, and between hypomere and epimere, form ledge structure, and described spring upper end contacts at the lower surface of described foil, described lower spring end is sticked on described ledge structure.
5. failure analysis system as claimed in claim 2, it is characterised in that described vertical through hole is up big and down small round table-like structure, and described spring upper end contacts at the lower surface of described foil, and described lower spring end is sticked at described vertical through hole inwall.
6. failure analysis system as claimed in claim 1, it is characterized in that, described clamping plate include cleat body and may connect to the fixed plate of described cleat body bottom, described fixed plate offers fixing groove according to the profile of chip under test, and chip under test is embedded in described fixing groove, described fixed plate is threadeded fixing with described cleat body.
7. failure analysis system as claimed in claim 6, it is characterized in that, also include high power photographic head, described high power photographic head is located at above described clamping plate, and described cleat body and fixed plate are highly transparent structure, when described clamping plate are gently pressed on described chip under test and are pressed on described foil by the pin of chip under test, can be the best with contacting of described foil by the pin of described high power photographic head observation chip under test.
8. failure analysis system as claimed in claim 1, it is characterised in that described foil is brushed with for the tin paste layer or conductive silver slurry layer with chip under test pin good contact.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201521030739.3U CN205484689U (en) | 2015-12-10 | 2015-12-10 | Failure analysis system |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201521030739.3U CN205484689U (en) | 2015-12-10 | 2015-12-10 | Failure analysis system |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN205484689U true CN205484689U (en) | 2016-08-17 |
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Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201521030739.3U Expired - Fee Related CN205484689U (en) | 2015-12-10 | 2015-12-10 | Failure analysis system |
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| CN (1) | CN205484689U (en) |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN107102179A (en) * | 2017-06-02 | 2017-08-29 | 深圳市同创精密自动化设备有限公司 | A kind of test fixture of PCB soft boards |
| CN112269045A (en) * | 2020-10-12 | 2021-01-26 | 上海华力集成电路制造有限公司 | Test structure for failure analysis |
| CN112269045B (en) * | 2020-10-12 | 2024-06-07 | 上海华力集成电路制造有限公司 | Test structure for failure analysis |
-
2015
- 2015-12-10 CN CN201521030739.3U patent/CN205484689U/en not_active Expired - Fee Related
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN107102179A (en) * | 2017-06-02 | 2017-08-29 | 深圳市同创精密自动化设备有限公司 | A kind of test fixture of PCB soft boards |
| CN107102179B (en) * | 2017-06-02 | 2023-09-29 | 深圳市同创精密自动化设备有限公司 | Test fixture of PCB soft board |
| CN112269045A (en) * | 2020-10-12 | 2021-01-26 | 上海华力集成电路制造有限公司 | Test structure for failure analysis |
| CN112269045B (en) * | 2020-10-12 | 2024-06-07 | 上海华力集成电路制造有限公司 | Test structure for failure analysis |
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Legal Events
| Date | Code | Title | Description |
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| C14 | Grant of patent or utility model | ||
| GR01 | Patent grant | ||
| TR01 | Transfer of patent right | ||
| TR01 | Transfer of patent right |
Effective date of registration: 20170726 Address after: 201114 Shanghai City, Pujiang, the new town of Victoria Road, building No. 777, No. 5, building Patentee after: Shanghai Hua Yue Yue Yue Material Technology Co., Ltd. Address before: 518101 Guangdong, Shenzhen Province, Baoan District District, Wei Wei Industrial Park, building C, 70 Patentee before: CENTRE TESTING INTERNATIONAL GROUP CO., LTD. |
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| CF01 | Termination of patent right due to non-payment of annual fee | ||
| CF01 | Termination of patent right due to non-payment of annual fee |
Granted publication date: 20160817 Termination date: 20191210 |