CN100521172C - 半导体器件及其制造方法 - Google Patents
半导体器件及其制造方法 Download PDFInfo
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Abstract
本发明的半导体器件是在半导体基板(1)的表面形成与内部电路连接的电极焊盘(2),在电极焊盘(2)的周围接近电极焊盘(2)形成布线(6),并形成覆盖电极焊盘(2)的周边部分与布线(6)与半导体基板(1)表面的保护膜(4),在所述电极焊盘(2)上形成金属突起电极(3),使得周边部分放置在布线(6)上的保护膜(4)上。根据这样,由于接近电极焊盘(2)形成布线(6),因此覆盖电极焊盘(2)的周边部分及其周围区域的保护膜(4)形成得比较平坦,金属突起电极(3)放置在前述比较平坦的保护膜(4)上而形成的凸起部分(3a)具有平坦的表面。因而,即使电极焊盘(2)小,也能够在金属突起电极(3)的表面充分确保平坦的区域,能够确保利用COG安装等的各向异性导电片等的连接稳定性。
Description
技术领域
本发明涉及半导体器件及其制造方法。
背景技术
近年来,由于笔记本电脑及液晶型电视机的普及,液晶面板的需要大大增加,使液晶面板工作用的半导体器件的需要也大大增加。另一方面,为了使笔记本电脑等达到普及价格,迫切要求降低液晶面板及半导体器件的成本,多采用像TCP(Tape Carrier Package,载带封装)安装或COG(Chip On Glass,玻板上芯片)安装那样使用各向异性导电片等将半导体器件直接安装在安装基板上的方法。在TCP安装及COG安装中,安装基板与半导体器件的外部电极的连接稳定性是重要的技术课题。
图10所示为半导体器件(半导体芯片)上作为外部电极的输入输出焊盘的一般性配置,是在形成半导体元件、构成电路的有源区域21的外侧即半导体器件22的区边区域设置输入输出焊盘23。输入输出焊盘23如图11的放大图所示,至少具有在半导体基板1的表面形成的铝合金主体的电极焊盘2、以及在其上为了与外部引线连接而形成的金或镍等的金属突起电极3。另外,为了用电镀技术等形成金属突起电极3,预先形成保护膜4,使其一直覆盖至电极焊盘2的周边部分。利用电极焊盘2与金属突起电极3的材料组合,形成阻挡金属层5。另外图中省略一点,为了提高TCP与引线连接的可靠性,也有的情况下使金属突起电极3与电极焊盘2相比至少沿一个方向延长增大,以增大连接面积(例如参照特开2001—110833号公报)。
但是,若如上所述形成覆盖电极焊盘2的周边部分的保护膜4,则在没有用保护膜4覆盖的电极焊盘2的表面与保护膜4的表面之间产生台阶,在其上形成的金属突起电极3的表面产生台阶。即,由于是在有台阶的电极焊盘2及保护膜4的表面利用电镀技术等形成金属突起电极3,因此在金属突起电极3形成凸起部分3a及凹陷部分3b。虽然说产生了台阶,但由于能够稳定形成金属突起电极3的突起形状的技术除电镀以外还没有,因此目前的现状还使用该方法。
但是若存在台阶,则采用COG安装等,在将金属突起电极3通过各向异性导电片在安装基板上进行连接时,各向异性导电片的导电粒子往往产生能够紧贴的部分及不能紧贴的部分,在导电粒子没有充分紧贴时,半导体器件与安装基板的连接电阻将大于设计值,或产生差异。作为该解决的措施,虽然有一种方法是例如使导电粒子足够大,超过台阶以上,但由于与相邻的金属突起电极3短路的可能性很高,因此难以适用于窄间距的半导体器件。
本发明正是为解决上述问题,其目的在于提高能够确保外部连接用的金属突起电极连接稳定性的半导体器件及其制造方法。
发明内容
为了解决上述问题,本发明的半导体器件,在半导体基板的表面形成与内部电路连接的电极焊盘,同时在所述焊盘的周围接近所述电极焊盘形成布线,并形成覆盖所述电极焊盘的周边部分及布线及半导体基板表面的保护膜,在所述电极焊盘上形成金属突起电极,使得周边部分放置在所述布线上的保护膜上。
根据上述结构,由于接近电极焊盘形成布线,因此覆盖电极焊盘的周边部分及其周围区域的保护膜形成得比较平坦,而金属突起电极的周边部分放置在该比较平坦的保护膜上,这样就具有平坦的表面。因而,即使电极焊盘小,也能够在金属突起电极的表面充分确保平坦的区域,能够确保利用各向异性导电片等的连接稳定性。
可以在多个电极焊盘的周围形成布线,并形成覆盖各电极焊盘的周边部分及布线及半导体基板表面的保护膜,形成金属突起电极,使得连接所述多个电极焊盘。
可以沿电极焊盘的外周配置一条或多条布线,形成金属突起电极,使得周边部分放置在所述一条或多条布线上及电极焊盘上的保护膜上。
另外,可以形成一条或多条布线,使得包围电极焊盘的整个外周,形成金属突起电极,使得周边部分放置在所述一条或多条布线上的保护膜上。
也可以在相邻的电极焊盘间也形成布线。
最好是金属突起电极的外端部配置在比根据排列的电极焊盘及布线的最外端部与其外侧的半导体基板表面的台阶在保护膜的表面形成的倾斜部分更内侧。
最好是在电极焊盘的外侧隔开适当间隔形成多条布线,在电极焊盘与布线的间隙及布线相互之间的间隙之上的保护膜表面形成的多个倾斜部分互相连接。
最好是在电极焊盘与布线的间隙或形成多条的布线相互之间的间隙之上的保护膜表面形成的倾斜部分的台阶为1μm及1μm以下。
可以是矩形金属突起电极的三个周边部分放置在单一电极焊盘或布线上的保护膜上。
最好是放置金属突起电极的三个周边部分的电极焊盘的外端部或布线配置在沿半导体基板的外周边缘的方向。
最好是放置金属突起电极的三个周边部分的电极焊盘的外端部或布线位于半导体基板的外周边缘的附近。
可以是布线包围电极焊盘而连续形成。
本发明的半导体器件制造方法,进行在表面具有电极焊盘及在所述电极焊盘的周围接近所述电极焊盘而形成的布线的半导体基板上形成覆盖所述电极焊盘的周边部分及布线及半导体基板表面的保护膜的工序、以及在从所述电极焊盘上到布线上的保护膜的整个区域使金属材料生长而形成金属突起电极的工序。
附图说明
图1为本发明一实施形态的半导体器件的输入输出焊盘部分的剖面图。
图2为图1的半导体器件的输入输出焊盘部分的平面图。
图3为说明图1的半导体器件的制造方法的工序图。
图4为本发明的其它输入输出焊盘部分的电极焊盘、布线、金属突起电极的布图。
图5为本发明的另外其它输入输出焊盘部分的电极焊盘、布线、金属突起电极的布图。
图6为本发明的另外其它输入输出焊盘部分的电极焊盘、布线、金属突起电极的布图。
图7为本发明的另外其它输入输出焊盘部分的电极焊盘、布线、金属突起电极的布图。
图8为本发明的另外其它输入输出焊盘部分的电极焊盘、布线、金属突起电极的布图。
图9为本发明的另外其它输入输出焊盘部分的剖面图。
图10所示为以往的半导体器件的简要结构成平面图。
图11为以往的半导体器件的输入输出焊盘部分的剖面图。
具体实施方式
以下参照附图说明本发明的实施形态。
图1所示为本发明一实施形态的半导体器件的输入输出焊盘部分的结构剖面图,图2为该输入输出焊盘部分的平面图。输入输出焊盘一般是在半导体器件(半导体芯片)中位于形成晶体管、电阻、电容、二极管及布线等半导体元件并构成内部电路的有源区域的外侧即半导体基板的周边区域(参照图10)。
在图1及图2中,与内部电路连接的电极焊盘2及多条布线6在同一层形成,至少形成一层覆盖电极焊盘2的周边部分及布线6及半导体基体1表面的保护膜4。在从保护膜4的开口部分4a露出的电极焊盘2上及保护膜4上,隔着阻挡金属层5形成金属突起电极3。也有时在电极焊盘2的下方的半导体基板1内,设置形成晶体管等的有源区域7。
多条布线6包围矩形电极焊盘2、而且接近电极焊盘2形成。这些布线6具有与电极焊盘2相同的厚度,而且互相平行隔着间隔配置。详细来说,在矩形电极焊盘2的互相平行的一对边的各自附近,配置沿各边延伸的布线6,在另一对边的各自附近,形成沿与各边相交的方向延伸的布线6。另外,用布线6及电极焊盘2占有矩形区域。各布线6相对于电极焊盘2电气分离或连接,与内部电路连接,或形成作为与内部电路完全不连接的虚设布线。
保护膜4以近似均匀的膜厚形成在电极焊盘2的周边部分及布线6及其周围的半导体基板1的表面之上,在电极焊盘2、布线6与半导体基板1的表面的边界部分呈倾斜形状。
金属突起电极3是这样形成的,它与电极焊盘2的中心对齐,并使得外端位于比各布线6的外端部与半导体基板1的表面的边界部分的保护膜4的倾斜部分4b(以下仅称为保护膜4的倾斜部分4b)更内侧。这里用L1表示金属突起电极3与倾斜部分4b的距离。金属突起电极3的表面取决于从保护膜4的开口部分4a露出的电极焊盘2的表面与保护膜4的表面的高度之差,呈凹凸状。以下,将放置在保护膜4上的高位部分称为凸起部分3a,将放置在从开口部分4a露出的电极焊盘2上的低位部分称为凹陷部分3b。
下面根据图3的工序图说明上述半导体器件的制造方法。
如图3A所示,在已经形成半导体元件的半导体基板1上,利用溅射或CVD技术等形成电极焊盘2及布线6。作为电极焊盘2及布线6的材料,可以使用以铝或铜为主要成分的导电体比较合适。
然后,如图3B所示,形成具有开口部分4a的保护膜4。该保护膜4可利用CVD技术形成,并利用光刻及干法刻蚀等技术形成图形。作为保护膜4的材料,除了SiN以外,可以使用以Si或Ga等为主要成分的材料比较合适。另外,若用CVD法等成膜,则仿照衬底的图形形成薄膜,但在边界部分不完全仿照图形,而形成倾斜部分4b等。
然后,如图3C所示,在电极焊盘2及保护膜4的整个表面,利用溅射技术等形成所希望厚度的阻挡金属层5。对于阻挡金属层5,除了Ti以外,可以使用TiW、W、Pd、Cr等材料。
然后,如图3D所示,在电极焊盘2上隔着阻挡金属层5形成金属突起电极3。该金属突起电极3是如上所述形成的,使得外端位于比保护膜4的倾斜部4b更内侧。为了在所希望的位置以所希望的尺寸形成金属突起电极3,一般采用光刻及电镀等技术。这里,将阻挡金属层5作为种层,使镀层生长,形成金属突起电极3的图形,并将金属突起电极3作为掩膜,对金属突起电极3的更外周侧的阻挡金属层5进行腐蚀。对于金属突起电极3可以使用金或镍等材料。
另外,由于根据电极焊盘2与金属突起电极3的材料组合情况,在金属突起电极3形成时,会产生电极焊盘2的溶解等,因此为了避免这种情况,最好使阻挡金属层5介于其中。
在这样的输入输出焊盘部分中,由于金属突起电极3形成在此保护膜4的倾斜部分4b的更内侧,因此其凹凸形状大概仅根据保护膜4的开口部分4a的台阶而形成的。由于在布线6相互之间的间隙及电极焊盘2与布线6的间隙上的保护膜4的表面所形成的台阶小,几乎不受其影响。因此,金属突起电极3的凸起部分3a的上表面与不存在接近电极焊盘2的布线的以往结构相比,面积增大而且近似平坦。因而,在与玻璃基板等安装基板之间配置的各向异性导电片中的导电填料的接触概率升高,能够实现稳定的接合。在从金属突起电极3的表面侧加上载荷进行安装时,保护膜4也不容易产生裂纹等不良情况,能够实现有高稳定电阻值的安装。由于安装时的载荷由电极焊盘2及布线承受,因此对于电极焊盘2的下方的有源区域7的影响也很少。
下面举出图1及图2所示的输入输出焊盘部分的具体例子。取电极焊盘2为40μm×40μm的大小,布线6为30μm宽度,与电极焊盘2的间隔为1μm,分布以900nm厚度形成,在其上以约1000nm厚度形成保护膜4,在其上以200nm厚度形成阻挡金属层5,再在其上以17μm厚度形成金属突起电极3,使得外端位于比保护膜4的倾斜部分4b更内侧2μm。
其结果,对于保护膜4虽然产生根据布线相互之间的间隙而形成的台阶300nm,但位于该台阶上的金属突起电机及3的凸起部分3a的上表面没有特别形成凹凸。在将具有该电极结构的半导体器件从金属突起电极3的表面侧加上200N/mm2的载荷进行安装的结果,保护膜4没有产生裂纹等不良情况,能够很好地接合。
图4至图8所示为本发明有关的其它输入输出焊盘部分的电极焊盘、布线、金属突起电极的布图。由于保护膜4及阻挡金属层5的配置与图1相同,因此省略图示。
在图4所示的输入输出焊盘中,在矩形电极焊盘2的三边配置布线6,在这些电极焊盘2及布线6之上配置金属突起电极3。2a表示电极焊盘2从保护膜的露出部分。在该电极结构中也与图1所示的相同,在比保护膜4的倾斜部分4b的更内侧形成金属突起电极3,通过这样能够得到与图1所示的电极结构相同的效果。在该结构中,是将电极焊盘2的一部分引出在金属突起电极3以外,则电极焊盘2及布线6的走线自由度也提高。
在图5所示的输入输出焊盘中,在围绕矩形电极焊盘2的周围形成的多条布线6内,将1条布线6a沿半导体基板1的端部1a配置,在该布线6a及比它更位于基板内侧的电极焊盘2及布线6之上配置金属突起电极3。在该电极结构中也与图1所示的相同,在此保护膜4倾斜部分4b的更内侧形成金属突起电极3,通过这样能够得到与图1所示的电极结构相同的效果。
在图6所示的输入输出焊盘中,将矩形电极焊盘2沿半导体基板1的端部1a配置,在该电极焊盘2及比它更配置在基板内侧的布线6之上配置金属突起电极3。在该电极结构中也与图1所示的相同,在此保护膜4的倾斜部4b的更内侧形成金属突起电极3,通过这样能够得到与图1所示的电极结构相同的效果。
再有,这些图5及图6所示的输入输出焊盘,由于是采用将金属突起电极3的三个周边部分放置在沿半导体基板1的端部1a形成的布线6a或电极焊盘2上的保护膜4上,因此在用TCP等带状基板安装中对付因半导体芯片与带状基板之间的垫膨胀系数差而产生的剥离应力是有效的。即,由于该剥离力是从半导体芯片的外侧向内侧产生的,因此对金属突起电极3的下部也作用了剥离力,若该部位有不连续部分,则容易产生裂纹等,但在图5及图6所示的结构中,由于沿半导体基板1的端部1a的布线6a或电极焊盘2没有不连续部分,因此难以产生裂纹等。
在图7所示的输入输出焊盘中,配置方形框状的布线6,使其包围矩形电极焊盘2,在该电极焊盘2及布线6之上配置金属突起电极3。在该电极结构中也与图1所示的相同,在比保护膜4的倾斜部分4b的更内侧形成金属突起电极3,通过这样能够得到与图1所示的电极结构相同的效果。再有在该结构中,由于布线6不存在不连续部位,因此金属突起电极3的凸起部分3a的上表面平坦度更高。
在图8所示的输入输出焊盘中,接近两个电极焊盘2A及2B的周围配置多条布线6,在电极焊盘2A及2B和布线6之上配置金属突起电极3。详细来说,在两个电极焊盘2A与2B之间,配置在沿其相对的各边的方向沿伸的布线6b,配置多条布线6,使其包围一个电极焊盘2A的剩下的三边,沿另一个电极焊盘2B的剩下的两边配置布线6。
在该电极结构中也与图1所示的相同,在比保护膜4的倾斜部4b的更内侧形成金属突起电极3,通过这样能够得到与图1所示的电极结构相同的效果。再有在该结构中,由于金属突起电极3位于两个电极焊盘2A与2B之上,因此在从保护膜4露出的电极焊盘2的露出部分2Aa及2Ba较小时,金属突起电极3的接合稳定性也增加,金属突起电极3的表面平坦区域也增大。另外,布线6b也可以是与电极焊盘2A及2B和另外的电路电气连接。
在图9所示的输入输出焊盘部分中,电极焊盘2的周围的多条布线6分别形成宽度窄而且间隔小的布线。因此,在从电极焊盘2的周边部分至多条布线6的外侧的半导体基板1表面连续形成的保护膜4上,在距离电极焊盘2最远的布线6的外端部与半导体基板1表面的边界部分形成倾斜部分4b,除此之外形成与布线6相互之间的间隙或配线6与电极焊盘2之间的间隙和保护膜4的膜厚相应的多个倾斜部分4c。这些多个倾斜部分4C由于前述间隙非常小,因此连成锯齿状。
该倾斜部4C的保护膜5的台阶最好取为1μm及1μm以下。若形成超过1μm的台阶,则金属突起电极3的凸起部分7也会形成凹凸。若台阶为1μm及1μm以下,则在通过电镀形成金属突起电极3时能够吸收凹凸。如下所述,在倾斜部分4C相互之间连接的情况下,台阶比较小,在金属突起电极3的凸起部分7难以形成明显的凹凸。
在这样形成的输入输出焊盘部分中,金属突起电极3的凸起部分3a的上表面与不存在接近电极焊盘2的布线6的以往结构相比,面积增大而且近似平坦。因此,在与玻璃基板等安装基板之间配置的各向异性导电片中的导电填料的接触概率增高,能够实现稳定的接合。在从金属突起电极3的表面侧加上载荷进行安装时,保护膜4也不容易产生裂纹等不良情况,能够实现有高稳定电阻值的安装。
下面举出图9所示的输入输出焊盘部分的具体例子。取电极焊盘2为40μm×40μm的大小,布线6为1μm宽度,相邻的布线6与电极焊盘2的间隙为1μm,分别以900nm厚度形成,在其上以约1000nm厚度形成保护膜4,在其上以200nm厚度形成阻挡金属层5、再在其上以17μm厚度形成金属突起电极3,使得外端位于比保护膜4的倾斜部分4b更内侧1μm。
其结果,对于保护膜4虽然产生根据电极焊盘2与布线6的间隙及布线6相互之间的间隙的台阶300nm,但位于该台阶上的金属突起电极3的凸起部分3a的上表面沿有特别形成凹凸。在将具有该电极结构的半导体器件从金属突起电极3的表面侧加上200N/mm2的载荷进行安装的结果,保护膜4没有产生裂纹等不良情况,能够很好地接合。
如上所述,本发明的各半导体器件由于这样形成外部连接用的金属突起电极,使得周边部分也放置在接近电极焊盘的布线上,因此能够比较平坦地形成覆盖电极焊盘的周边部分及其周围区域的保护膜,能够使得放置在该该比较平坦的保护膜上的金属突起电极的周边部分具有平坦的表面。因而,即使电极焊盘小,金属突起电极的表面也能够充分确保平坦的区域,能够确保用COG安装等的各向异性导电片等形成的连接稳定性。
通过在多个电极焊盘的周围形成布线,并形成金属突起电极,使得连接前述多个电极焊盘,则金属突起电极的接合稳定性增加,金属突起电极的表面平坦区域也增加。
通过将金属突起电极的外端部配置在比根据排列的电极焊盘及布线的最外端部与其外侧的半导体基板表面的台阶在保护膜的表面形成的倾斜部分更内侧,则也能够抑制在COG安装时因对压力的应力而产生的保护膜的裂纹。
通过设定间隙及膜厚,使得在电极焊盘与布线的间隙及布线相互之间的间隙之上的保护膜表面形成的多个倾斜部分连续,则由于该倾斜部分的台阶比较小,被在其上形成的金属突起电极吸收,因此能够确保金属突起电极的表面平坦度。
通过形成金属突起电极,使得三个周边部分放置在单一电极焊盘或布线上的保护膜上,则布线的走线性能提高。
通过包围电极焊盘连续形成布线,则因没有布线的不连续部分,因此能够提高金属突起电极的表面平坦度。
Claims (5)
1、一种半导体器件,其特征在于,
所述半导体器件设置有输入输出焊盘,所述输入输出焊盘由电极焊盘、覆盖所述电极焊盘的周边部分的保护膜和在所述电极焊盘上方形成的金属突出电极组成,
在所述电极焊盘的周围接近所述电极焊盘配置一条或多条布线,所述布线被所述保护膜所覆盖,
所述金属突起电极的周边部分与倾斜部分相比位于更内侧,所述倾斜部分根据所述排列的电极焊盘及布线的最外端部与其外侧的半导体基板表面之间的台阶形成在所述保护膜的表面,同时,所述金属突起电极的周边部分位于所述布线的上方,或者位于所述电极焊盘和所述布线的上方,
所述金属突起电极在该金属突起电极背对着所述电极焊盘的表面具有凹陷部分和凸起部分,
所述凹陷部分位于所述保护膜的开口部的上方,
所述凸起部分位于所述电极焊盘的周边部分、所述电极焊盘与所述布线之间的间隙和所述布线的上方,
所述凸起部分的上面实质上是平坦的。
2、如权利要求1所述的半导体器件,其特征在于,
在多个电极焊盘的周围形成布线,并在所述多个电极焊盘上方形成一个金属突起电极。
3、如权利要求1所述的半导体器件,其特征在于,
电极焊盘或者布线的一端边形成在半导体基板上,所述电极焊盘或者布线的一端边相对着所述半导体基板的一边。
4、如权利要求1所述的半导体器件,其特征在于,
配置布线使得包围电极焊盘的整个外周。
5、如权利要求1所述的半导体器件,其特征在于,
在保护膜和电极焊盘的上面形成阻挡金属层,所述金属突起电极形成在所述阻挡金属层的上面。
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-
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