CN100514676C - 应变沟道mos元件 - Google Patents

应变沟道mos元件 Download PDF

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CN100514676C
CN100514676C CNB2007101380239A CN200710138023A CN100514676C CN 100514676 C CN100514676 C CN 100514676C CN B2007101380239 A CNB2007101380239 A CN B2007101380239A CN 200710138023 A CN200710138023 A CN 200710138023A CN 100514676 C CN100514676 C CN 100514676C
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mos device
semiconductor layer
channel mos
strain
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CN101118928A (zh
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陈豪育
杨富量
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Taiwan Semiconductor Manufacturing Co TSMC Ltd
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Abstract

一种选择性应变MOS元件，其中该MOS元件可为由一组NMOS元件以及PMOS元件所组成的选择性应变PMOS元件，且其不影响NMOS元件上的应变。其形成方法包括提供半导体基材，其中半导体基材包括底半导体层、配置于该底半导体层上的绝缘层以及配置于该绝缘层上的顶半导体层；图案化该顶半导体层以及绝缘层用以形成MOS作用区；形成MOS元件于MOS作用区上，且MOS元件包括栅极结构以及沟道层；以及进行氧化工艺，将一部分的顶半导体层氧化用以在沟道层上产生应变。本发明不仅克服了现有技术的缺点以及不足，并提升了元件性能且改善其工艺。

Description

应变沟道MOS元件
技术领域
本发明涉及一种微电子集成电路半导体元件及其工艺，特别是涉及一种在具有较佳电荷载子迁移率的绝缘半导体基材上形成的应变沟道电晶体，其利用一不含磊晶步骤的工艺所形成。
背景技术
半导体电晶体结构快速的发展，利用掺质控制CMOS元件沟道中电荷载子导通的技术遭遇到了瓶颈。随着CMOS元件工艺缩小至纳米级工艺，具有完全空乏区以及局部空乏区的硅绝缘层的技术能使MOSFETS能在低消耗功率的情况下作用。然而，硅绝缘层会产生自导性加热问题因而降低电晶体沟道层中的电荷迁移率。
机械应力在电荷载子迁移率上扮演了重要的角色，而电荷载子迁移率会影响许多重要的参数，如临界电压(VT)的切换、驱动电流的饱和(I DSat)以及开关切换的电流(On/Off current)。造成MOSFET元件沟道层应变的感应机械应力以及电荷载子迁移率都被认为是被复杂的实体工艺中所产生的声光散射现象影响。一般来说，电荷载子迁移率的高低与驱动电流的大小是成正比。
举例来说，现有技术提供了运用晶格常数差异的磊晶法用以引起造成沟道层上的应力而形成应变沟道。然而，所引起的应变程度会在后续的热处理工艺，如自导性加热效应中减轻，元件的效能也因此降低。现有的磊晶沉积工艺不仅复杂且耗成本，更需要多道的步骤才可完成。此外，利用两个材质间晶格常数的差异在沟道层上产生应力的方法会造成接面漏电(junction leakage)的问题，因而降低了元件的可靠度以及性能。
当拉伸应变沟道层改善了NMOS元件中的电子迁移率时，PMOS中的空穴迁移率可能会依据不同应变强度的拉伸应变或压缩应变而改善或降低。因此，在一晶圆上导入各种适当程度的应变至PMOS以及NMOS元件的沟道层仍是一个待克服的挑战。
所以，如何在半导体IC工艺技术上发展出改良的应变沟道SOI元件及其形成方法用以提升元件性能，并改善其工艺，即成为追求的目标。
发明内容
本发明的主要目的是在提供一改良的应变沟道SOI元件及其形成方法，特别是一改良的应变沟道MOS元件及其形成方法，不仅克服了现有技术的缺点以及不足，并提升了元件性能且改善其工艺。
根据本发明的上述目的，提出一种选择性应变MOS元件，如构成一组NMOS以及PMOS元件的选择性应变PMOS元件，且不影响NMOS元件中的应变。
本发明的目的及解决其技术问题还采用以下技术方案来实现。依据本发明提出的一种应变沟道MOS元件，其包括：一MOS作用区，该MOS作用区包括：一底半导体层；一绝缘层，配置于该底半导体层之上；及一顶半导体层，配置于该绝缘层之上；一MOS元件，位于该MOS作用区上，且包括一栅极结构以及一沟道层；以及一部份氧化的顶半导体层，选择性地于沟道层中形成一应变，且该绝缘层与该部份氧化的顶半导体层结合成一扩大绝缘区，其中该扩大绝缘区的两侧邻接于该MOS元件的的源极/漏极区，且该扩大绝缘区于邻接该源极/漏极区形成鸟嘴形状，且该扩大绝缘区于该顶半导体层的底部形成一凹面朝上的曲面。
本发明的目的及解决其技术问题还可采用以下技术措施进一步实现。
前述的应变沟道MOS元件，其更包括填充有一导体材质的凹陷区，其中该凹陷区位于邻接于MOS元件的相反两侧用以形成源极/漏极区。
前述的应变沟道MOS元件，其更包括具有一导体材质且提高的源极/漏极区。
前述的应变沟道MOS元件，其中所述的MOS作用区借由邻接的电绝缘结构电绝缘，且该电绝缘结构为浅沟槽绝缘层(STI)结构。
前述的应变沟道MOS元件，其中所述的MOS作用区在邻接表面上提高。
前述的应变沟道MOS元件，其中所述的绝缘层包括一氧化埋层。
前述的应变沟道MOS元件，其中所述的绝缘层的厚度约小于20nm。
前述的应变沟道MOS元件，其中所述的MOS元件包括一PMOS元件，且与邻接的该NMOS元件电绝缘，其中一NMOS元件形成于一NMOS作用区上。
前述的应变沟道MOS元件，其中所述的应变为一压应变，该压应变选择性地产生于PMOS元件沟道层上，且该压应变不影响该NMOS元件区的应变。
前述的应变沟道MOS元件，其中所述的NMOS元件形成于底半导体层上。
本发明与现有技术相比具有明显的优点和有益效果。由以上可知，为了达到上述目的，在第一实施例中，其方法包括提供一半导体基材，其中该半导体基材包括了底半导体层、配置于该底半导体层上的绝缘层以及配置于该绝缘层上的顶半导体层；图案化该顶半导体层以及绝缘层用以形成MOS作用区；形成MOS元件于MOS作用区上，且MOS元件包括栅极结构以及沟道层；以及进行氧化工艺，将一部份的顶半导体层氧化用以在沟道层上产生应变。
经由上述可知，本发明一选择性应变MOS元件，其中该MOS元件可为由一组NMOS元件以及PMOS元件所组成的选择性应变PMOS元件，且其不影响NMOS元件上的应变。其形成方法包括提供半导体基材，其中半导体基材包括底半导体层、配置于该底半导体层上的绝缘层以及配置于该绝缘层上的顶半导体层；图案化该顶半导体层以及绝缘层用以形成MOS作用区；形成MOS元件于MOS作用区上，且MOS元件包括栅极结构以及沟道层；以及进行氧化工艺，将一部份的顶半导体层氧化用以在沟道层上产生应变。
借由上述技术方案，本发明应变沟道MOS元件至少具有下列优点：本发明公开了一种出选择性地于PMOS元件上形成压应变沟道的方法，其中PMOS元件区中的压应力不影响NMOS元件区中的应力。借由个别针对PMOS元件与NMOS元件的沟道层产生应变，可得到较佳的应变等级控制以及电荷载子迁移率。此外，虽然依据晶格常数交错的磊晶来形成沟道层的方法在制作工艺中也常被运用，但形成应变沟道层的方法并不限定于此。本发明利用现有的工艺来形成一机械应变元件沟道层的方法，可降低产品成本、改善工艺流程以及提升晶圆的生产率。更可解决现有技术中接面漏电的缺点，借此改善元件的整体效能。
上述说明仅是本发明技术方案的概述，为了能够更清楚了解本发明的技术手段，而可依照说明书的内容予以实施，并且为了让本发明的上述和其他目的、特征和优点能够更明显易懂，以下特举较佳实施例，并配合附图，详细说明如下。
附图说明
图1A至图1F是本发明的实施例中，应变沟道SOI NMOS以及PMOS元件在各工艺步骤的侧面剖视图。
图2A至图2C是本发明的另一实施例中，应变沟道SOI NMOS以及PMOS元件在各工艺步骤的侧面剖视图。
图3是本发明各实施例的流程示意图。
12：半导体基材                 12A：底半导体层
12B：电绝缘层                  12C：顶半导体层
14A：PMOS元件区                14B：NMOS元件区
16A：浅沟槽绝缘层              16B：浅沟槽绝缘层
16C：浅沟槽绝缘层              18A：PMOS元件
18B：NMOS元件                  20A：凹陷区
20B：凹陷区                    20AA：源极区
20BB：漏极区                   22A：栅极介电层
22B：闸电极层                  24A：侧壁绝缘间隙壁
24B：侧壁绝缘间隙壁            30：保护覆盖层
32A：PMOS沟道层                32B：NMOS沟道层
301：步骤                      303：步骤
305：步骤                      307：步骤
309：步骤               311：步骤
具体实施方式
为更进一步阐述本发明为达成预定发明目的所采取的技术手段及功效，以下结合附图及较佳实施例，对依据本发明的具体实施方式、结构、特征及其功效，详细说明如后。
虽然本发明形成SOI结构的方式是选择性地形成压应变沟道PMOS元件，且不影响邻接NMOS元件的应变，但是也可利用分开的工艺以选择性方式于邻接NMOS元件的沟道层中形成一拉伸应变。
请参阅图1A中绝缘半导体层的基材部分的剖视图。半导体基材12(如硅)中，电绝缘层12B形成于半导体基材表面之下以界定出底半导体层12A以及顶半导体层12C。其中电绝缘层12B可为一氧化埋层(buried oxide，BOX)。氧化埋层12B可由现有的方法形成，如利用布植能量的大小决定氧化埋层12B的深度以及厚度。例如，布植高能量(200-1000keV)的氧离子到半导体基材12上且经由一高温退火步骤(约1200度至1350度)来形成氧化埋层。此外，该技术领域中其他现有的方法也可用来形成绝缘层12B。氧化埋层12B的厚度可以介于约100埃至5000埃之间，甚至小于200埃(20nm)。顶半导体层12C的厚度介于约50埃至2000埃之间。但氧化埋层12B以及顶半导体层12C的实际厚度应视实际元件(电晶体)尺寸以及元件操作的参数值来决定。
再次参阅图1A，半导体基材12借由离子布植来掺杂形成P掺杂区(P井)以及N掺杂区(N井)用以在两个掺杂区上个别形成一NMOS元件(电晶体)以及PMOS元件(电晶体)。
请参阅图1B，利用现有的图案化工艺(如微影图案化以及蚀刻)蚀刻出顶半导体层12C以及氧化埋层12B的厚度用以在半导体基材12A上形成一PMOS元件区14A以及一NOMS元件区14B。其中PMOS元件区14A是由半导体基材12A向外突出，而NOMS元件区14B是与半导体基材12A位于同一平面上。
在实施例中，氧化埋层12B的厚度小于20nm。选择较佳的氧化埋层厚度，可不需要后续在NMOS元件区14B上的选择性磊晶成长步骤即可达到阶梯高度去除的目的。此外，在后续的热氧化过程(容后详述)当中，具有较佳厚度的氧化埋层12B会因为大量膨胀(如膨胀量百分比)而产生一高压缩应力。
再次参阅图1B，电绝缘层如浅沟槽绝缘层(Shallow Trench Isolation，STI)结构16A、16B以及16C是利用现有的方法形成并分别邻接于NMOS元件区以及PMOS元件区。举例来说，硬光罩层是接续着半导体基材12A上STI沟槽的图案化以及蚀刻步骤形成于基材上。布植完毕且光罩移除后，STI沟槽中填满了绝缘材质，如二氧化硅。较佳是在半导体基材12的表面上突出一STI氧化层，如图中所示，突出的STI氧化层的上表面是与PMOS作用区14A中蚀刻后的氧化埋层12B的上表面处于同一平面。
请参阅图1C，具有栅极结构的PMOS元件(电晶体)18A以及NMOS元件(电晶体)18B利用现有的工艺与材质在PMOS元件区14A以及NMOS元件区14B上形成。这些MOS元件包括有栅极介电层(gate dielectricportion)22A、闸电极层(conductive gate electrode portion)22B以及侧壁绝缘间隙壁(sidewall insulator spacer)24A与24B。虽然图中所示的侧壁绝缘间隙壁具有一圆弧的倒角，但也可为现有的L型间隙壁或者多层间隙壁。在侧壁绝缘间隙壁24A与24B形成之前，在顶半导体层12C上形成一利用环状布植而成的轻掺杂区，且此轻掺杂区邻接于闸电极层22B。
请参阅图1D，保护覆盖层30形成于NMOS元件区14B上并覆于STI结构16B以及16C上使其在后续的干式蚀刻工艺中免于被蚀刻。保护覆盖层30可为有机或无机材质。在干式蚀刻步骤结束后，位于PMOS元件18A下方的半导体基材12被蚀刻出一深度而形成凹陷区20A以及20B。凹陷区20A以及20B是位于PMOS元件18A两侧与相邻于PMOS元件18A的STI结构16A以及16B之间。
请参阅图1E，其绘示本发明一重要步骤的剖面示意图。当以约800度至900度的温度完成一干式(或湿式)氧化工艺之后，部分的顶半导体层12C即被氧化。此部分的氧化区包括了一优先氧化的外部氧化区(outerportion)以及扩散至氧化埋层12B的区块。因此，在顶半导体层12C(材质可为硅)上会产生一压应力。此压应力具有在加工表面上水平方向所产生的侧向应力线。在氧化工艺中，半导体硅层12C部分的氧化区与氧化埋层12B结合以扩大绝缘区，而此绝缘区因包括了氧化埋层12B而形成一鸟嘴状的结构。参阅图示当中邻接的氧化埋层12B以及顶半导体层12C，顶半导体层12C朝邻接的氧化埋层12B方向形成一突出的区域，也就是说，包括了氧化埋层12B的氧化硅层12C于底部具有一凹面朝上的曲面。
请参阅图1F，利用现有的磊晶工艺来沉积(成长)如硅的半导体材质或如硅锗的应变半导体合金用以填充凹陷区20A以及20B而形成源极区20AA以及漏极区20BB。晶格常数大于半导体基材(如硅基材12A)的应变硅合金可被使用填充于凹陷区20A以及20B中，借此增加PMOS沟道层32A上的压应力。凹陷区充填完毕之后，如硼这类的P掺质可于磊晶工艺或离子布植工艺中在原处被加入用以降低源极以及漏极的电阻值。
在利用半导体材质或者半导体合金填充于凹陷区20A以及20B用以形成源极区20AA以及漏极区20BB之后，保护覆盖层30被移除。PMOS元件18A具有一压应变沟道层32A，而NMOS元件18B并未在其沟道层32B形成感应机械应力。此外，也可利用分开的工艺在NMOS沟道层32B中产生一拉伸应力。
’后续形成硅化物以降低源极/漏极表面上的接触电阻的工艺中，表面区的材质为硅，而闸电极顶部的材质为多晶硅。
请参阅图2A，其绘示本发明的另一实施例。在图2A中所示的结构成型前，步骤与元件的编号皆与前述的第1实施例相同，在此不再多加赘述。
请参阅图2B，图中所示的结构并未如第一实施例在图1D中形成凹陷区，而是进行氧化工艺使顶半导体层12C(材质可为硅)从外部区块开始被氧化而形成一压应力较小的半导体基材12C。因此，会在与PMOS元件18A两侧邻接的源极区以及漏极区上形成一鸟嘴形状。
在氧化工艺之后会形成一瘦长型的半导体层12C，且此半导体区12C具有水平方向的侧向应力，借此侧向应力于PMOS元件18A中沟道层32A上产生一压应力。
请参阅图2C，源极区34A以及漏极区34B分别形成于PMOS元件18A以及NMOS元件18B上的两相反侧边。源极区34A以及漏极区34B可利用沉积半导体材质或半导体合金的方法，在与侧壁绝缘间隙壁24A以及24B相邻接处形成具有预定高度(如25埃至500埃)的源极区34A以及漏极区34B。
源极区34A以及漏极区34B可借由选择性磊晶成长(SelectiveEpitaxial Growth，SEG)技术并利用硅或硅合金(如硅锗合金)用以增加或维持PMOS元件沟道层32A上的压应力。源极34A以及漏极区34B可在原处用P掺质(如硼)进行掺杂而形成，或者是在源极34A以及漏极区34B成型后进行一离子布植工艺。此外，PMOS元件18A与NMOS元件18B上的源极/漏极区可分开形成。源极/漏极区可由半导体硅或由晶格常数小于硅的拉伸应变半导体合金(如掺杂有碳的硅化物)所制成。此拉伸应变半导体合金可由加入或由原处生成一N型的掺质而形成。现有的金属硅化物成型工艺可用来在源极/漏极区表面上形成一金属硅化物，以便进行后续接点的形成。
因此，本发明提一种出选择性地于PMOS元件上形成压应变沟道的方法，其中PMOS元件区中的压应力不影响NMOS元件区中的应力。借由个别针对PMOS元件与NMOS元件的沟道层产生应变，可得到较佳的应变等级控制以及电荷载子迁移率。此外，虽然依据晶格常数交错的磊晶来形成沟道层的方法在制作工艺中也常被运用，但形成应变沟道层的方法并不限定于此。本发明利用现有的工艺来形成一机械应变元件沟道层的方法，可降低产品成本、改善工艺流程以及提升晶圆的生产率。更可解决现有技术中接面漏电的缺点，借此改善元件的整体效能。
请参阅图3，其绘示本发明中各种实施例的流程图。在步骤301中，提供一具有绝缘埋层(如氧化埋层)的半导体基材。在步骤303中，形成电绝缘的NMOS与PMOS作用区，其中PMOS作用区的高度被提升，且包括了延伸于加工表面上的底部氧化埋层区。在步骤305中，NMOS与PMOS的栅极结构形成于个别的作用区上。在步骤307中，凹陷区形成于邻接PMOS栅极结构任一边的源极/漏极区。在步骤309中，利用氧化工艺将配置于PMOS栅极结构下方的顶半导体层氧化，因而形成一压应变沟道层。在步骤311中，形成一具有较高高度的源极/漏极区，且为导体材质所制成。
以上所述，仅是本发明的较佳实施例而已，并非对本发明作任何形式上的限制，虽然本发明已以较佳实施例揭露如上，然而并非用以限定本发明，任何熟悉本专业的技术人员，在不脱离本发明技术方案范围内，当可利用上述揭示的技术内容作出些许更动或修饰为等同变化的等效实施例，但凡是未脱离本发明技术方案的内容，依据本发明的技术实质对以上实施例所作的任何简单修改、等同变化与修饰，均仍属于本发明技术方案的范围内。

Claims (10)

1.一种应变沟道MOS元件，其特征在于包括：
一MOS作用区，包括：
一底半导体层；
一绝缘层，配置于该底半导体层之上；及
一顶半导体层，配置于该绝缘层之上；
一MOS元件，位于该MOS作用区上，且包括一栅极结构以及一沟道层；以及
一部分氧化的顶半导体层，选择性地于沟道层中形成一应变，且该绝缘层与该部分氧化的顶半导体层结合成一扩大绝缘区，其中该扩大绝缘区的两侧邻接于该MOS元件的源极/漏极区，且该扩大绝缘区于邻接该源极/漏极区形成鸟嘴形状，且该扩大绝缘区于该顶半导体层的底部形成一凹面朝上的曲面。
2.根据权利要求1所述的应变沟道MOS元件，其特征在于更包括填充有一导体材质的凹陷区，其中该凹陷区位于邻接于MOS元件的相反两侧用以形成源极/漏极区。
3.根据权利要求1所述的应变沟道MOS元件，其特征在于更包括具有一导体材质且提高的源极/漏极区。
4.根据权利要求1所述的应变沟道MOS元件，其特征在于其中所述的MOS作用区借由邻接的电绝缘结构电绝缘，且该电绝缘结构为浅沟槽绝缘层结构。
5.根据权利要求1所述的应变沟道MOS元件，其特征在于其中所述的MOS作用区在邻接表面上提高。
6.根据权利要求1所述的应变沟道MOS元件，其特征在于其中所述的绝缘层包括一氧化埋层。
7.根据权利要求1所述的应变沟道MOS元件，其特征在于其中所述的绝缘层的厚度小于20nm。
8.根据权利要求1所述的应变沟道MOS元件，其特征在于其中所述的MOS元件包括一PMOS元件，且与邻接的该NMOS元件电绝缘，其中一NMOS元件形成于一NMOS作用区上。
9.根据权利要求8所述的应变沟道MOS元件，其特征在于其中所述的应变为一压应变，该压应变选择性地产生于PMOS元件沟道层上，且该压应变不影响该NMOS元件区的应变。
10.根据权利要求8所述的应变沟道MOS元件，其特征在于其中所述的NMOS元件形成于底半导体层上。
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