CN100490111C - 用于获得具有支撑衬底和超薄层的结构的方法 - Google Patents
用于获得具有支撑衬底和超薄层的结构的方法 Download PDFInfo
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- CN100490111C CN100490111C CNB2004800156014A CN200480015601A CN100490111C CN 100490111 C CN100490111 C CN 100490111C CN B2004800156014 A CNB2004800156014 A CN B2004800156014A CN 200480015601 A CN200480015601 A CN 200480015601A CN 100490111 C CN100490111 C CN 100490111C
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- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 claims description 4
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- GPXJNWSHGFTCBW-UHFFFAOYSA-N Indium phosphide Chemical compound [In]#P GPXJNWSHGFTCBW-UHFFFAOYSA-N 0.000 description 1
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Images
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/76—Making of isolation regions between components
- H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
- H01L21/7624—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology
- H01L21/76251—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology using bonding techniques
- H01L21/76254—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology using bonding techniques with separation/delamination along an ion implanted layer, e.g. Smart-cut, Unibond
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/76—Making of isolation regions between components
- H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
- H01L21/7624—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology
- H01L21/76251—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology using bonding techniques
- H01L21/76259—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology using bonding techniques with separation/delamination along a porous layer
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- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Manufacturing & Machinery (AREA)
- Recrystallisation Techniques (AREA)
- Element Separation (AREA)
Abstract
Description
Claims (17)
Applications Claiming Priority (3)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
FR03/06843 | 2003-06-06 | ||
FR0306843A FR2855908B1 (fr) | 2003-06-06 | 2003-06-06 | Procede d'obtention d'une structure comprenant au moins un substrat et une couche ultramince |
PCT/FR2004/001369 WO2005004233A1 (fr) | 2003-06-06 | 2004-06-03 | Procede d'obtention d'une structure comprenant un substrat support et une couche ultramince |
Publications (2)
Publication Number | Publication Date |
---|---|
CN1802737A CN1802737A (zh) | 2006-07-12 |
CN100490111C true CN100490111C (zh) | 2009-05-20 |
Family
ID=33443189
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
CNB2004800156014A Expired - Lifetime CN100490111C (zh) | 2003-06-06 | 2004-06-03 | 用于获得具有支撑衬底和超薄层的结构的方法 |
Country Status (7)
Country | Link |
---|---|
US (1) | US6991995B2 (zh) |
EP (1) | EP1631984B1 (zh) |
JP (1) | JP2006527479A (zh) |
KR (1) | KR100751125B1 (zh) |
CN (1) | CN100490111C (zh) |
FR (1) | FR2855908B1 (zh) |
WO (1) | WO2005004233A1 (zh) |
Families Citing this family (59)
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JP4407127B2 (ja) * | 2003-01-10 | 2010-02-03 | 信越半導体株式会社 | Soiウエーハの製造方法 |
CN1795409A (zh) * | 2003-04-23 | 2006-06-28 | 斗日电子通信株式会社 | 用于耦合波导的方法与系统 |
FR2857983B1 (fr) * | 2003-07-24 | 2005-09-02 | Soitec Silicon On Insulator | Procede de fabrication d'une couche epitaxiee |
US7538010B2 (en) * | 2003-07-24 | 2009-05-26 | S.O.I.Tec Silicon On Insulator Technologies | Method of fabricating an epitaxially grown layer |
TW593126B (en) * | 2003-09-30 | 2004-06-21 | Prime View Int Co Ltd | A structure of a micro electro mechanical system and manufacturing the same |
CN101036222A (zh) | 2004-09-21 | 2007-09-12 | S.O.I.Tec绝缘体上硅技术公司 | 通过实施共注入获得薄层的方法和随后的注入 |
EP1831922B9 (en) * | 2004-12-28 | 2010-02-24 | S.O.I.Tec Silicon on Insulator Technologies | Method for obtaining a thin layer having a low density of holes |
JP2009503564A (ja) * | 2005-07-22 | 2009-01-29 | クアルコム,インコーポレイテッド | Memsデバイスのための支持構造、およびその方法 |
KR101423321B1 (ko) * | 2005-07-22 | 2014-07-30 | 퀄컴 엠이엠에스 테크놀로지스, 인크. | 지지 구조물들을 가지는 전자기계 장치들 및 그 제조방법들 |
EP2495212A3 (en) * | 2005-07-22 | 2012-10-31 | QUALCOMM MEMS Technologies, Inc. | Mems devices having support structures and methods of fabricating the same |
EP1907316A1 (en) | 2005-07-22 | 2008-04-09 | Qualcomm Mems Technologies, Inc. | Support structure for mems device and methods therefor |
CN100487885C (zh) * | 2005-07-29 | 2009-05-13 | 上海新傲科技有限公司 | 一种绝缘体上硅的制作方法 |
WO2007044545A2 (en) * | 2005-10-07 | 2007-04-19 | Lee, Michael, J. | Monolitically integrated optical devices with amorphous silicon arrayed waveguide gratings and ingaasp gain |
US7657143B2 (en) * | 2005-10-07 | 2010-02-02 | Novatronix Corporation | Method for improving refractive index control in PECVD deposited a-SiNy films |
US20070155071A1 (en) * | 2005-10-07 | 2007-07-05 | Chan Winston K | Method of reducing edge height at the overlap of a layer deposited on a stepped substrate |
US7773840B2 (en) | 2005-10-07 | 2010-08-10 | Novatronix Corporation | Interface for a-Si waveguides and III/V waveguides |
FR2895563B1 (fr) * | 2005-12-22 | 2008-04-04 | Soitec Silicon On Insulator | Procede de simplification d'une sequence de finition et structure obtenue par le procede |
WO2007071787A1 (en) * | 2005-12-22 | 2007-06-28 | S.O.I.Tec Silicon On Insulator Technologies | Process for simplification of a finishing sequence and structure obtained by the process |
EP1981063B1 (en) * | 2005-12-27 | 2021-04-07 | Shin-Etsu Chemical Co., Ltd. | Process for producing a soi wafer |
JP5135713B2 (ja) * | 2006-05-25 | 2013-02-06 | 株式会社Sumco | 半導体基板の製造方法 |
FR2903809B1 (fr) * | 2006-07-13 | 2008-10-17 | Soitec Silicon On Insulator | Traitement thermique de stabilisation d'interface e collage. |
US20080032501A1 (en) * | 2006-07-21 | 2008-02-07 | Honeywell International Inc. | Silicon on metal for mems devices |
US7545552B2 (en) * | 2006-10-19 | 2009-06-09 | Qualcomm Mems Technologies, Inc. | Sacrificial spacer process and resultant structure for MEMS support structure |
CN101652317B (zh) * | 2007-04-04 | 2012-12-12 | 高通Mems科技公司 | 通过牺牲层中的界面修改来消除释放蚀刻侵蚀 |
US7719752B2 (en) * | 2007-05-11 | 2010-05-18 | Qualcomm Mems Technologies, Inc. | MEMS structures, methods of fabricating MEMS components on separate substrates and assembly of same |
US7825007B2 (en) * | 2007-05-11 | 2010-11-02 | Semiconductor Energy Laboratory Co., Ltd. | Method of joining a plurality of SOI substrates on a glass substrate by a heat treatment |
JP5415676B2 (ja) * | 2007-05-30 | 2014-02-12 | 信越化学工業株式会社 | Soiウェーハの製造方法 |
WO2009001836A1 (en) * | 2007-06-28 | 2008-12-31 | Semiconductor Energy Laboratory Co., Ltd. | Manufacturing method of semiconductor device |
US8431451B2 (en) | 2007-06-29 | 2013-04-30 | Semicondutor Energy Laboratory Co., Ltd. | Display device and method for manufacturing the same |
US8068268B2 (en) * | 2007-07-03 | 2011-11-29 | Qualcomm Mems Technologies, Inc. | MEMS devices having improved uniformity and methods for making them |
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US20090115018A1 (en) * | 2007-11-01 | 2009-05-07 | Alpha & Omega Semiconductor, Ltd | Transient voltage suppressor manufactured in silicon on oxide (SOI) layer |
FR2926748B1 (fr) | 2008-01-25 | 2010-04-02 | Commissariat Energie Atomique | Objet muni d'un element graphique reporte sur un support et procede de realisation d'un tel objet. |
US20090242031A1 (en) * | 2008-03-27 | 2009-10-01 | Twin Creeks Technologies, Inc. | Photovoltaic Assembly Including a Conductive Layer Between a Semiconductor Lamina and a Receiver Element |
US20090242010A1 (en) * | 2008-03-27 | 2009-10-01 | Twin Creeks Technologies, Inc. | Method to Form a Photovoltaic Cell Comprising a Thin Lamina Bonded to a Discrete Receiver Element |
US20100038686A1 (en) * | 2008-08-14 | 2010-02-18 | Advanced Micro Devices, Inc. | Soi substrates and devices on soi substrates having a silicon nitride diffusion inhibition layer and methods for fabricating |
WO2010036602A1 (en) * | 2008-09-26 | 2010-04-01 | S.O.I.Tec Silicon On Insulator Technologies | Method of forming a composite laser substrate |
FR2938119B1 (fr) * | 2008-10-30 | 2011-04-22 | Soitec Silicon On Insulator | Procede de detachement de couches semi-conductrices a basse temperature |
JP5521339B2 (ja) * | 2009-02-05 | 2014-06-11 | 信越半導体株式会社 | 多層膜付き半導体ウェーハの製造方法及び半導体デバイスの製造方法 |
US8782818B2 (en) * | 2009-05-14 | 2014-07-22 | Chang-Hsien Ho | Safety helmet structure and processing method thereof |
JP5455445B2 (ja) * | 2009-05-29 | 2014-03-26 | 信越化学工業株式会社 | 貼り合わせウェーハの製造方法 |
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FR2946435B1 (fr) | 2009-06-04 | 2017-09-29 | Commissariat A L'energie Atomique | Procede de fabrication d'images colorees avec une resolution micronique enfouies dans un support tres robuste et tres perenne |
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FR2954585B1 (fr) * | 2009-12-23 | 2012-03-02 | Soitec Silicon Insulator Technologies | Procede de realisation d'une heterostructure avec minimisation de contrainte |
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FR2961948B1 (fr) * | 2010-06-23 | 2012-08-03 | Soitec Silicon On Insulator | Procede de traitement d'une piece en materiau compose |
GB201010705D0 (en) * | 2010-06-25 | 2010-08-11 | Element Six Ltd | Substrates for semiconductor devices |
US8659816B2 (en) | 2011-04-25 | 2014-02-25 | Qualcomm Mems Technologies, Inc. | Mechanical layer and methods of making the same |
US9520293B2 (en) | 2011-07-11 | 2016-12-13 | King Abdullah University Of Science And Technology | Method for producing mechanically flexible silicon substrate |
CN102969267B (zh) * | 2011-08-31 | 2015-12-16 | 上海华力微电子有限公司 | 绝缘体上硅硅片及浮体动态随机存储器单元的制造方法 |
JP2013076753A (ja) * | 2011-09-29 | 2013-04-25 | Sumitomo Osaka Cement Co Ltd | 光導波路素子及びその製造方法 |
CN102543834A (zh) * | 2012-02-14 | 2012-07-04 | 上海先进半导体制造股份有限公司 | 绝缘层上的半导体结构及其制造方法 |
WO2013124719A1 (en) * | 2012-02-22 | 2013-08-29 | Soitec | Methods of providing thin layers of crystalline semiconductor material, and related structures and devices |
CN102851734B (zh) * | 2012-09-06 | 2015-11-25 | 苏州晶湛半导体有限公司 | 半导体外延结构及其生长方法 |
US10985204B2 (en) * | 2016-02-16 | 2021-04-20 | G-Ray Switzerland Sa | Structures, systems and methods for electrical charge transport across bonded interfaces |
FR3076292B1 (fr) * | 2017-12-28 | 2020-01-03 | Commissariat A L'energie Atomique Et Aux Energies Alternatives | Procede de transfert d'une couche utile sur un substrat support |
FR3077923B1 (fr) * | 2018-02-12 | 2021-07-16 | Soitec Silicon On Insulator | Procede de fabrication d'une structure de type semi-conducteur sur isolant par transfert de couche |
JP7253730B2 (ja) * | 2018-12-26 | 2023-04-07 | 株式会社日進製作所 | 半導体装置の製造方法及び半導体装置 |
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FR2755537B1 (fr) * | 1996-11-05 | 1999-03-05 | Commissariat Energie Atomique | Procede de fabrication d'un film mince sur un support et structure ainsi obtenue |
SG67458A1 (en) | 1996-12-18 | 1999-09-21 | Canon Kk | Process for producing semiconductor article |
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US6328796B1 (en) * | 1999-02-01 | 2001-12-11 | The United States Of America As Represented By The Secretary Of The Navy | Single-crystal material on non-single-crystalline substrate |
JP2000223682A (ja) * | 1999-02-02 | 2000-08-11 | Canon Inc | 基体の処理方法及び半導体基板の製造方法 |
US20040175901A1 (en) | 1999-02-10 | 2004-09-09 | Commissariat A L'energie Atomique | Method for forming an optical silicon layer on a support and use of said method in the production of optical components |
FR2789517B1 (fr) * | 1999-02-10 | 2001-03-09 | Commissariat Energie Atomique | Procede de formation sur un support d'une couche de silicium a usage optique et mise en oeuvre du procede pour la realisation de composants optiques |
JP3900741B2 (ja) * | 1999-05-21 | 2007-04-04 | 信越半導体株式会社 | Soiウェーハの製造方法 |
US6500732B1 (en) * | 1999-08-10 | 2002-12-31 | Silicon Genesis Corporation | Cleaving process to fabricate multilayered substrates using low implantation doses |
JP2001196566A (ja) * | 2000-01-07 | 2001-07-19 | Sony Corp | 半導体基板およびその製造方法 |
FR2817394B1 (fr) * | 2000-11-27 | 2003-10-31 | Soitec Silicon On Insulator | Procede de fabrication d'un substrat notamment pour l'optique, l'electronique ou l'optoelectronique et substrat obtenu par ce procede |
JP4304879B2 (ja) * | 2001-04-06 | 2009-07-29 | 信越半導体株式会社 | 水素イオンまたは希ガスイオンの注入量の決定方法 |
JP4628580B2 (ja) * | 2001-04-18 | 2011-02-09 | 信越半導体株式会社 | 貼り合せ基板の製造方法 |
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2003
- 2003-06-06 FR FR0306843A patent/FR2855908B1/fr not_active Expired - Lifetime
-
2004
- 2004-02-20 US US10/784,032 patent/US6991995B2/en not_active Expired - Lifetime
- 2004-06-03 KR KR1020057023454A patent/KR100751125B1/ko active IP Right Grant
- 2004-06-03 EP EP04767238.1A patent/EP1631984B1/fr not_active Expired - Lifetime
- 2004-06-03 CN CNB2004800156014A patent/CN100490111C/zh not_active Expired - Lifetime
- 2004-06-03 JP JP2006508352A patent/JP2006527479A/ja active Pending
- 2004-06-03 WO PCT/FR2004/001369 patent/WO2005004233A1/fr active Application Filing
Also Published As
Publication number | Publication date |
---|---|
FR2855908B1 (fr) | 2005-08-26 |
KR100751125B1 (ko) | 2007-08-22 |
CN1802737A (zh) | 2006-07-12 |
EP1631984A1 (fr) | 2006-03-08 |
US6991995B2 (en) | 2006-01-31 |
EP1631984B1 (fr) | 2017-08-23 |
US20040248380A1 (en) | 2004-12-09 |
JP2006527479A (ja) | 2006-11-30 |
WO2005004233A1 (fr) | 2005-01-13 |
KR20060015642A (ko) | 2006-02-17 |
FR2855908A1 (fr) | 2004-12-10 |
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