CN100483698C - 多孔低k介质互连结构 - Google Patents
多孔低k介质互连结构 Download PDFInfo
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- CN100483698C CN100483698C CNB028204360A CN02820436A CN100483698C CN 100483698 C CN100483698 C CN 100483698C CN B028204360 A CNB028204360 A CN B028204360A CN 02820436 A CN02820436 A CN 02820436A CN 100483698 C CN100483698 C CN 100483698C
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Abstract
Description
工艺 | 条件 |
旋涂 | 粘合促进剂 |
热板烘焙 | 185℃/90秒钟 |
旋涂 | 第一ILD层(多孔SiLK) |
热板烘焙 | 150℃/2分钟400℃/5分钟或150℃/2分钟400℃/2分钟430℃/2分钟 |
旋涂 | 埋置腐蚀停止层(HOSP) |
热板烘焙 | 150℃/2分钟400℃/2分钟 |
旋涂 | 第二ILD层(多孔SiLK) |
热板烘焙 | 150℃/2分钟 |
固化 | 炉子-430℃/80分钟 |
Claims (68)
Applications Claiming Priority (4)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US33973401P | 2001-12-13 | 2001-12-13 | |
US60/339,734 | 2001-12-13 | ||
US10/290,682 | 2002-11-08 | ||
US10/290,616 | 2002-11-08 |
Publications (2)
Publication Number | Publication Date |
---|---|
CN1788347A CN1788347A (zh) | 2006-06-14 |
CN100483698C true CN100483698C (zh) | 2009-04-29 |
Family
ID=36785140
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
CNB028204360A Expired - Lifetime CN100483698C (zh) | 2001-12-13 | 2002-12-13 | 多孔低k介质互连结构 |
Country Status (4)
Country | Link |
---|---|
US (4) | US6783862B2 (zh) |
KR (1) | KR100581815B1 (zh) |
CN (1) | CN100483698C (zh) |
TW (1) | TW580755B (zh) |
Families Citing this family (44)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP3715626B2 (ja) * | 2003-01-17 | 2005-11-09 | 株式会社東芝 | 半導体装置の製造方法および半導体装置 |
US6737365B1 (en) * | 2003-03-24 | 2004-05-18 | Intel Corporation | Forming a porous dielectric layer |
US7208389B1 (en) | 2003-03-31 | 2007-04-24 | Novellus Systems, Inc. | Method of porogen removal from porous low-k films using UV radiation |
US7241704B1 (en) * | 2003-03-31 | 2007-07-10 | Novellus Systems, Inc. | Methods for producing low stress porous low-k dielectric materials using precursors with organic functional groups |
US7390537B1 (en) | 2003-11-20 | 2008-06-24 | Novellus Systems, Inc. | Methods for producing low-k CDO films with low residual stress |
US7342315B2 (en) * | 2003-12-18 | 2008-03-11 | Texas Instruments Incorporated | Method to increase mechanical fracture robustness of porous low k dielectric materials |
JP4194508B2 (ja) * | 2004-02-26 | 2008-12-10 | 三洋電機株式会社 | 半導体装置の製造方法 |
US7381662B1 (en) | 2004-03-11 | 2008-06-03 | Novellus Systems, Inc. | Methods for improving the cracking resistance of low-k dielectric materials |
US7341761B1 (en) | 2004-03-11 | 2008-03-11 | Novellus Systems, Inc. | Methods for producing low-k CDO films |
US7557035B1 (en) | 2004-04-06 | 2009-07-07 | Advanced Micro Devices, Inc. | Method of forming semiconductor devices by microwave curing of low-k dielectric films |
US7781351B1 (en) | 2004-04-07 | 2010-08-24 | Novellus Systems, Inc. | Methods for producing low-k carbon doped oxide films with low residual stress |
US7344972B2 (en) * | 2004-04-21 | 2008-03-18 | Intel Corporation | Photosensitive dielectric layer |
US7115974B2 (en) * | 2004-04-27 | 2006-10-03 | Taiwan Semiconductor Manfacturing Company, Ltd. | Silicon oxycarbide and silicon carbonitride based materials for MOS devices |
US7622400B1 (en) | 2004-05-18 | 2009-11-24 | Novellus Systems, Inc. | Method for improving mechanical properties of low dielectric constant materials |
US7078814B2 (en) * | 2004-05-25 | 2006-07-18 | International Business Machines Corporation | Method of forming a semiconductor device having air gaps and the structure so formed |
US7326444B1 (en) | 2004-09-14 | 2008-02-05 | Novellus Systems, Inc. | Methods for improving integration performance of low stress CDO films |
US7695765B1 (en) | 2004-11-12 | 2010-04-13 | Novellus Systems, Inc. | Methods for producing low-stress carbon-doped oxide films with improved integration properties |
US7166531B1 (en) | 2005-01-31 | 2007-01-23 | Novellus Systems, Inc. | VLSI fabrication processes for introducing pores into dielectric materials |
US8728289B2 (en) * | 2005-12-15 | 2014-05-20 | Medtronic, Inc. | Monolithic electrodes and pH transducers |
JP4788415B2 (ja) * | 2006-03-15 | 2011-10-05 | ソニー株式会社 | 半導体装置の製造方法 |
US20070232046A1 (en) * | 2006-03-31 | 2007-10-04 | Koji Miyata | Damascene interconnection having porous low K layer with improved mechanical properties |
US8399349B2 (en) * | 2006-04-18 | 2013-03-19 | Air Products And Chemicals, Inc. | Materials and methods of forming controlled void |
US7906174B1 (en) | 2006-12-07 | 2011-03-15 | Novellus Systems, Inc. | PECVD methods for producing ultra low-k dielectric films using UV treatment |
US7947565B2 (en) | 2007-02-07 | 2011-05-24 | United Microelectronics Corp. | Forming method of porous low-k layer and interconnect process |
US7615482B2 (en) * | 2007-03-23 | 2009-11-10 | International Business Machines Corporation | Structure and method for porous SiCOH dielectric layers and adhesion promoting or etch stop layers having increased interfacial and mechanical strength |
JP4977508B2 (ja) * | 2007-03-26 | 2012-07-18 | アイメック | ダメージの入った多孔性誘電体の処理方法 |
US9329822B2 (en) * | 2007-04-04 | 2016-05-03 | Xerox Corporation | Methods and apparatus for improved operation of networked printing system |
US8129257B2 (en) * | 2008-01-14 | 2012-03-06 | The Regents Of The University Of California | Vertical outgassing channels |
US20100015816A1 (en) * | 2008-07-15 | 2010-01-21 | Kelvin Chan | Methods to promote adhesion between barrier layer and porous low-k film deposited from multiple liquid precursors |
US20100176513A1 (en) * | 2009-01-09 | 2010-07-15 | International Business Machines Corporation | Structure and method of forming metal interconnect structures in ultra low-k dielectrics |
US8889544B2 (en) * | 2011-02-16 | 2014-11-18 | Taiwan Semiconductor Manufacturing Company, Ltd. | Dielectric protection layer as a chemical-mechanical polishing stop layer |
US9054110B2 (en) | 2011-08-05 | 2015-06-09 | Taiwan Semiconductor Manufacturing Company, Ltd. | Low-K dielectric layer and porogen |
US9330989B2 (en) | 2012-09-28 | 2016-05-03 | Taiwan Semiconductor Manufacturing Company, Ltd. | System and method for chemical-mechanical planarization of a metal layer |
CN103871961B (zh) | 2012-12-17 | 2017-08-25 | 中芯国际集成电路制造(上海)有限公司 | 互连结构及其制造方法 |
US8765546B1 (en) | 2013-06-24 | 2014-07-01 | United Microelectronics Corp. | Method for fabricating fin-shaped field-effect transistor |
JP2015115446A (ja) * | 2013-12-11 | 2015-06-22 | 株式会社東芝 | 半導体装置の製造方法 |
CN105097658B (zh) * | 2014-05-15 | 2018-05-25 | 中芯国际集成电路制造(上海)有限公司 | 半导体器件、互连层和互连层的制作方法 |
KR20170070083A (ko) | 2014-10-15 | 2017-06-21 | 어플라이드 머티어리얼스, 인코포레이티드 | 플라즈마 손상 방지를 위한 다중-층 유전체 스택 |
US10008382B2 (en) * | 2015-07-30 | 2018-06-26 | Taiwan Semiconductor Manufacturing Company, Ltd. | Semiconductor device having a porous low-k structure |
US10083904B2 (en) * | 2016-01-12 | 2018-09-25 | Globalfoundries Inc. | Metholodogy for profile control and capacitance reduction |
US9997451B2 (en) | 2016-06-30 | 2018-06-12 | International Business Machines Corporation | Semiconductor device including a porous dielectric layer, and method of forming the semiconductor device |
US9824982B1 (en) | 2016-08-09 | 2017-11-21 | International Business Machines Corporation | Structure and fabrication method for enhanced mechanical strength crack stop |
US10529660B2 (en) | 2016-09-30 | 2020-01-07 | Intel Corporation | Pore-filled dielectric materials for semiconductor structure fabrication and their methods of fabrication |
US10679892B1 (en) | 2019-02-28 | 2020-06-09 | International Business Machines Corporation | Multi-buried ULK field in BEOL structure |
Citations (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US6069071A (en) * | 1996-12-26 | 2000-05-30 | Kabushiki Kaisha Toshiba | Method of manufacturing an interconnect by dissolving an intermetallic compound film into a main component of a metal film |
US6071809A (en) * | 1998-09-25 | 2000-06-06 | Rockwell Semiconductor Systems, Inc. | Methods for forming high-performing dual-damascene interconnect structures |
US6156648A (en) * | 1999-03-10 | 2000-12-05 | United Microelectronics Corp. | Method for fabricating dual damascene |
Family Cites Families (27)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
ATE217447T1 (de) * | 1990-08-03 | 2002-05-15 | Canon Kk | Verfahren zur herstellung eines halbleiterkörpers |
US5470802A (en) * | 1994-05-20 | 1995-11-28 | Texas Instruments Incorporated | Method of making a semiconductor device using a low dielectric constant material |
JPH10173179A (ja) | 1996-12-11 | 1998-06-26 | Toshiba Corp | 半導体装置及び半導体装置の製造方法 |
US6017804A (en) * | 1998-01-09 | 2000-01-25 | Lucent Technologies Inc. | Method and apparatus for cleaving semiconductor material |
US6218020B1 (en) * | 1999-01-07 | 2001-04-17 | Alliedsignal Inc. | Dielectric films from organohydridosiloxane resins with high organic content |
US6177199B1 (en) * | 1999-01-07 | 2001-01-23 | Alliedsignal Inc. | Dielectric films from organohydridosiloxane resins with low organic content |
TW465101B (en) * | 1998-09-04 | 2001-11-21 | Canon Kk | Semiconductor substrate and method for producing the same |
US6284149B1 (en) * | 1998-09-18 | 2001-09-04 | Applied Materials, Inc. | High-density plasma etching of carbon-based low-k materials in a integrated circuit |
US6171945B1 (en) | 1998-10-22 | 2001-01-09 | Applied Materials, Inc. | CVD nanoporous silica low dielectric constant films |
CN1325560C (zh) | 1998-11-24 | 2007-07-11 | 陶氏环球技术公司 | 含可交联基质前体和致孔剂的组合物及由此组合物制成的多孔性基质 |
EP1157059A1 (en) | 1999-01-08 | 2001-11-28 | The Dow Chemical Company | Low dielectric constant polymers having good adhesion and toughness and articles made with such polymers |
US6271127B1 (en) * | 1999-06-10 | 2001-08-07 | Conexant Systems, Inc. | Method for dual damascene process using electron beam and ion implantation cure methods for low dielectric constant materials |
US6362091B1 (en) * | 2000-03-14 | 2002-03-26 | Intel Corporation | Method for making a semiconductor device having a low-k dielectric layer |
US6482733B2 (en) * | 2000-05-15 | 2002-11-19 | Asm Microchemistry Oy | Protective layers prior to alternating layer deposition |
US6358842B1 (en) * | 2000-08-07 | 2002-03-19 | Chartered Semiconductor Manufacturing Ltd. | Method to form damascene interconnects with sidewall passivation to protect organic dielectrics |
US7115531B2 (en) * | 2000-08-21 | 2006-10-03 | Dow Global Technologies Inc. | Organosilicate resins as hardmasks for organic polymer dielectrics in fabrication of microelectronic devices |
US6472306B1 (en) * | 2000-09-05 | 2002-10-29 | Industrial Technology Research Institute | Method of forming a dual damascene opening using CVD Low-K material and spin-on-polymer |
US6451712B1 (en) * | 2000-12-18 | 2002-09-17 | International Business Machines Corporation | Method for forming a porous dielectric material layer in a semiconductor device and device formed |
US6383920B1 (en) * | 2001-01-10 | 2002-05-07 | International Business Machines Corporation | Process of enclosing via for improved reliability in dual damascene interconnects |
US6524947B1 (en) * | 2001-02-01 | 2003-02-25 | Advanced Micro Devices, Inc. | Slotted trench dual inlaid structure and method of forming thereof |
US6603204B2 (en) * | 2001-02-28 | 2003-08-05 | International Business Machines Corporation | Low-k interconnect structure comprised of a multilayer of spin-on porous dielectrics |
US6878615B2 (en) * | 2001-05-24 | 2005-04-12 | Taiwan Semiconductor Manufacturing Company, Ltd. | Method to solve via poisoning for porous low-k dielectric |
US6798043B2 (en) * | 2001-06-28 | 2004-09-28 | Agere Systems, Inc. | Structure and method for isolating porous low-k dielectric films |
US6879046B2 (en) * | 2001-06-28 | 2005-04-12 | Agere Systems Inc. | Split barrier layer including nitrogen-containing portion and oxygen-containing portion |
US6797605B2 (en) * | 2001-07-26 | 2004-09-28 | Chartered Semiconductor Manufacturing Ltd. | Method to improve adhesion of dielectric films in damascene interconnects |
US6815333B2 (en) * | 2002-04-02 | 2004-11-09 | Dow Global Technologies Inc. | Tri-layer masking architecture for patterning dual damascene interconnects |
US20040137153A1 (en) * | 2002-04-16 | 2004-07-15 | Michael Thomas | Layered stacks and methods of production thereof |
-
2002
- 2002-11-08 US US10/290,682 patent/US6783862B2/en not_active Ceased
- 2002-11-08 US US10/290,616 patent/US6933586B2/en not_active Expired - Fee Related
- 2002-12-13 CN CNB028204360A patent/CN100483698C/zh not_active Expired - Lifetime
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2003
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-
2014
- 2014-02-10 US US14/176,526 patent/USRE45781E1/en not_active Expired - Lifetime
Patent Citations (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US6069071A (en) * | 1996-12-26 | 2000-05-30 | Kabushiki Kaisha Toshiba | Method of manufacturing an interconnect by dissolving an intermetallic compound film into a main component of a metal film |
US6071809A (en) * | 1998-09-25 | 2000-06-06 | Rockwell Semiconductor Systems, Inc. | Methods for forming high-performing dual-damascene interconnect structures |
US6156648A (en) * | 1999-03-10 | 2000-12-05 | United Microelectronics Corp. | Method for fabricating dual damascene |
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US6844257B2 (en) | 2005-01-18 |
US20030114013A1 (en) | 2003-06-19 |
US20040018717A1 (en) | 2004-01-29 |
TW200305253A (en) | 2003-10-16 |
CN1788347A (zh) | 2006-06-14 |
KR100581815B1 (ko) | 2006-05-23 |
TW580755B (en) | 2004-03-21 |
US6933586B2 (en) | 2005-08-23 |
USRE45781E1 (en) | 2015-10-27 |
US6783862B2 (en) | 2004-08-31 |
US20030111263A1 (en) | 2003-06-19 |
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