CN100461463C - 半导体结构和形成金属氧化物半导体结构的方法 - Google Patents

半导体结构和形成金属氧化物半导体结构的方法 Download PDF

Info

Publication number
CN100461463C
CN100461463C CNB2005800228619A CN200580022861A CN100461463C CN 100461463 C CN100461463 C CN 100461463C CN B2005800228619 A CNB2005800228619 A CN B2005800228619A CN 200580022861 A CN200580022861 A CN 200580022861A CN 100461463 C CN100461463 C CN 100461463C
Authority
CN
China
Prior art keywords
drain region
silicide
fully silicided
annealing
source
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
CNB2005800228619A
Other languages
English (en)
Chinese (zh)
Other versions
CN1981386A (zh
Inventor
格伦·A·比利
米切尔·L·斯廷
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Core Usa Second LLC
GlobalFoundries Inc
Original Assignee
International Business Machines Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by International Business Machines Corp filed Critical International Business Machines Corp
Publication of CN1981386A publication Critical patent/CN1981386A/zh
Application granted granted Critical
Publication of CN100461463C publication Critical patent/CN100461463C/zh
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Images

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/01—Manufacture or treatment
    • H10D30/021—Manufacture or treatment of FETs having insulated gates [IGFET]
    • H10D30/0212—Manufacture or treatment of FETs having insulated gates [IGFET] using self-aligned silicidation
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/01—Manufacture or treatment
    • H10D30/021—Manufacture or treatment of FETs having insulated gates [IGFET]
    • H10D30/0212—Manufacture or treatment of FETs having insulated gates [IGFET] using self-aligned silicidation
    • H10D30/0213—Manufacture or treatment of FETs having insulated gates [IGFET] using self-aligned silicidation providing different silicide thicknesses on gate electrodes and on source regions or drain regions
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D64/00—Electrodes of devices having potential barriers
    • H10D64/01—Manufacture or treatment
    • H10D64/015—Manufacture or treatment removing at least parts of gate spacers, e.g. disposable spacers
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D64/00—Electrodes of devices having potential barriers
    • H10D64/01—Manufacture or treatment
    • H10D64/017—Manufacture or treatment using dummy gates in processes wherein at least parts of the final gates are self-aligned to the dummy gates, i.e. replacement gate processes
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D64/00—Electrodes of devices having potential barriers
    • H10D64/01—Manufacture or treatment
    • H10D64/021—Manufacture or treatment using multiple gate spacer layers, e.g. bilayered sidewall spacers
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D64/00—Electrodes of devices having potential barriers
    • H10D64/60—Electrodes characterised by their materials
    • H10D64/66—Electrodes having a conductor capacitively coupled to a semiconductor by an insulator, e.g. MIS electrodes
    • H10D64/667—Electrodes having a conductor capacitively coupled to a semiconductor by an insulator, e.g. MIS electrodes the conductor comprising a layer of alloy material, compound material or organic material contacting the insulator, e.g. TiN workfunction layers
    • H10D64/668—Electrodes having a conductor capacitively coupled to a semiconductor by an insulator, e.g. MIS electrodes the conductor comprising a layer of alloy material, compound material or organic material contacting the insulator, e.g. TiN workfunction layers the layer being a silicide, e.g. TiSi2
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/01—Manufacture or treatment
    • H10D84/0123—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs
    • H10D84/0126—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs the components including insulated gates, e.g. IGFETs
    • H10D84/013—Manufacturing their source or drain regions, e.g. silicided source or drain regions
    • H10D84/0133—Manufacturing common source or drain regions between multiple IGFETs
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/01—Manufacture or treatment
    • H10D84/0123—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs
    • H10D84/0126—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs the components including insulated gates, e.g. IGFETs
    • H10D84/0135—Manufacturing their gate conductors
    • H10D84/0137—Manufacturing their gate conductors the gate conductors being silicided
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/01—Manufacture or treatment
    • H10D84/02—Manufacture or treatment characterised by using material-based technologies
    • H10D84/03—Manufacture or treatment characterised by using material-based technologies using Group IV technology, e.g. silicon technology or silicon-carbide [SiC] technology
    • H10D84/038—Manufacture or treatment characterised by using material-based technologies using Group IV technology, e.g. silicon technology or silicon-carbide [SiC] technology using silicon technology, e.g. SiGe
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]

Landscapes

  • Electrodes Of Semiconductors (AREA)
  • Insulated Gate Type Field-Effect Transistor (AREA)
  • Thin Film Transistor (AREA)
  • Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
CNB2005800228619A 2004-07-06 2005-03-10 半导体结构和形成金属氧化物半导体结构的方法 Expired - Fee Related CN100461463C (zh)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US10/885,462 US7705405B2 (en) 2004-07-06 2004-07-06 Methods for the formation of fully silicided metal gates
US10/885,462 2004-07-06

Publications (2)

Publication Number Publication Date
CN1981386A CN1981386A (zh) 2007-06-13
CN100461463C true CN100461463C (zh) 2009-02-11

Family

ID=35540415

Family Applications (1)

Application Number Title Priority Date Filing Date
CNB2005800228619A Expired - Fee Related CN100461463C (zh) 2004-07-06 2005-03-10 半导体结构和形成金属氧化物半导体结构的方法

Country Status (7)

Country Link
US (2) US7705405B2 (enExample)
EP (1) EP1807875A4 (enExample)
JP (2) JP2008506253A (enExample)
KR (1) KR100945785B1 (enExample)
CN (1) CN100461463C (enExample)
TW (1) TWI364796B (enExample)
WO (1) WO2006014188A2 (enExample)

Families Citing this family (27)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7271455B2 (en) * 2004-07-14 2007-09-18 International Business Machines Corporation Formation of fully silicided metal gate using dual self-aligned silicide process
US7118997B2 (en) * 2005-01-28 2006-10-10 International Business Machines Corporation Implantation of gate regions in semiconductor device fabrication
US20060183323A1 (en) * 2005-02-14 2006-08-17 Omnivision Technologies, Inc. Salicide process using CMP for image sensor
US7732312B2 (en) * 2006-01-24 2010-06-08 Texas Instruments Incorporated FUSI integration method using SOG as a sacrificial planarization layer
US20070298573A1 (en) * 2006-06-22 2007-12-27 Chien-Ting Lin Semiconductor device and method for manufacturing the same
US7410854B2 (en) * 2006-10-05 2008-08-12 Taiwan Semiconductor Manufacturing Company, Ltd. Method of making FUSI gate and resulting structure
JP5464239B2 (ja) * 2006-10-11 2014-04-09 富士通セミコンダクター株式会社 半導体装置の製造方法
US8652912B2 (en) * 2006-12-08 2014-02-18 Micron Technology, Inc. Methods of fabricating a transistor gate including cobalt silicide
US7704835B2 (en) * 2006-12-29 2010-04-27 Intel Corporation Method of forming a selective spacer in a semiconductor device
US8999786B1 (en) 2007-03-20 2015-04-07 Marvell International Ltd. Reducing source contact to gate spacing to decrease transistor pitch
KR100896862B1 (ko) * 2007-05-18 2009-05-12 주식회사 동부하이텍 반도체 소자의 제조방법
WO2009019837A1 (ja) 2007-08-07 2009-02-12 Panasonic Corporation 炭化珪素半導体素子およびその製造方法
JP2009182089A (ja) * 2008-01-30 2009-08-13 Panasonic Corp 半導体装置の製造方法
US7939389B2 (en) * 2008-04-18 2011-05-10 Semiconductor Energy Laboratory Co., Ltd. Semiconductor device and method for manufacturing the same
CN102074479B (zh) * 2009-11-24 2012-08-29 中国科学院微电子研究所 半导体器件及其制造方法
US8664070B2 (en) * 2009-12-21 2014-03-04 Taiwan Semiconductor Manufacturing Company, Ltd. High temperature gate replacement process
US8133746B2 (en) * 2010-03-01 2012-03-13 International Business Machines Corporation Method for semiconductor gate hardmask removal and decoupling of implants
US8431453B2 (en) * 2011-03-31 2013-04-30 Taiwan Semiconductor Manufacturing Company, Ltd. Plasma doping to reduce dielectric loss during removal of dummy layers in a gate structure
US8432002B2 (en) * 2011-06-28 2013-04-30 International Business Machines Corporation Method and structure for low resistive source and drain regions in a replacement metal gate process flow
CN102956504A (zh) * 2012-10-25 2013-03-06 上海宏力半导体制造有限公司 改善多晶硅耗尽的方法以及mos晶体管
JP2014135353A (ja) * 2013-01-09 2014-07-24 National Institute Of Advanced Industrial & Technology 半導体装置の製造方法
US10276562B2 (en) * 2014-01-07 2019-04-30 Taiwan Semiconductor Manufacturing Co., Ltd. Semiconductor device with multiple threshold voltage and method of fabricating the same
US9478631B2 (en) * 2014-06-04 2016-10-25 Taiwan Semiconductor Manufacturing Company Limited Vertical-gate-all-around devices and method of fabrication thereof
US11088030B2 (en) 2015-12-30 2021-08-10 Taiwan Semiconductor Manufacturing Co., Ltd. Semiconductor device and a method for fabricating the same
JP6808977B2 (ja) * 2016-05-30 2021-01-06 セイコーエプソン株式会社 流路継手および液体噴射装置
JP2017213703A (ja) * 2016-05-30 2017-12-07 セイコーエプソン株式会社 流路継手および液体噴射装置
US10290739B2 (en) 2017-09-29 2019-05-14 Taiwan Semiconductor Manufacturing Co., Ltd. Device and method of dielectric layer

Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20020072231A1 (en) * 2000-12-08 2002-06-13 United Microelectronics Corp. Method of forming a self-aligned silicide
US20030073269A1 (en) * 1998-08-12 2003-04-17 Tran Luan C Low voltage high performance semiconductor devices and methods
US6562718B1 (en) * 2000-12-06 2003-05-13 Advanced Micro Devices, Inc. Process for forming fully silicided gates
US6686248B1 (en) * 2001-04-03 2004-02-03 Advanced Micro Devices, Inc. Method of fabricating a semiconductor device having a MOS transistor with a high dielectric constant material
CN1599078A (zh) * 2003-09-15 2005-03-23 台湾积体电路制造股份有限公司 形成具有完全硅化结构的半导体组件及晶体管的方法

Family Cites Families (17)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6100173A (en) * 1998-07-15 2000-08-08 Advanced Micro Devices, Inc. Forming a self-aligned silicide gate conductor to a greater thickness than junction silicide structures using a dual-salicidation process
JP3168992B2 (ja) * 1998-09-08 2001-05-21 日本電気株式会社 半導体装置の製造方法
US6211000B1 (en) * 1999-01-04 2001-04-03 Advanced Micro Devices Method of making high performance mosfets having high conductivity gate conductors
JP2000252462A (ja) * 1999-03-01 2000-09-14 Toshiba Corp Ｍｉｓ型半導体装置及びその製造方法
US6620718B1 (en) 2000-04-25 2003-09-16 Advanced Micro Devices, Inc. Method of forming metal silicide regions on a gate electrode and on the source/drain regions of a semiconductor device
US6376320B1 (en) * 2000-11-15 2002-04-23 Advanced Micro Devices, Inc. Method for forming field effect transistor with silicides of different thickness and of different materials for the source/drain and the gate
US6475874B2 (en) * 2000-12-07 2002-11-05 Advanced Micro Devices, Inc. Damascene NiSi metal gate high-k transistor
US6518137B2 (en) * 2001-01-19 2003-02-11 United Microelectronics Corp. Method for forming steep spacer in a MOS device
US6555453B1 (en) 2001-01-31 2003-04-29 Advanced Micro Devices, Inc. Fully nickel silicided metal gate with shallow junction formed
KR100399357B1 (ko) * 2001-03-19 2003-09-26 삼성전자주식회사 코발트 실리사이드를 이용한 반도체 장치 및 그 형성 방법
JP3485103B2 (ja) * 2001-04-19 2004-01-13 セイコーエプソン株式会社 Ｍｏｓ型トランジスタ及びその製造方法
JP2004039943A (ja) * 2002-07-05 2004-02-05 Renesas Technology Corp 半導体装置の製造方法
US6846734B2 (en) * 2002-11-20 2005-01-25 International Business Machines Corporation Method and process to make multiple-threshold metal gates CMOS technology
JP4515077B2 (ja) * 2003-11-13 2010-07-28 富士通株式会社 半導体装置の製造方法
US7148143B2 (en) * 2004-03-24 2006-12-12 Texas Instruments Incorporated Semiconductor device having a fully silicided gate electrode and method of manufacture therefor
US7338888B2 (en) * 2004-03-26 2008-03-04 Texas Instruments Incorporated Method for manufacturing a semiconductor device having a silicided gate electrode and a method for manufacturing an integrated circuit including the same
US7183187B2 (en) * 2004-05-20 2007-02-27 Texas Instruments Incorporated Integration scheme for using silicided dual work function metal gates

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20030073269A1 (en) * 1998-08-12 2003-04-17 Tran Luan C Low voltage high performance semiconductor devices and methods
US6562718B1 (en) * 2000-12-06 2003-05-13 Advanced Micro Devices, Inc. Process for forming fully silicided gates
US20020072231A1 (en) * 2000-12-08 2002-06-13 United Microelectronics Corp. Method of forming a self-aligned silicide
US6686248B1 (en) * 2001-04-03 2004-02-03 Advanced Micro Devices, Inc. Method of fabricating a semiconductor device having a MOS transistor with a high dielectric constant material
CN1599078A (zh) * 2003-09-15 2005-03-23 台湾积体电路制造股份有限公司 形成具有完全硅化结构的半导体组件及晶体管的方法

Also Published As

Publication number Publication date
JP5400913B2 (ja) 2014-01-29
US20060006476A1 (en) 2006-01-12
US20090029515A1 (en) 2009-01-29
KR100945785B1 (ko) 2010-03-08
TWI364796B (en) 2012-05-21
US8178433B2 (en) 2012-05-15
WO2006014188A2 (en) 2006-02-09
JP2008506253A (ja) 2008-02-28
TW200618119A (en) 2006-06-01
EP1807875A2 (en) 2007-07-18
JP2012124519A (ja) 2012-06-28
US7705405B2 (en) 2010-04-27
WO2006014188A3 (en) 2006-11-23
KR20070029799A (ko) 2007-03-14
CN1981386A (zh) 2007-06-13
EP1807875A4 (en) 2008-11-19

Similar Documents

Publication Publication Date Title
CN100461463C (zh) 半导体结构和形成金属氧化物半导体结构的方法
US10211095B2 (en) High performance middle of line interconnects
CN1943027B (zh) Cmos硅化物金属栅集成
US10340355B2 (en) Method of forming a dual metal interconnect structure
US9917014B2 (en) Vertical air gap subtractive etch back end metal
JP4144884B2 (ja) Ｃｍｏｓトランジスタの製造方法
US7682968B2 (en) Self-aligned metal to form contacts to Ge containing substrates and structure formed thereby
US10707132B2 (en) Method to recess cobalt for gate metal application
JP2002151690A (ja) Ｍｏｓｆｅｔデバイスの製造方法
JPH11261063A (ja) 半導体装置の製造方法
US20080299767A1 (en) Method for Forming a Semiconductor Device Having a Salicide Layer
JP2001102583A (ja) Ｍｏｓｆｅｔの製造を目的とした置き換えゲートとしてシリコンゲルマニウムおよびその他の合金の使用
CN104681535A (zh) 半导体器件的接触件结构

Legal Events

Date Code Title Description
C06 Publication
PB01 Publication
C10 Entry into substantive examination
SE01 Entry into force of request for substantive examination
C14 Grant of patent or utility model
GR01 Patent grant
TR01 Transfer of patent right

Effective date of registration: 20171117

Address after: Grand Cayman, Cayman Islands

Patentee after: GLOBALFOUNDRIES INC.

Address before: American New York

Patentee before: Core USA second LLC

Effective date of registration: 20171117

Address after: American New York

Patentee after: Core USA second LLC

Address before: American New York

Patentee before: International Business Machines Corp.

TR01 Transfer of patent right
CF01 Termination of patent right due to non-payment of annual fee

Granted publication date: 20090211

Termination date: 20190310

CF01 Termination of patent right due to non-payment of annual fee