CN100433319C - 集成连接装置及制造方法 - Google Patents
集成连接装置及制造方法 Download PDFInfo
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- CN100433319C CN100433319C CNB2004800233383A CN200480023338A CN100433319C CN 100433319 C CN100433319 C CN 100433319C CN B2004800233383 A CNB2004800233383 A CN B2004800233383A CN 200480023338 A CN200480023338 A CN 200480023338A CN 100433319 C CN100433319 C CN 100433319C
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Abstract
本发明涉及一种连接装置,它包括外导电结构(44),其至少部分地或完全地被放置在不导电的绝缘层(34、36)的切口(recess)(37)中。在切口(37)的底部,在绝缘层(34、36)的一侧上放置内导电结构(22),并且在接触区域中,它邻接外导电结构(44)。在切口(37)的另一侧上的外导电结构(44)上设置接触表面。接触区域和接触表面彼此不重叠或仅部分重叠。当以法线方向观察时,切口(37)的底部以这种方式布置,即它至少重叠接触表面的一半或其全部,这样使绝缘层(34、36)中的阶梯位于主电流通路外面的切口(37)的边缘上,该主电流通路在接触表面和内导电结构(22)之间延伸。
Description
本发明涉及一种集成连接装置,其包含衬底、远离衬底的外导电结构和靠近衬底的内导电结构。在衬底的主区域(main area)中布置了多个电子元件,例如诸如晶体管之类的半导体元件。
例如在国际专利申请WO 03/003458A2中公开了这种集成电路装置,其中外导电结构是包含焊接区和测试区的焊盘(bonding pad)。在已知的集成电路装置中,在具有互连的两个金属化层之间布置了具有所谓的过孔(via)的另一金属化层。在该金属化层的过孔中,在集成电路装置工作期间,电流基本上以主区域的法线方向或与该法线方向相反的方向进行传导,而不是与主区域平行或相对于法线方向横切。
虽然存在大量类型的过孔,但是过孔共同具有下述:
-在过孔中主要发生在主区域的法线方向或与该法线方向相反的方向的电流,而不是在与主区域平行的方向,
-通过截面的大部分截面面积平行于主区域或者以完全重叠下面的互连或上面的互连的方式来布置它们,以及
-过孔的截面不与上面或下面的互连重叠,也就是说,截面相对于互连发生偏移,该过孔的截面不影响集成电路装置的功能,也就是说,尤其不被用作集成电路装置的功能所需要的导电连接。
一方面具有互连和过孔的金属化层以及另一方面只具有过孔的金属化层的制造是集成电路装置的制造中惯用且公认的技术。根据工艺工程,如果金属化层的过孔具有彼此相同的尺寸,则这是有利的。相反,金属化层的互连具有彼此显著不同的轮廓.长度例如是互连宽度的多倍。
然而,本发明的目的是详细说明一种改进的连接装置,其尤其具有与已知连接装置相比改进的电性能。而且,本发明打算详细说明一种制造方法。
涉及连接装置的该目的是通过具有专利的权利要求1的特征的连接装置来实现的。在从属权利要求中详细说明了改进。
本发明尤其是基于下述考虑,即随着在集成电路装置的制造中每个新技术的产生,对金属化的需求增大了。特别是在双极和CMOS技术的情况中,尽管尺寸非常小,但仍然需要非常高的体截面积电流密度,例如大于1、大于5或大于10毫安每平方微米,或者非常低的体电阻,这通过铜金属化来实现。由于迄今还没有用于铜表面的成本划算且制造已被证实的安装技术,因此迄今为止铝已被用作最后的金属化平面。然而,与铜相比,铝具有较低的载流能力。由于这些事实,与具有相同尺寸的铜结构相比,铝焊盘只能加载较低的绝对电流,或者对电迁移的阻力更少。因此,焊盘成为关键的电路部分,其对整个产品的寿命具有显著的影响。未来所需要的电流密度将增大。而且,由于与附加功能相关的增大的集成密度,将需要更小的测试和安装焊盘。这意味着每焊盘的电流密度将进一步增大。
而且,本发明尤其是基于下述考虑,即过孔金属化层可以被布置在具有连接的金属化层下面。然而,这将引起临界空间阶梯(step),也就是说,包括例如氧化物、具有小于3.7的相对介电常数的材料、氟硅玻璃(FSG)、聚酰亚胺或氮化硅的电介质。电介质中的阶梯会导致导电层厚度的收缩或局部减小,并因此导致载流能力降低,这将在下面参考图4进行更详细地解释。如果在这些阶梯上淀积金属化,则由于工艺影响,层厚度在阶梯处减小到例如在平面区域中层厚度的约50%的值。这又具有电流密度在阶梯处增大的效应。因此,由于几何形状或厚度变小和因此局部增大的电流密度,结果电流密度增大。
它对在镶嵌(damascene)结构中产生的互连上的铝焊盘特别有效,迄今为止该互连已经通过嵌入氧化层中的过孔(所谓的焊盘过孔)被连接到最后的镶嵌布线平面,例如铜。铝层厚度通常具有600nm和1200nm之间的值。电流通过“焊盘过孔”和与其连接的氧化边缘以独立的方向流动。平面铝区域用于测试和/或作为安装区域,例如用于焊线或用于在倒装片技术中使用的所谓的焊接粘合。也可以只用作测试焊盘。在整个区域土用铜铺在焊盘下面的障碍在于下述事实,由于在用于连接和用于测试的铝焊盘的区域下的机械稳定性,所以铜布线是不利的。
因此,除在引言中提到的特征之外,根据本发明的集成连接装置还具有以下特征:
-当以内导电结构的该区域的法线方向观察时,接触带(contactzone)不与接触区域重叠或仅部分重叠,该内导电结构邻接在外导电结构和内导电结构之间的接触带,并且
-当以法线方向观察时,完全或部分包含外导电结构的切口(cutout)的底部以这样的方式布置,即它至少重叠接触区域的一半或重叠整个接触区域。
根据本发明的电路装置具有以下效果,特别是在上述铝焊盘的情况下,在其处电流密度增加的电介质阶梯不在主电流通路中出现。主电流通路在其中流动例如相对于流过接触区域的总电流的大于百分之五十的电流。小部分的电流例如通过外导电结构的不同电流通路来流动经过该连接装置.由于现在电流密度均匀且不再局部增加,因此提高了产品的可靠性。特别是,降低了电迁移效应。而且,可以在处于内导电结构和外导电结构之间的接触带中和处于平面区域上的该接触带外部的主电流通路中制造阻挡层,使得在阻挡层使用期限中几乎不发生局部缺陷。结果,再次显著增加了集成电路装置的寿命。
在根据本发明的电路装置的情况下,通过除去在载流带的区域中外导电结构和内导电结构之间的氧化物来避免临界阶梯。外互连以平面方式邻接内导电结构,特别是在载流带中,特别是在接触区域50和最近的内互连22之间的具有特别高电流密度的带中。这些措施产生了许多技术效果:
-避免了在接触区域50和最近的内互连22之间的载流区域中的临界阶梯,
-可允许的电流密度以保持相同的可靠性来增加或者电流密度的可靠性的显著增加保持不变,
-对电路设计有利;举例来说,电流传导需要更小的面积,
-除布图改变之外,无需改变先前的工艺次序,
-在阶梯处的层中不再能够产生局部缺陷;这进一步提高了可靠性,
-可以以保持相同的可靠性来使用更高的绝对电流,这导致了电路设计中更多结构的可能性;举例来说,每芯片更少数量的连接区域是可能的,
-通过根据本发明的集成电路装置可以实现高的机械需求。这样,在没有导电结构的阻挡层或衬底附近的导电结构未被破坏的情况下,可以机械地加载接触区域。
在一个改进中,外导电结构在一个部分中用作用于金属化层中横向电流传输的互连,该部分优选长于10nm或长于1微米或长于10微米或长于100微米。该部分提高了机械稳定性,放宽了设计和/或导致所需金属化层的数量减少,如果外金属化层以目标的(targeted)方式被利用来布线并且不仅仅用于连接的话。
在下一改进中,内导电结构包含靠(bear)在接触带上由铜或铜合金制成的主导电体或导电芯。导电芯传导例如流过导电结构的百分之九十的电流。远离衬底的外导电结构包含由铝或铝合金制成的主导电体。此外,外导电结构在接触带处包含阻挡层,优选为由钽、钛、氮化钛、氮化钽制成的层或这些材料的层的组合。阻挡层阻止铜渗透到铝中并防止发生体积变化,该体积变化促进电迁移并削弱连接例如粘合连接(bonding connection)的质量。而且,在该改进的情况下,可以将铝的良好粘合能力与铜的高导电率结合起来。
在另一改进中,在至少一个边缘区域中用钝化层或钝化层序列(sequence)来覆盖外导电结构,优选沿着其远离衬底的整个边缘。钝化层例如阻止湿气在远离衬底的互连处进入集成电路装置中。
在另一改进中,外导电结构还在内导电结构侧面处伸出接触带外,该内导电结构侧面远离外导电结构的承载接触区域的那个部分。特别是,伸出大于10nm(或大于100nm)。以这种方式形成用于可填充由电迁移引起的空隙的材料的储集层(reservoir)。优选将伸出区域连接到不比远离衬底的互连更远的部分.
在另一改进中,外导电结构具有至少一个靠在绝缘层上的边缘区域。特别是,这与外导电结构的整个边缘区域有关.可以通过这种措施来方便外导电结构的构图.
如果在制造金属化层期间使用例如CMP方法(化学机械抛光),则界面是平面区域。例如由于在光掩模的曝光期间减少了反射,因此在金属化层之间尽可能平坦的区域简化了进一步的处理过程.
在下一改进中,在最远离衬底的外金属化层和靠近衬底最近的金属化层之间没有布置包含下述结构的金属化层,该结构在集成电路装置工作期间主要在主区域的法线方向或与该法线方向相反的方向传导电流,也就是说,该金属化层只包含过孔。
另一方面,本发明涉及一种用于制造集成电路装置的方法,特别是根据本发明或其改进之一的电路装置。因此上述技术效果对该制造方法也是有效的。
在根据本发明的方法的另一改进中,通过具有最后的平坦化步骤的镶嵌技术来制造靠近衬底的金属化层。镶嵌技术特别(但不仅仅)适用于铜互连。作为可选的或另外的方法,通过淀积层并随后在以光刻法构图该层来制造外金属化层。该工序特别适用于铝层或含铝层的制造。
下面参考附图来说明本发明的示例性实施例,其中:
图1示出穿过具有铜导电结构和铝焊接的集成电路装置的截面,
图2示出集成电路装置的平面图,
图3示出在集成电路装置的制造期间的方法步骤,以及
图4示出穿过未使用本发明的集成电路装置的截面。
图1示出集成电路装置10,它包含具有多个集成半导体元件的衬底(未示出),例如硅衬底。从衬底开始,在集成电路装置中有多个金属化层,图1中示出了三个金属化层12、14和16。金属化层12包含铜过孔,每个铜过孔包含铜芯18和导电阻挡层,导电阻挡层例如由钽、氮化钽、氮化钛或其组合制成。在铜的淀积期间,阻挡层完成扩散阻挡层、增进粘合和定位的功能(衬垫(liner)功能).将金属化层12的垂直导电结构嵌入绝缘材料20中,例如二氧化硅中。
金属化结构14包含多个导电结构,特别是垂直导电结构和互连,其中图1中示出了具有铜芯24的互连22。金属化层14主要是互连平面,但是其中也可以布置过孔。铜芯24被阻挡层26向下并向侧面包围,该阻挡层26与互连22相连并由导电材料制得,例如由氮化钛制得。在金属化层14的导电结构之间,特别是在其互连之间布置电绝缘的绝缘材料28,例如二氧化硅。金属化层14还包含与金属化层12邻接的可选的停止层30。停止层30包括电绝缘材料,例如氮化硅,并用作蚀刻停止或抛光停止。举例来说,停止层30具有50nm的厚度。举例来说,金属化层14的总厚度具有200nm和5μm之间的值。
平坦界面32位于金属化层14和金属化层16之间,其邻接在导电结构22的区域中的铜芯24。金属化层16包含靠在界面32上的可选的停止层,或由电绝缘材料制成的金属钝化层34,例如由氮化硅制成。在示例性实施例中,停止层具有50nm的厚度。邻接停止层34,金属化层16包含由不同于停止层的材料制成的电绝缘的绝缘层36,例如由二氧化硅制成。在导电结构22之上,绝缘层36和停止层34被具有左侧切口边缘38和右侧切口边缘40的切口37穿透,使得接触区域B1来被覆盖。
在另一示例性实施例中,仅使用停止层34。在该情况下不存在绝缘层36。
切口边缘38和40之间的距离A1等于导电结构22的侧壁之间的距离A2的多倍。距离A2与导电结构22的宽度相同。在示例性实施例中,距离A1为90μm(微米)。举例来说,距离A2为15μm。导电结构22位于左侧切口边缘38的附近。在具有切口边缘38和40的切口的中心部分和右侧部分下面,没有导电结构,特别是没有互连位于金属化层28中。优选没有互连,特别是没有铜互连被直接布置于接触区域和衬底之间,正如以衬底表面的法线方向所观察到的。
金属化层16另外包含可选的导电阻挡层42的区域,其例如包括氮化钛,并例如具有50nm的厚度。图1示出在具有切口边缘38和40的切口37的区域中的这种区域。图1所示的区域在界面32处的切口底部、切口37的侧壁处并以重叠绝缘层36上的切口37的边缘的方式延伸。在所有情况下,重叠例如为300nm。金属化层16还包含多个由铝层构成的铝结构,图1中示出其中的一个铝结构44。铝结构44例如具有600nm和1.2μm之间的值的厚度并与阻挡层42同时被构图。
电路装置10另外包含钝化层序列,该钝化层序列邻接绝缘层36并具有下部电绝缘层和上部电绝缘层,下部电绝缘层例如是二氧化硅层46,上部电绝缘层例如是氮化硅层48。在示例性实施例中二氧化硅层46和氮化硅层48的每个都具有300nm的厚度。
在区域B1之上,二氧化硅层46和氮化硅层48被切口50穿透,在其边缘之间为距离A3。在示例性实施例中距离A3为60μm,切口50例如是矩形或正方形。举例来说,在切口50中布置粘合连接52。
图1另外示出法线N的方向,相对该法线,互连22的接触带一方面与阻挡层42以及另一方面与切口50相对彼此偏移。当以法线N的方向观察时,切口37的底部还完全与切口50重叠。法线N的方向还相当于半导体衬底的主区域的法线方向。
图2示出集成电路装置10的平面图,金属化层14上面的层以透明方式来说明。线示出了切口37的轮廓的位置。在切口37的左侧四分之一的下面布置了金属化层14中互连22的一半。切口37仅部分伸出到导电结构22上,这样,导电结构22用于在垂直方向和水平方向上的电流传输。在互连22的未与铝结构44重叠的端部处,过孔80位于金属化层12中。另一条线示出了铝结构44的位置,其还沿切口37外部的其外围靠在绝缘层36上。
在另一示例性实施例中,相反,切口37在所有边上伸出到导电结构22上,于是使得导电结构22具有过孔的功能,参见虚线81。
在可选示例性实施例中,互连22从金属化层14中的切口37被带向其它侧。还可以改变金属化层14内的方向。
如图2所示,用于接触区域的切口50完全重叠切口37的底部。举例来说,在垂直导电结构22的纵向上,切口37具有45μm的长度。
图2另外示出金属化层14的互连82,其例如平行于垂直导电结构22的纵轴。互连82同样包含铜芯和扩散阻挡层。互连82用于金属化层14中水平电流的传输。
图3示出在集成电路装置10的制造期间的方法步骤.该方法以方法步骤150开始,方法步骤150具有有源电子元件和在金属化层12下面的金属层的制造,并且还具有金属化层12的制造。
在随后的方法步骤152中制造金属化层14,例如借助于单镶嵌方法。在另一示例性实施例中,取代金属化层12和14,借助于双镶嵌方法制造金属化层,于是使得金属化层包含邻接金属化层16的常规互连金属化层和下面的常规过孔金属化层。
在下一方法步骤154中,将氮化硅层34和二氧化硅层36施加到金属化层14上,该金属化层14已经借助于例如CMP方法(化学机械抛光)被变平。随后在方法步骤156中构图氮化硅层34和二氧化硅层36。将光致抗蚀剂层施加于二氧化硅层36并选择性进行曝光和显影。
借助于已构图的光致抗蚀剂层,在蚀刻工艺中蚀刻二氧化硅层36,特别是借助于反应离子蚀刻。在这种情况下制造切口37的上部。当切口的底部到达氮化硅层34时结束蚀刻操作,使得氮化硅层34仍基本未被变薄。随后除去光致抗蚀剂层的残留物。
在除去光致抗蚀剂层的残留物之后,借助于例如各向异性蚀刻方法将切口37移动到集成电路装置10中,该各向异性蚀刻方法相对于铜选择性除去了氧化物和氮化物。在这种情况下,将二氧化硅层36和氮化硅层34的暴露区域都变薄。当切口37的底部到达铜芯24并且氮化硅已经完全从铜芯24中被除去时,结束蚀刻操作。通过此工序所实现的是,在光致抗蚀剂层的光致抗蚀剂的煅烧(incineration)期间不形成减小有效导电截面的氧化铜。
在方法步骤156之后,淀积阻挡层42和将由其制造铝结构44的铝层,参见方法步骤158和160。在随后的方法步骤中,在方法步骤162中借助于光刻方法来构图阻挡层42和铝层,制造铝结构44。
在下一方法步骤164中,淀积用于钝化的二氧化硅层46和氮化硅层48。借助于光刻方法,然后在方法步骤166中构图二氧化硅层46和氮化硅层48,制造切口50。可选地,例如聚酰亚胺层可以被施加到钝化并独立地或与层46和48共同地被构图。
在方法步骤168中结束该方法,例如使用区域B1进行集成电路装置的测试,随后借助于焊线52通过区域B1来连接该集成电路装置,并将集成电路装置浇铸到例如外壳中。
在参考图1至3所说明的示例性实施例中,两个金属化层14和16在界面32处彼此邻接,二者的金属化层都包含互连,该互连在集成电路装置10工作期间也在水平方向上传导电流。这意味着在具有互连的金属化层16和14之间不存在金属化层和专门包含用于垂直电流传输的结构的金属化层,也就是说具有迄今已被称作过孔的导电结构。也不存在用于将一个金属化层的导电结构与另一个金属化层的导电结构绝缘的绝缘层。
在其它示例性实施例中,改变铜芯24与铝结构44的重叠;举例来说,切口37的左侧边缘38靠在铜芯24上或者部分伸入铜芯24中,特别是在主电流通路的外面。也可以改变在铝结构44上钝化的重叠。
图4通过箭头200指示用于切口37a的边缘38a的可选位置.箭头202指示用于切口37a的边缘40a的可选位置.在这种情况下,切口37a的底部不与相当于切口50的切口50a中的接触区域B1重叠.在边缘40a处或在由箭头202所示的位置处的氧化物阶梯邻接在互连22a和切口50a之间的主电流通路,并使主电流通路收缩(constrict)。主电流通路传导还流过互连22a的例如大于90%的电流。在阶梯处产生电流密度的增加。通过将边缘40a从箭头202所示的位置移动到更靠近图1所示的位置,可以更加减少电介质阶梯的有害影响,特别是氧化物阶梯的有害影响,将右侧边缘40a布置在更靠近图1所示的位置处。在这种情况下,制造步骤几乎相同,只是改变了布图。
在本发明的情况下,由箭头200标记的左侧边缘38a的位置是容许的,但由箭头202标记的右侧边缘40a的位置是不容许的。这是因为边缘38a不使在互连22a和接触区域50a之间的主电流通路收缩.
在位置200处,如果从互连22a通过铝结构44a到切口50a发生了强的电子流,则切口40a的左侧边缘38a可以仅形成有限的供给储集层,用于填充由在铝结构44a中的电迁移造成的空腔。所述储集层部分地位于绝缘层36a上。然而,如果边缘38a被布置在距互连22a一定距离处,则在切口37a中有利地产生铝储集层。显著地提高了电路装置10的电性能,特别是对于电迁移的阻力。
在另一示例性实施例中,接触区域只是测试区域,其例如小于20微米×20微米。相反,用于外部接触的连接区域大于40微米×40微米。
取代提到的外部接触的可能性,还可以使用其它技术,例如倒装片技术或焊液扩散法。
在介电层36中有切口37的情况下,没有进行用于倒圆(rounding)边缘并由此用于倒圆阶梯的另外的措施。尽管如此,仍然可以在主电流通路中避免阶梯。
在另一示例性实施例中,外导电结构主要还包含已经通过抛光法平坦化的铜,以便不会发生超出切口37的上边缘的铜的重叠。
在又一示例性实施例中,所有金属化层主要由铝或由另一合适的材料制成。
在介电层36中布置切口37,该介电层36是最远离衬底的介电层,并且通过光刻法构图的其切口优选地完全填充着集成的导电结构。换言之,在构图介电层36之后,例如借助于光刻法使所制造的切口中没有制造其它介电层,而集成了具有金属化层的导电结构。举例来说,只施加了钝化层。
Claims (26)
1、一种集成连接装置,
具有导电的外导电结构(44),其至少部分地或完全地被布置在电绝缘的绝缘层(34、36)的切口(37)中,
具有导电的内导电结构(22),其被布置在切口(37)一侧的底部处,并在切口(37)的底部处邻接外导电结构(44)于外导电结构(44)和内导电结构(22)之间的接触带中,
具有接触区域(B1),其被布置在切口(37)另一侧上的外导电结构(44)处,
当以内导电结构(22)的邻接接触带的区域的法线方向观察时,该接触带与该接触区域不重叠,
当以该法线方向观察时,切口(37)的底部以这种方式布置,即它至少重叠该接触区域的一半或重叠整个接触区域,
以及该外导电结构(44)具有至少一个邻接在该切口(37)外面的绝缘层(34、36)的边缘区域。
2、如权利要求1中所述的连接装置,其特征在于,切口(37)的边缘(38、40)在距外导电结构(44)的主电流通路一定距离处,该主电流通路位于该接触区域(B1)和内导电结构(22)之间,
和/或其特征在于,切口(37)的边缘不使该主电流通路收缩,
和/或其特征在于,切口(37)的边缘位于该主电流通路外面。
3、如权利要求2中所述的连接装置,其特征在于,所述距离大于10nm或大于100nm。
4、如权利要求1-3之一所述的连接装置,其特征在于,外导电结构(44)的一个部分用作金属化层(16)中横向电流传输的互连。
5、如权利要求4中所述的连接装置,其特征在于,所述部分长于10nm或长于1微米或长于10微米或长于100微米。
6、如权利要求1-3之一所述的连接装置,其特征在于,在远离具有该接触区域(B1)的部分的内导电结构(22)的一侧,该外导电结构(44)伸出该接触带外。
7、如权利要求6中所述的连接装置,其特征在于,该外导电结构(44)伸出该接触带外的部分大于10nm。
8、如权利要求1-3之一所述的连接装置,其特征在于,内导电结构(22)是金属化层(14)的一部分,该金属化层(14)还包含用于金属化层(14)中横向电流传输的互连。
9、如权利要求1-3之一所述的连接装置,其特征在于,该外导电结构(44)具有连接区域,在该连接区域处布置外部连接。
10、如权利要求9中所述的连接装置,其特征在于,所述外部连接是粘合连接(52)或焊料连接。
11、如权利要求1-3之一所述的连接装置,其特征在于,通过镶嵌技术来制造该内导电结构(22),
其特征在于,该外导电结构(44)包含由铝或铝合金制成的主导电体,
和/或其特征在于,该外导电结构(44)在接触带处包含阻挡层(42)。
12、如权利要求11中所述的连接装置,其特征在于,所述内导电结构包含由铜或铜合金制成的主导电体。
13、如权利要求12中所述的连接装置,其特征在于,铜的质量的比例大于90%。
14、如权利要求11中所述的连接装置,其特征在于,铝的质量的比例大于90%。
15、如权利要求11中所述的连接装置,其特征在于,所述阻挡层为由钽或钛或氮化钽或氮化钛制成的层,或者为包括这些材料的层序列的层。
16、如权利要求1-3之一所述的连接装置,其特征在于,在至少一个边缘区域中,将该外导电结构(44)用钝化层或钝化层序列(46、48)来覆盖。
17、如权利要求16中所述的连接装置,其特征在于,在至少一个边缘区域中的所述覆盖是沿着该接触区域的整个外围。
18、如权利要求16中所述的连接装置,其特征在于,所述钝化层序列(46、48)是二氧化硅层(46)和氮化硅层(48)。
19、如权利要求1-3之一所述的连接装置,其特征在于,该外导电结构(44)具有围绕该切口(37)延伸并邻接该切口(37)外面的绝缘层(34、36)的边缘区域。
20、如权利要求1-3之一所述的连接装置,其特征在于,该接触带是平面带,
和/或其特征在于,该集成连接装置被包含在具有半导体衬底的集成电路装置(10)中。
21、如权利要求20中所述的连接装置,其特征在于,所述半导体衬底的主区域带有多个集成半导体元件。
22、如权利要求1-3之一所述的连接装置,其特征在于,在该外导电结构(44)和该内导电结构(22)之间没有布置仅包含如下结构的金属化层,该结构在集成电路装置(10)工作期间只以半导体衬底的主区域的法线方向或与该法线方向相反的方向传导电流。
23、一种用于制造集成电路装置(10)的方法,其中进行以下方法步骤:
在衬底的主区域中形成多个电子元件,
制造具有多个内导电结构(22、82)的内金属化层(14),至少一个内导电结构(22、82)被形成为一个互连(82),该互连在电路装置工作期间平行于该主区域传导电流,
邻接该内金属化层(14)制造具有多个外导电结构(44)的外金属化层,
至少一个外导电结构(44)在外导电结构(44)和内导电结构(22)之间的接触带中邻接内导电结构(22),
将该外导电结构(44)至少部分地或完全地布置在电绝缘的绝缘层(34、36)的切口(37)中,
在该外导电结构(44)处形成接触区域(B1),
当以内导电结构(22)的邻接该切口的底部的区域的法线(N)方向观察时,该接触带不与该接触区域重叠,
以及当以该法线方向观察时,该切口的底部以这种方式布置,即它至少重叠该接触区域的一半或重叠整个接触区域,
以及该外导电结构(44)具有至少一个邻接该切口(37)外面的绝缘层(34、36)的边缘区域。
24、如权利要求23中所述的方法,其特征在于,该方法用于制造具有如权利要求1-22之一所述的连接装置的集成电路装置(10)。
25、如权利要求23中所述的方法,其特征在于,至少一个外导电结构(44)被形成为另一互连(44),该互连在该电路装置工作期间平行于该主区域传导电流。
26、如权利要求23-25之一所述的方法,其特征在于,通过具有随后的平坦化步骤的镶嵌技术来制造该内金属化层,
和/或其特征在于,通过淀积层并随后借助于光刻法构图该层来制造该外金属化层(16)。
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- 2004-07-21 EP EP04766283A patent/EP1654760A1/de not_active Ceased
- 2004-07-21 JP JP2006523006A patent/JP4456112B2/ja not_active Expired - Fee Related
- 2004-07-21 CN CNB2004800233383A patent/CN100433319C/zh not_active Expired - Fee Related
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2006
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Also Published As
Publication number | Publication date |
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US20100007027A1 (en) | 2010-01-14 |
JP2007502532A (ja) | 2007-02-08 |
EP1654760A1 (de) | 2006-05-10 |
WO2005020321A1 (de) | 2005-03-03 |
US7964494B2 (en) | 2011-06-21 |
DE10337569B4 (de) | 2008-12-11 |
CN1836327A (zh) | 2006-09-20 |
US7619309B2 (en) | 2009-11-17 |
US20060192289A1 (en) | 2006-08-31 |
DE10337569A1 (de) | 2005-03-24 |
JP4456112B2 (ja) | 2010-04-28 |
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