CN100401503C - 半导体装置及其制造方法 - Google Patents

半导体装置及其制造方法 Download PDF

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Publication number
CN100401503C
CN100401503C CNB2005100738045A CN200510073804A CN100401503C CN 100401503 C CN100401503 C CN 100401503C CN B2005100738045 A CNB2005100738045 A CN B2005100738045A CN 200510073804 A CN200510073804 A CN 200510073804A CN 100401503 C CN100401503 C CN 100401503C
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Prior art keywords
semiconductor device
semiconductor chip
semiconductor
wiring layer
hole
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CNB2005100738045A
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CN1702853A (zh
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落合公
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Northeast Sanyo Semi-Conductive Co Ltd
Sanyo Electric Co Ltd
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Northeast Sanyo Semi-Conductive Co Ltd
Sanyo Electric Co Ltd
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Publication of CN1702853A publication Critical patent/CN1702853A/zh
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    • H05K3/32—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits
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Abstract

一种半导体装置及其制造方法，可不使工序复杂，提高安装时的强度及精度。在半导体衬底(10)的背面沿切割线(DL)形成槽(14)。进而形成从半导体衬底(10)的背面到达焊盘电极(11)的通孔(16)。在通孔(16)内形成埋入电极(18)，和其连接，形成沿切割线(DL)附近延伸的配线层(19)。在配线层(19)的端部形成导电端子(21)。然后，通过进行沿切割线(DL)的切割，完成在背面端部具有倾斜面1s的半导体装置(1)。在半导体装置(1)通过回流处理与电路衬底(30)连接时，流动性增强的导电膏覆盖导电端子(21)及倾斜面(1s)。在此，在半导体装置(1)外缘的电路衬底(30)上形成含有侧嵌条的导电膏(40a、40b)。

Description

半导体装置及其制造方法
技术领域
本发明涉及半导体装置及其制造方法，特别是涉及封装型半导体装置及其制造方法。
背景技术
近年来，作为封装型半导体装置，CSP(芯片尺寸封装Chip Size Package)受到人们的关注。CSP是具有和半导体芯片的外形尺寸大致相同尺寸的外形尺寸的小型封装。
目前，CSP的一种，可知有BGA(焊球阵列Ball GridArray)型半导体装置。该BGA型半导体装置中，在封装的一主面上格子状地排列多个由焊锡等金属部件构成的球状导电端子，并将其与搭载于封装的其它主面上的半导体芯片电连接。下面，参照附图说明现有例的BGA型半导体装置。
图9是说明现有例的半导体装置的剖面图。如图9所示，在半导体装置2的半导体芯片60A的表面形成有焊盘电极61。另外，半导体芯片60A的表面被密封件63(或支承体)覆盖。在半导体芯片60A上形成有从该背面贯通到焊盘电极61的通孔。在该通孔中形成有和焊盘电极61连接的埋入电极68。在半导体芯片60A背面的通孔露出的埋入电极68上形成有球状的导电端子71。
该半导体装置2在安装于形成有未图示的导电图案的电路衬底80上时，使电路衬底80和半导体芯片的背面对向，设置在该电路衬底80上。在此，在形成有未图示的导电图案的电路衬底80的主面上，在和导电端子71接触的位置利用例如印刷法形成有由例如焊锡构成的导电膏90。另外，在电路衬底80的主面上，在不形成导电膏90的区域形成有用于防止在半导体芯片60A的背面和电路衬底80之间产生空间的所谓的底层填料91。
导电膏90通过回流处理增加流动性，部分地覆盖导电端子71。由此，导电端子71和电路衬底80的未图示的导电图案电连接，同时，固定在电路衬底80上。
另外，关联的技术文献可举出例如以下的专利文献。
专利文献1：特开2003-309221号公报
专利文献2：特表2002-512436号公报
专利文献3：特开2003-229518号公报
但是，在介由导电膏90连接上述的现有例的半导体装置2和电路衬底80时，存在产生连接不良的问题。这是由于，形成于电路衬底80上的导电膏90的量被限制为少量，故有时在回流处理时，导电膏90不能准确地流到导电端子71和电路衬底80的未图示的导电图案两者上。另外，在为解决上述连接不良而增加导电膏90的量时，产生了回流处理时多于的导电膏使相邻的导电端子71短路这样的问题。另外，难于确认是否正确地连接着。
另外，即使介由导电膏90将半导体装置2和电路衬底80正确地连接，但由于导电膏的量少，故连接时的机械强度也不够。因此，在半导体芯片60A和电路衬底80之间形成所谓的由环氧树脂等构成的底层填料，抑制导电端子71间的短路，同时，加强上述机械强度。该底层填料的形成通常由半导体装置的用户进行，故存在用户进行安装时的工序增加这样的问题。
结果是，半导体装置的用户安装时的工序复杂，且安装时的精度降低。因此，本发明提供一种半导体装置及其制造方法，其不会使工序复杂，且可提高安装时的强度及精度。
发明内容
本发明的半导体装置是鉴于上述课题而开发的，其提供一种半导体装置，载置于电路衬底上，具有以下特征。
即，本发明的半导体装置包括：半导体芯片；焊盘电极，其形成于半导体芯片的表面上；倾斜面，其从半导体芯片的背面的端部倾斜到该半导体芯片的侧面；通孔，其从半导体芯片的背面贯通到焊盘电极的表面；绝缘膜，其形成于含有通孔的侧壁的半导体芯片的背面上；埋入电极，其经由绝缘膜形成于通孔中，且和焊盘电极电连接；配线层，其经由绝缘膜形成在含通孔在内的半导体芯片的背面上，和埋入电极连接，且在半导体芯片的倾斜面上延伸。在此，半导体装置使电路衬底和半导体芯片的背面相对而载置于电路衬底上。另外，本发明的半导体装置在上述结构的基础上，具有形成于配线层上的导电端子。
本发明的半导体装置在上述结构的基础上，在半导体芯片背面的端部形成有覆盖埋入电极上及所述倾斜面上的配线层(在形成导电端子时包括导电端子)的导电性嵌条。另外，本发明的半导体装置在上述结构的基础上，在半导体芯片的表面上形成有支承体。
本发明提供一种半导体装置的制造方法，其特征在于，包括：准备由切割线区分，且在表面上形成焊盘电极的半导体衬底，在半导体衬底的背面，沿切割线形成向半导体衬底的表面方向成尖头的槽的工序；形成从所述半导体衬底的背面到达所述半导体衬底的所述焊盘电极侧表面的通孔的工序；在槽内和所述通孔的侧壁以及除所述通孔外的半导体衬底的背面形成绝缘膜的工序；形成经由所述绝缘膜设置在所述通孔中并和焊盘电极电连接的埋入电极的工序；形成经由所述绝缘膜配置在含所述通孔在内的所述半导体芯片的背面上、和埋入电极连接且延伸到切割线附近的配线层的工序；通过沿切割线进行切割，将半导体衬底分割成多个半导体芯片的工序。另外，本发明的半导体装置的制造方法在上述工序的基础上，具有在配线层上形成导电端子的工序。
本发明的半导体装置的制造方法在上述工序的基础上，具有在半导体芯片的背面的端部形成覆盖埋入电极上及倾斜面上的配线层(在形成导电端子时包括导电端子)的导电性嵌条的工序。另外，本发明的半导体装置的制造方法在上述工序的基础上，具有在半导体芯片的表面上形成支承体的工序。
根据本发明，在将半导体装置安装在电路衬底上时，利用回流处理增加流动性的导电膏利用形成于半导体装置背面的倾斜面的表面张力沿该倾斜面朝向半导体芯片表面的方向流动，同时，沿电路衬底朝向半导体芯片的外部流动。由此，不仅导电端子，连半导体装置的背面的倾斜面也由导电膏覆盖。因此，可最大限度地抑制现有例中所见的导电端子和电路衬底的连接不良。另外，可提高将半导体装置连接到电路衬底上时的机械强度。
在正确地进行了所述连接时，从半导体装置的表面来看，存在从半导体装置的侧面溢出的导电膏(所谓的侧嵌条)。因此，进行上述连接的半导体装置的用户可通过观察该侧嵌条的有无，确认是否正确地进行了上述连接。
另外，由于所述倾斜面的表面张力，导电膏具有沿电路衬底朝向半导体装置外部流动的倾向，故与现有例相比，即使在电路衬底上形成大量的导电膏，也可以最大限度地抑制导电膏埋入相邻的导电端子间的空间。即，可最大限度地抑制导电端子间短路。
另外，由于可提高将半导体装置与电路衬底连接时的机械强度，且最大限度地避免导电端子间的短路，故可省略现有例所见的半导体装置的用户进行的底层填料的形成工序。
结果是，可不使工序复杂而提高安装时的强度及精度。
附图说明
图1是表示本发明实施例的半导体装置的制造方法的剖面图；
图2是表示本发明实施例的半导体装置的制造方法的剖面图；
图3是表示本发明实施例的半导体装置的制造方法的剖面图；
图4是表示本发明实施例的半导体装置的制造方法的剖面图；
图5是表示本发明实施例的半导体装置的制造方法的剖面图；
图6是表示本发明实施例的半导体装置及其制造方法的剖面图；
图7是说明本发明实施例的半导体装置的剖面图；
图8是说明本发明实施例的半导体装置的剖面图；
图9是说明现有例的半导体装置的剖面图。
具体实施方式
下面，参照附图详细说明本实施例的半导体装置的制造方法。图1～图5是表示本实施例的半导体装置的制造方法的剖面图。图6是表示本实施例的半导体装置及其制造方法的剖面图。图1～图6中表示构成半导体装置的半导体衬底中切割线DL附近。
首先，如图1所示，准备形成有未图示的电子器件的半导体衬底10。未图示的电子器件形成于半导体衬底10的第一主面即表面上。在此，在半导体衬底10的表面介由来图示的绝缘膜形成有从未图示的电子器件延伸的焊盘电极11。另外，焊盘电极11的个数不限于图2所示的个数(2个)。另外，在上述半导体衬底10上，在使上述焊盘电极11的局部露出的状态下，形成有由氧化硅膜或氮化硅膜构成的未图示的钝化膜。
在包括未图示的电子器件上及焊盘电极11上的半导体衬底10的表面上，覆盖它们而形成例如由环氧树脂等构成的树脂层12。另外，在半导体衬底10的表面上介由树脂层12形成支承体13。在形成于该表面上的未图示的电子器件为受光元件时，支承体13使用具有透明或半透明性状的材料、衬底、树脂或带等。在未图示的电子器件不是受光元件时，支承体13不限于透明或半透明性状。另外，该支承体13的形成根据未图示的电子器件或半导体装置的使用目的也可以省略。
其次，根据需要，研磨半导体衬底10的背面直至规定的厚度。即进行背面研磨。另外，也可以蚀刻该背面，除去由背面研磨产生的机械性损伤层。
其次，如图2所示，沿切割线DL在半导体衬底10的背面上形成槽14。该槽14通过例如使用切割片进行的切削形成。在此，槽14具有相对于半导体衬底10的背面以规定角度倾斜的倾斜面。该倾斜面从半导体衬底10的背面朝向该表面形成，汇聚于切割线DL。
其次，如图3所示，在半导体衬底10的背面上选择性地形成第一抗蚀层15。即，第一抗蚀层15在对应焊盘电极11的规定位置具有开口部。然后，以第一抗蚀层15为掩模，进行半导体衬底10及未图示的绝缘膜的蚀刻，形成从半导体衬底10的背面到达焊盘电极11的通孔16。然后，除去第一抗蚀层15。
另外，图3所示的通孔16形成直线形状，但可通过调节蚀刻条件，形成任意形状。另外，上述槽14也可以通过形成通孔16时的蚀刻和通孔16同时形成。此时，需要调节该蚀刻条件而形成槽14，使其具有以规定角度倾斜的倾斜面。此时，利用该蚀刻同时形成的通孔16形成圆锥形状。
另外，通孔16的形成不限于形成槽14后，也可以在形成槽14之前进行。不过，此时，在切削槽14时，其切削屑等有可能污染通孔16的底部。
其次，如图4所示，在含有通孔16的半导体衬底10的背面上形成例如由氧化硅膜或氮化硅膜构成的绝缘膜INS。在此，在通孔16底部的绝缘膜INS形成地比其它区域薄时，从半导体衬底10的背面整体蚀刻绝缘膜INS，仅除去通孔16底部的绝缘膜INS。或，以对应通孔16开口的未图示的抗蚀层为掩模，仅蚀刻除去通孔16的底部绝缘膜INS。另外，绝缘膜INS也可以仅在通孔16的侧壁作为侧壁绝缘膜形成。
其次，在含有通孔16内的半导体衬底10的背面上(即绝缘膜INS上)利用镀敷法或溅射法形成例如由铜(Cu)构成的埋入电极18及与其连接的配线层19。另外，在配线层19中残存的区域上形成第二抗蚀层17。在此，残存配线层19的区域是指从埋入电极18上至槽14内的倾斜面上的区域(从埋入电极18上至槽14内的切割线DL或其附近的区域)。然后，以第二抗蚀层17为掩模，蚀刻配线层19。由此，配线层19与焊盘电极11及埋入电极18电连接，同时，进行构图，使其向槽14的倾斜面上延伸。
另外，埋入电极18或配线层19不限于铜(Cu)，只要是可以由镀敷法或溅射法形成的，则也可以使用铝(Al)或铝合金等铜(Cu)以外的金属形成。另外，埋入电极18及配线层19既可以由各自不同的工序形成，也可以通过相同的工序由同一层形成。
其次，在除去第二抗蚀层17后，如图5所示，在配线层19上的规定位置形成导电端子21。形成导电端子21的上述规定位置如图所示，可以是对应埋入电极18的位置，但也可以是其它位置。导电端子21例如由焊锡等构成，利用印刷法及回流处理形成。
另外，在焊盘电极11及埋入电极18形成于半导体衬底的切割线DL附近的情况下，也可以省略配线层19的形成。
其次，如图6所示，通过沿切割线DL切割，分割半导体衬底10及其它各层，完成由半导体芯片10A及其它各层构成的半导体装置1。在此，在该半导体装置1的背面，形成从其半导体芯片10A的端部向侧面倾斜的倾斜面1s。
其次，参照附图说明将上述的半导体装置1安装在电路衬底上的情况。图7是说明本发明实施例的半导体装置的剖面图。图7表示半导体装置1连接在例如印刷线路板等电路衬底30上时两者的剖面。另外，在电路衬底30上形成有未图示的导电图案。
如图7所示，半导体装置1载置于电路衬底30上，使其背面(即形成有导电端子21侧的主面)与电路衬底80的表面(即形成有未图示的导电图案的一侧的主面)对向。
在此，在形成未图示的导电图案的电路衬底30的表面中，在和导电端子21相接的位置通过例如印刷法形成由例如焊锡或银(Ag)等构成的导电膏或导电性焊料(后述的回流处理之后表示为导电膏40a、40b)。
为介由上述导电膏连接半导体装置1和电路衬底30，进行回流处理(即热处理)。通过该回流处理增加了流动性的导电膏40a、40b通过半导体装置1背面的倾斜面1s(即形成配线层19的倾斜面1s)的表面张力沿该倾斜面1s向半导体装置1的表面方向流动，同时，沿电路衬底30的水平方向向半导体装置1的外部流动。由此，不但导电端子21，连倾斜面1s也由导电膏40a、40b覆盖。因此，可最大限度地抑制现有例所见的导电端子和电路衬底的连接不良。另外，可提高半导体装置连接在电路衬底上时的机械强度。
在正确地进行了上述连接时，从半导体装置1的表面来看，存在从半导体装置的侧面溢出的导电膏40a，即所谓的侧嵌条。因此，进行上述连接的半导体装置1的用户可通过观察该侧嵌条的有无，确认是否正确地进行了上述连接。
另外，由于上倾斜面1s的表面张力，导电膏40a、40b具有沿电路衬底30朝向半导体装置1外部方向流动的倾向，故即使与现有例相比，在电路衬底30上形成大量的导电膏，也可以最大限度地抑制相邻的导电端子21间的空间被导电膏40b埋入。即，可最大限度地抑制导电端子21间短路。
由于可提高半导体装置1连接在电路衬底30上时的机械强度，且最大限度地避免导电端子21间的短路，故可省略现有例所见的半导体装置的用户进行的底层填料91的形成工序。
结果是可不使工序复杂而提高半导体装置安装时的强度及精度。
换句话说，在图7所示的半导体装置1中，在除半导体芯片10A的端部外的背面也可以覆盖该背面或配线层19形成未图示的保护层。在这种情况下，可进一步提高半导体装置的可靠性。
另外，在上述的本实施例中，在半导体装置10A的背面形成有导电端子21，但本发明不限于此。即，本发明只要是形成贯通半导体芯片的埋入电极18及与其连接而延伸到倾斜面1s的配线层19的半导体装置，则也可以应用于未形成有导电端子21的半导体装置。此时，例如如图8所示，在半导体装置1L的半导体芯片10A的端部，覆盖埋入电极18上及倾斜面1s，在不存在导电端子的配线层19上形成含有和图7所示的相同的侧嵌条的导电膏40a、40b。

Claims (12)

1.一种半导体装置，其载置于电路衬底上，其特征在于，包括：半导体芯片；焊盘电极，其形成于所述半导体芯片的表面上；倾斜面，其从所述半导体芯片的背面端部向该半导体芯片的侧面倾斜；通孔，其从所述半导体芯片的背面贯通到所述焊盘电极的表面；绝缘膜，其形成于所述通孔的侧壁和除所述通孔外的所述半导体芯片的背面上；埋入电极，其经由所述绝缘膜形成于所述通孔中，且和所述焊盘电极电连接；配线层，其经由所述绝缘膜形成在含所述通孔在内的所述半导体芯片的背面上，与所述埋入电极连接，且在所述半导体芯片的所述倾斜面上延伸，所述半导体装置使该电路衬底和所述半导体芯片的背面相对而载置于所述电路衬底上。
2.如权利要求1所述的半导体装置，其特征在于，所述埋入电极和所述配线层由同一层形成。
3.如权利要求1或2所述的半导体装置，其特征在于，具有形成于所述配线层上的导电端子。
4.如权利要求1或2所述的半导体装置，其特征在于，在所述半导体芯片背面的端部形成有将所述埋入电极上及所述倾斜面上的所述配线层覆盖的导电性嵌条。
5.如权利要求3所述的半导体装置，其特征在于，在所述半导体芯片背面的端部形成覆盖所述导电端子及所述倾斜面上的所述配线层的导电性嵌条。
6.如权利要求1或2所述的半导体装置，其特征在于，在所述半导体芯片的表面上形成有支承体。
7.一种半导体装置的制造方法，其特征在于，包括：准备由切割线区分，且在表面上形成有焊盘电极的半导体衬底，在所述半导体衬底的背面，沿所述切割线形成向所述半导体衬底的表面方向变尖的槽的工序；形成从所述半导体衬底的背面到达所述半导体衬底的所述焊盘电极侧表面的通孔的工序；在所述槽内和所述通孔的侧壁以及除所述通孔外的所述半导体衬底的背面上形成绝缘膜的工序；形成经由所述绝缘膜设置在所述通孔中并与所述焊盘电极电连接的埋入电极的工序；形成经由所述绝缘膜配置在含所述通孔在内的所述半导体芯片的背面上、与所述埋入电极连接且延伸到所述切割线附近的配线层的工序；通过沿所述切割线进行切割将所述半导体衬底分割成多个半导体芯片的工序。
8.如权利要求7所述的半导体装置的制造方法，其特征在于，所述埋入电极和所述配线层由同一层形成。
9.如权利要求7或8所述的半导体装置的制造方法，其特征在于，具有在所述配线层上形成导电端子的工序。
10.如权利要求7或8所述的半导体装置的制造方法，其特征在于，具有在所述半导体芯片的背面端部形成将所述埋入电极上及所述倾斜面上的所述配线层覆盖的导电性嵌条的工序。
11.如权利要求9所述的半导体装置的制造方法，其特征在于，具有在所述半导体芯片的背面端部形成覆盖所述导电端子及所述倾斜面上的所述配线层的导电性嵌条的工序。
12.如权利要求7或8所述的半导体装置的制造方法，其特征在于，具有在准备由切割线区分且形成有焊盘电极的半导体衬底后，在所述半导体芯片的表面上形成支承体的工序。
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