CN100394614C - 半导体装置及其形成方法 - Google Patents
半导体装置及其形成方法 Download PDFInfo
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- CN100394614C CN100394614C CNB2004100961965A CN200410096196A CN100394614C CN 100394614 C CN100394614 C CN 100394614C CN B2004100961965 A CNB2004100961965 A CN B2004100961965A CN 200410096196 A CN200410096196 A CN 200410096196A CN 100394614 C CN100394614 C CN 100394614C
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Abstract
本发明揭示一种半导体装置及其形成方法,该半导体装置具有一基底,其表层具有<100>的结晶方向。借由硅化的源/漏极区、张力层、浅沟槽隔离结构、层间介电质等,施加用以增进NMOS场效晶体管效能的张应力。本发明有效的改善了晶体管的效能。
Description
技术领域
本发明是关于半导体装置,特别是关于一种互补式场效晶体管(complementary field-effect transistors)及其制造方法。
背景技术
金属氧化物半导体场效晶体管(metal-oxide-semiconductorfield-effect transistors;MOSFET)的尺寸缩减,包含栅极长度与栅氧化物的尺寸缩减,促使在过去数十年间集成电路每单位元件的速度、效能、密度及成本的改善。为了更加强化晶体管的效能,可使其沟道区发生应变而改善载流子(carrier)的迁移率(mobility)。一般而言,较好为沿NMOS(N型金属氧化物半导体)晶体管的源极-漏极的方向在其N型沟道区施加张应力、与沿PMOS(P型金属氧化物半导体)晶体管的源极-漏极的方向在其P型沟道区施加压应力。以下,兹列出相关于使晶体管沟道区发生应变的几项现有技术。
J.Welser等人在一九九二年十二月于旧金山所举行的“International Electron Devices Meeting”,其出版品中第1000~1002页,所发表名为“NMOS and PMOS TransistorsFabricated in Strained Silicon/Relaxed Silicon-GermaniumStructures”的文献中,揭露在沟道区下方提供一松弛的(relaxed)硅锗(silicon germanium)缓冲层。上述松弛的硅锗层的晶格常数大于松弛的硅,而使形成于其上的晶格呈现在水平方向拉长的状态,亦即使其受到双轴向的(biaxial)拉伸应变。因此,形成于外延(epitaxial)应变硅层的晶体管,其沟道区是处于双轴向拉伸应变的状态。在此方法中,上述松弛的硅锗缓冲层可视为应力源(stressor)而在沟道区造成应变。在此文献中,应力源是设于晶体管沟道区的下方。
由于须要成长微米尺度的松弛硅锗缓冲层,上述方法的成本相当昂贵,再加上述松弛的硅锗缓冲层内存在为数众多的错位(dislocation),且其中部分错位会延伸至上述应变硅层中,而导致基底具有很高的缺陷密度。因此,上述方法在应用上受到成本及基底材料性质的限制。
在另一方法中,是在晶体管形成之后才使其沟道区发生应变。在此方法中,是于已完成的晶体管结构(形成于硅基底中)上形成一高应力薄膜。上述高应力薄膜或应力源是改善沟道区中硅晶格的间隔,而对上述沟道区造成显著的影响,而使上述沟道区发生应变。在此方法中,应力源是置于已完成的晶体管结构上。此方法是由A.Shimizu等人,发表于“the Digest of Technical Papersof the 2001 International Electron Device Meeting”的出版品第433~436页,其标题为“Local mechanical stress control(LMC):a new technique for CMOS performance enhancement”。
由上述高应力薄膜所造成应变,据信在本质上为平行于源极-漏极方向的单轴向(uniaxial)应变。然而,单轴向的拉伸应变会降低空穴迁移率,而单轴向的压应变会降低电子的迁移率。可使用锗离子植入而选择性地造成应变松弛,而避免空穴或电子的迁移率的降低,但是因为N型沟道的晶体管与P型沟道的晶体管相当靠近而使其难以达成。因此,需要一有效且省钱的方法来引发应变,从而改善晶体管的效能。
发明内容
本发明是提供一种半导体装置,包含:一基底;一晶体管形成于上述基底上,上述晶体管具有一栅极与一源/漏极,上述晶体管并使流经上述源/漏极的电流大体上沿着上述基底<100>的晶格方向流动;一介电质形成于上述栅极的侧面及邻接上述栅极的上述基底的上方;以及一硅化物层形成于上述基底的表面上,并位于上述介电质的下方。
本发明所述的半导体装置,该介电质包含一介电线层(liner)与形成于该介电线层上的一间隔物。
本发明所述的半导体装置,该间隔物的宽度与该介电线层的厚度的比值小于5。
本发明所述的半导体装置,该间隔物的宽度与该栅极的长度的比值为0.8~1.5。
本发明所述的半导体装置,该介电质包含多个该介电线层。
本发明所述的半导体装置,该介电线层的厚度小于
本发明所述的半导体装置,该半导体装置是受到一张力层的被覆。
本发明所述的半导体装置,该介电质包含一间隔物,且该张力层的厚度与该间隔物的宽度的比值为0.5~1.6。
本发明所述的半导体装置,该张力层所施加的张应力为50MPa~2GPa。
本发明所述的半导体装置,该基底包含一具有刻痕(notch)的晶圆,而使得该基底<100>的晶格方向、与该刻痕和该晶圆中心所连成的线段之间的夹角小于7°。
本发明所述的半导体装置,该基底包含一浅沟槽隔离结构将应力传递至该基底。
本发明所述的半导体装置,该基底为绝缘层上覆半导体的基底,具有形成于第一硅层上的一绝缘层、与形成于该绝缘层上的第二硅层,其中该第一硅层<110>的晶格方向是沿着该第二硅层<100>的晶格方向,而该栅极硅形成于该第二硅层上。
本发明所述的半导体装置,该基底包含第一硅层、位于该第一硅层上的松弛Si1-xGex层、与位于该松弛Si1-xGex层上的应变硅层。
本发明所述的半导体装置,该半导体装置包含一PMOS晶体管与一NMOS晶体管,且该PMOS晶体管的栅极宽度与该NMOS晶体管的栅极宽度的比值等于该第一硅层中的电子迁移率与空穴迁移率的比值。
本发明所述的半导体装置,该半导体装置包含一PMOS晶体管与一NMOS晶体管,且该PMOS晶体管的栅极宽度与该NMOS晶体管的栅极宽度的比值等于该应变硅层中的电子迁移率与空穴迁移率的比值。
本发明所述的半导体装置,该半导体装置包含一PMOS晶体管与一NMOS晶体管,且该PMOS晶体管的栅极宽度与该NMOS晶体管的栅极宽度的比值等于该第一硅层中的电子迁移率与空穴迁移率的比值的平方根。
本发明所述的半导体装置,该半导体装置包含一PMOS晶体管与一NMOS晶体管,且该PMOS晶体管的栅极宽度与该NMOS晶体管的栅极宽度的比值等于该应变硅层中的电子迁移率与空穴迁移率的比值的平方根。
本发明所述的半导体装置,该x值大于0.1且小于0.5。
本发明所述的半导体装置,该半导体装置是被一层间介电质所覆盖,该层间介电质是沿着源极-漏极的方向施加0.1GPa~2GPa的张应力。
本发明所述的半导体装置,更包含第一区与第二区,该第一区包含多个微电子元件与多个金属层,该第二区包含多个金属层,且该第二区更包含一切割边缘与一间隙区,该间隙区为该基底上未被一顶盖金属层覆盖的区域。
本发明所述的半导体装置,该第二区中的该间隙区包含宽0.5~10μm的带状区域。
本发明所述的半导体装置,该第二区中的该间隙区包含该基底上未被内连线金属层覆盖的区域。
本发明所述的半导体装置,更包含七层或更多层的金属层形成于该基底上。
本发明所述的半导体装置,该第二区中的该间隙区包含宽0.5~10μm的带状区域,且该间隙区不包含主动区。
本发明所述的半导体装置,该第二区中的该间隙区包含一低介电常数介电层,其介电常数低于氧化硅的介电常数。
本发明是又提供一种半导体装置,包含:一基底,具有具第一晶格常数的第一半导体材料、与具第二晶格常数的第二半导体材料;以及至少一场效晶体管形成于上述第二半导体材料上,该场效晶体管具有一栅极与一源/漏极,该场效晶体管并使流经该源/漏极的电流大体上沿着该基底<100>的晶格方向流动。
本发明是又提供一种半导体装置,包含:一基底具有第一硅层、位于上述第一硅层上的松弛Si1-xGex层、与位于上述松弛Si1-xGex层上的应变硅层;以及至少一场效晶体管形成于上述应变硅层上,该场效晶体管具有一栅极与一源/漏极,该场效晶体管并使流经该源/漏极的电流大体上沿着该基底<100>的晶格方向流动。
本发明是又提供一种半导体装置,包含:一基底;第一晶体管形成于上述基底上,上述第一晶体管具有第一栅极与第一源/漏极区,上述第一晶体管的排列是使流经上述第一源/漏极的电流大体上沿着上述基底<100>的晶格方向流动;以及第二晶体管形成于上述基底上,上述第二晶体管具有第二栅极与第二源/漏极区,上述第二晶体管的排列是使流经上述第二源/漏极的电流大体上沿着上述基底<100>的晶格方向流动;其中上述第一栅极与上述第二栅极各具有沿其侧壁形成的间隔物(spacer),上述第一栅极的间隔物大于上述第二栅极的间隔物。
本发明是又提供一种半导体装置的形成方法,包含:提供一基底;形成一晶体管于上述基底上,上述晶体管具有一栅极与沿着上述栅极侧壁形成的间隔物;以及沿着上述基底的表面形成一硅化区,而使上述硅化区的至少一部分延伸至上述间隔物下;其中流经上述晶体管的一源/漏极的电流大体上沿着上述基底<100>的晶格方向流动。
本发明所述的半导体装置的形成方法,更包含形成一张力层于该晶体管上。
本发明所述的半导体装置的形成方法,形成该硅化区的步骤更包含:在该栅极、该基底与该间隔物之间形成一介电线层;在该间隔物下方的该介电线层蚀刻出一凹陷区;对该基底施以预洗(pre-clean);以及形成该硅化区。
本发明所述的半导体装置的形成方法,该预洗的步骤是采湿式,将该基底浸入一溶液中,该溶液为氢氟酸、硫酸、过氧化氢、氢氧化铵或上述的组合。
本发明所述的半导体装置的形成方法,形成于该间隔物下方的该硅化物小于该间隔物宽度的百分之七十。
本发明所述的半导体装置的形成方法,更包含形成七层或更多层的金属层于该基底上。
本发明是又提供一种半导体装置的形成方法,包含:提供一基底;形成第一晶体管于上述基底上,而使流经上述第一晶体管的一源/漏极的电流大体上沿着上述基底<100>的晶格方向流动,上述第一晶体管具有第一栅极与沿着上述第一栅极的侧壁形成的第一间隔物;以及形成第二晶体管于上述基底上,而使流经上述第二晶体管的一源/漏极的电流大体上沿着上述基底<100>的晶格方向流动,上述第二晶体管具有第二栅极与沿着上述第二栅极的侧壁形成的第二间隔物,上述第二间隔物小于上述第一间隔物。
本发明是又提供一种半导体装置,包含:提供一基底;一晶体管形成于上述基底上,上述晶体管具有一栅极与一源/漏极区,该晶体管并使流经该源/漏极的电流沿着该基底<100>的晶格方向流动;一低介电常数介电质形成于上述基底与上述栅极上;以及一硅化物层形成于上述介电质下的上述基底上;其中上述半导体装置包含第一区与第二区,上述第一区包含多个微电子元件与多个金属层、上述第二区包含多个金属层,且上述第二区更包含一切割边缘(die-saw edge)与一间隙(clearance)区,上述间隙区为上述基底上未被一顶盖金属层覆盖的区域。
附图说明
图1A~1E为一系列的剖面图,是显示本发明一较佳实施例的半导体装置的形成方法的步骤;
图2为示意图,是显示本发明一较佳实施例的半导体装置所使用的基底;
图3A~3D为一系列的俯视图与剖面图,是显示本发明另一实施例的半导体装置的晶片。
具体实施方式
为了让本发明的上述和其它目的、特征和优点能更明显易懂,下文特举一较佳实施例,并配合所附图式,作详细说明如下:
图1A~1E为一系列的剖面图,是显示本发明一较佳实施例的半导体装置的形成方法的步骤,其是于一半导体晶片中形成具应变沟道区的晶体管。此间绘示的本发明的步骤及半导体装置可应用于不同的电路中。例如本发明的实施例可应用于或非门(NORgate)、逻辑门(logic gate)、反向器(inverter)、互斥或门(ExclusiveOR gate;XOR gate)、与非门(NAND gate)、作为上拉晶体管(pull-up transistor)的PMOS晶体管、与作为下拉晶体管(pull-down transistor)的NMOS晶体管等的电路。
请参考图1A,是显示一晶圆100,其具有形成于一基底110上的第一晶体管102与第二晶体管104。在一较佳实施例中,基底110包含具<100>的晶格方向的硅基板(bulk silicon)。而基底110亦可以由绝缘层上覆半导体(semiconductor-on-insulator;SOI)基底的主动层来代替。在上述替代的实施例中,上述SOI的主动层包含硅,其是形成于一绝缘层上、且具<100>的晶格方向。上述绝缘层可以是例如埋入式的绝缘层(buried oxide;BOX)或氧化硅层。上述绝缘层可形成于硅基底或玻璃基底上,但较好是形成于具<110>的晶格方向的硅基底。
在另一实施例中,基底110是具有多层结构,其各层具有不同的晶格常数,其一例为具有应变硅表层的具成分渐变(graded)的硅锗(silicon-germanium;SiGe)基底。一般而言,一具成分渐变的硅锗层是形成于一硅基板上,且一松弛硅锗层是位于上述具成分渐变的硅锗层上。上述松弛Si1-xGex层,其x值较好为满足0.1<x<0.5,其晶格常数大于硅。具松弛晶格的硅是相对于具松弛晶格的硅锗,因不同的晶格常数而有晶格不匹配的情形。因此,以外延成长而形成于上述松弛硅锗层上的硅薄膜,将因为其被迫与上述松弛硅锗层的晶格对齐,而受到双轴向的拉伸应变。在本实施例中,上述应变硅层较好为具<100>的晶格方向。
另一具有多层结构的基底包含具第一晶格常数的第一层。而具第二晶格常数的第二层则形成于上述第一层上。上述第一层的材质可以是合金半导体、单一元素的半导体或化合物半导体等。例如,上述第一层可以是硅锗,且上述第二层可以是硅或含锗/碳的薄膜。在此具有多层结构的基底中,上述应变硅层的表面粗糙度小于1nm。
隔离区例如浅沟槽隔离结构112可形成于基底110中。浅沟槽隔离结构112是为现有,且可被其它隔离结构例如场氧化物(形成于硅的局部氧化)所取代。亦应注意的是浅沟槽隔离结构112会对晶圆100造成张应力。
以现有的方法在基底110上形成栅介电质114与栅极116并将其图形化。栅介电质114较好为高介电常数介电材料例如氧化硅、氮氧化硅、氮化硅、氧化物、含氮的氧化物或上述的组合等等。栅介电质114的相对介电常数较好为大于4。栅介电质114亦可以是氧化铝、氧化镧、氧化铪、氧化锆、氮氧化铪或上述的组合。
在一较佳实施例中,栅介电质114包含一氧化物层,可以任何氧化制程来形成,例如在氧化物、水、一氧化氮或上述的组合的环境中进行的湿式或干式热氧化法或是使用四乙基正硅酸盐(tetra-ethyl-ortho-silicate;TEOS)与氧为前驱物的CVD(chemical vapor deposition;化学气相沉积)技术。在一较佳实施例中,栅介电质114的厚度为较好为约厚。
栅极116较好为包含一导电材料例如金属(钽、钛、钼、钨、铂、铪、钌)、金属硅化物(硅化钛、硅化钴、硅化镍、硅化钽)、金属氮化物(氮化钛、氮化钽)、掺杂多晶硅、其它的导电材料或上述的组合。在一范例中,是沉积非晶硅并使其再结晶而形成多晶硅。在较佳实施例中,栅极116为多晶硅,而以LPCVD法(low-pressure chemical vapor deposition;低压化学气相沉积)沉积掺杂或未掺杂的多晶硅,其厚度为较佳为约
栅介电质114与栅极116的图形化较好是使用现有的光学微影(photolithography)技术。一般而言,光学微影包含沉积一光致抗蚀剂材料、使用光罩将其遮蔽、曝光、与显影。在图形化上述光致抗蚀剂层之后,施以一蚀刻的制程以移除栅介电质材料与栅极材料不需要的部分而形成图1A所示的栅介电质114与栅极116。在较佳的实施例中,上述的栅极材料为多晶硅,而上述的栅介电质为一氧化物,上述的蚀刻制程可采用干式或湿式、异向性或等向性的蚀刻制程,而较佳为异向性的干蚀刻制程。
在一实施例中,PMOS元件的栅极宽度异于NMOS元件栅极的宽度。在一实施例中,PMOS晶体管的栅极宽度与NMOS晶体管的栅极宽度的比值大体等于硅基板或应变硅层中的电子迁移率(mobility)与空穴迁移率的比值。在另一实施例中,PMOS晶体管的栅极宽度与NMOS晶体管的栅极宽度的比值大体等于硅基板或应变硅层中的电子迁移率与空穴迁移率的比值的平方根。
源/漏极118为以离子布植形成的淡掺杂漏极。可在源/漏极118植入N型掺杂物例如磷、氮、砷或锑等等,以形成NMOS元件;或可植入P型掺杂物例如硼、铝或铟等等以形成PMOS元件。NMOS元件亦可以选择性地与PMOS元件形成于相同的晶片上。在上述选择性的实施例中,如一般所知,需要使用不同的罩幕及离子布植的步骤,以仅在特定的区域植入N型及/或P型的离子。
上述晶体管或半导体装置的排列是使电流大体上沿着基底110的<100>的晶格方向流动,以改善空穴与电子的迁移率。因此,用以图形化源/漏极区118的罩幕是较好为使流经源/漏极区118的电流大体上沿着基底110的<100>的晶格方向流动。
请参考图1B,一介电线层120与一间隔物122是形成于栅极116的侧壁上,并对源/漏极区118施以第二次离子布植。氧化线层较好为一或多层的氧化物层,可以任何氧化制程来形成,例如在氧化物、水、一氧化氮或上述的组合的环境中进行的湿式或干式热氧化法或是使用TEOS与氧为前驱物的CVD技术。在一较佳实施例中,介电线层120的厚度为较好为约厚。
间隔物122是作为上述第二次离子布植实的间隔物之用,较好为包含氮化硅(Si3N4)或Si3N4以外的含氮层例如SixNy、氮氧化硅(SiOxNy)、肟化硅(silicon oxime;SiOxNy:Hz)或上述的组合。在一较佳实施例中,间隔物122包含以硅烷与氨作为前驱物气体的CVD制程所形成的Si3N4。
在一较佳实施例中,间隔物122的宽度与介电线层120的厚度的比值小于5,更好为小于3。另外,须注意间隔物122的宽度可能因元件型式而异。例如I/O元件可能需要较大的间隔物122,以获得操控该元件所需的电流。PMOS元件可能亦需要较大的间隔物122。具体而言,PMOS具较大的间隔物122时,可帮助减少作用于P型沟道区的张应力。在此例子中,较大的间隔物较好为比较小的间隔物大约10%。为了制造不同宽度的间隔物,可能需要加入额外的屏蔽、沉积、与蚀刻的步骤。
可使用等向性或异向性的蚀刻来图形化间隔物122。较佳的等向性蚀刻是使用磷酸溶液,并以介电线层120作为蚀刻停止层。因为上述Si3N4的厚度大于邻接的栅极116,上述等向性蚀刻是移除栅极116与未直接邻接栅极116的基底110上方的Si3N4材料,而留下如图1B所示的间隔物122。间隔物122的宽度较好为随晶体管102与104的栅极宽度的变动而改变。在一较佳实施例中,间隔物122的宽度与栅极116的长度的比例为0.8~1.5。
介电线层120的图形化可以使用例如以氢氟酸溶液作为蚀刻剂的等向性湿蚀刻制程。可使用的另一种蚀刻剂可以是浓硫酸与过氧化氢的混合物,其通常被称为“食人鱼溶液”(piranhasolution)。磷酸的水溶液亦可以用来图形化介电线层120。
如图1B所示,应注意的是较好为移除间隔物122下方的介电线层120。在一较佳实施例中,其凹入部分的程度为间隔物122宽度的10~70%,较好为间隔物122宽度的30%。
应注意的是形成上述凹入部分的蚀刻制程亦可能移除晶体管102与104上方的介电线层120与栅极116。如果需要的话,可将一罩幕置于晶体管102与104上,以避免在晶体管102与104上产生凹洞。
在形成间隔物122之后,可以现有技术在源/漏极区118施以第二次离子布植。可在源/漏极118植入N型掺杂物例如磷、氮、砷或锑等等,以形成NMOS元件;或可植入P型掺杂物例如硼、铝或铟等等以形成PMOS元件。NMOS元件亦可以选择性地与PMOS元件形成于相同的晶片上。在上述选择性的实施例中,如一般所知,需要使用不同的罩幕及离子布植的步骤,以仅在特定的区域植入N型及/或P型的离子。另外,可施以额外的离子布植而形成不同浓度梯度的接面(junction)结构。
请参考图1C,施以一硅化的制程而形成一硅化(物)区130。一般而言,上述硅化制程包含:沉积一金属层例如镍、钴、钯、铂、铜、钼、钛、钽、钨、铒、锆或上述的组合等等;以及使上述金属层与硅发生化学反应而形成硅化物。在一较佳实施例中,上述金属层是使用镍、钴、钯、铂或上述的组合等等,在其形成方面可使用现有的沉积技术例如蒸镀、溅镀或CVD等等。
在沉积上述金属层之前,较好为先清洁晶圆100以移除原生氧化物(native oxide)。用来清洁晶圆100的溶液可使用氢氟酸、硫酸、过氧化氢、氢氧化铵或上述的组合等等。
可借由退火的方式实施上述的硅化制程,以使上述金属层选择性地与曝露的硅区(例如源/漏极区118)与多晶硅区(例如栅极16)发生反应,而形成硅化物。在一较佳实施例中,上述金属层是使用镍、钴、钯或铂;经由上述硅化制程则分别形成硅化镍、硅化钴、硅化钯或硅化铂。上述金属层中为参与反应的金属,则可借由湿式的方式,进入硫酸、盐酸、过氧化氢、氢氧化铵或磷酸等溶液中,而将其移除。
应注意的是由于硅化物顶盖层厚度的延伸或是上述间隔物122下方的介电线层120因受到蚀刻而凹入的部分,硅化的部分是延伸至间隔物122下方。已发现以上述方式形成硅化物时,会增加作用在晶体管102与104中的沟道区的张应力。如之前所述,此张应力可强化晶体管特别是NMOS晶体管沟道区的电流。
在另一实施例中,蚀刻介电线层而形成凹入部分与实施硅化制程等一或数个步骤是仅实施于NMOS元件,借此可强化电子迁移率而不会去影响到PMOS元件的空穴迁移率。因此,在实施上述步骤时,可能需要先形成一罩幕层于PMOS元件上。
请参考图1D,沉积一张力层140,被覆于晶体管102与104上,以形成大体上沿着<100>方向作用的张应力。张力层140可以是氮化硅或是其它可形成张应力的材料,其形成方式例如为CVD法。上述CVD法可以是现有的LPCVD、RTCVD(rapidthermal CVD;快速热化学气相沉积)、ALCVD(atomic layerCVD;原子层化学气相沉积)或PECVD(plasma-enhanced CVD;等离子增益化学气相沉积)。张力层140所施加的张应力较好为50MPa~2.0GPa,并沿着源极-漏极的方向作用。张力层140的厚度与间隔物122的宽度的比值较好为0.5~1.6。在一实施例中,张力层140包含以LPCVD所形成的氮化硅,并施加1.2GPa的张应力;在另一实施例中,张力层140包含以PECVD所形成的氮化硅,并施加0.7GPa的张应力。
在另一实施例中,在NMOS元件具有一张力层时,PMOS元件可具有一压应力层,或不具任何施加应力的薄膜。上述压应力层可在源极-漏极的方向对P沟道元件的沟道区造成压应变,而强化空穴的迁移率。在PMOS元件上形成压应力层与在NMOS元件上形成张应力层是揭露于美国专利申请案号10/639,170中。
接下来请参考图1E,层间介电质(inter-layer dielectric;ILD)150,覆盖晶圆100。层间介电质150通常具有一平坦化的表面,可包含以沉积技术例如CVD所形成的氧化硅。层间介电质150的厚度较好为更好为另外,在一较佳实施例中,层间介电质150沿着<100>的方向施加0.1~2GPa的张应力。
接下来,可使用标准的制程技术来完成半导体装置的制造,其步骤可包含形成金属线与金属层、形成介层窗(via)与插塞(plug)、与封装等等。
图2是绘示一晶圆200,其可用以制造本发明的半导体装置。如上所述,流经晶体管102与104的源/漏极区118的电流方向较好为大体上沿着硅<100>的结晶方向。因此,较好为在晶圆上产生缺口或以标记方式使使用者知道<100>方向为何。在一较佳实施例中,一个5mm、三角形的缺口是置于晶圆200的边缘,上述缺口是大体上沿着<100>方向,其偏移的正负误差不超过7°。在另一实施例中,可使用矩形缺口、刮痕、平边或其它标记方式,方向亦可以改成垂直<100>方向或其它方向,其大小可视需求选用。
图3A~3D为一系列的俯视图与剖面图,是显示本发明另一实施例的半导体装置的晶片310,其是分离自具有<100>或<110>缺口方向的晶圆。在施行晶圆或半导体晶片310的分离制程时,用于形成半导体装置的晶圆200的缺口方向为<100>时,较缺口方向为<110>时为脆。另外,低介电常数介电质的存在会使金属间介电层332(绘示于图3B)的性质大幅恶化、及/或半导体晶片310的分离制程时的晶片崩裂(chipping)缺陷的数量大幅恶化。上述低介电常数介电质例如含氟或含碳的介电层,常用于金属间介电层332中,其特征在于介电常数与机械强度均较传统的氧化硅介电层为低。另外,无论晶圆缺口的方向是<100>或<110>,最容易发生晶片崩裂的区域是在大体上平行于切割边缘(die-saw edge)328的长度方向、由半导体晶片310的俯视图来看距离四个晶片角落334(300~500μm)的邻近的带状区域。
因此,所制造的半导体晶片310较好为具有位于其外围或边缘的间隙(clearance)区314-a、314-b(绘示于图3A)与314-c、314-d(绘示于图3B)。在图3A~3D中,是以边线322将半导体晶片310划分为两个相邻的区域,使熟悉此技艺者能够了解本实施例。第一区312包含大多数形成于半导体晶片310中的微电子元件例如晶体管、电阻器、电容器等等;而可为任意形状的焊垫316与多个金属层(不包括用于半导体晶片310的封装或连接(bonding)制程所使用的重布(redistribution)金属层)是作为内连线318,用于元件内或连接元件与外界的信号/电源线。单一金属层318可更包含多个堆栈导电层例如钛、氮化钛、钽及/或氮化钽。第二区326包含多个金属层或其它用于监控制造过程、且可与外界连接或不与外界连接的微电子装置324。此时,一部分第二区326的区域可与半导体晶片310的切割边缘328共享基底的空间。绘示于图3A的第二区326更包含一切割边缘328与间隙区314-a、314-b。在第二区326内的间隙区314-a、314-b为带状区域,并沿着边线322设置在第一区312的周围。绘示于图3B的第二区326更包含一金属,其含有密封环(seal ring)320,在半导体晶片310的封装及其后续制程时,可防止游离的离子或水气由水平方向侵入形成于第一区312的微电子元件。一相似的实施例中,可形成如图3B所示的间隙区314-c、314-d,其是位于第二区326内的带状区域,大体上沿着围着第一区312的边线322与密封环320之间的空间设置。在另一实施例中,上述间隙区可以是第一区312内的带状区域,并沿着边线322设置在第一区312的周围。间隙区314-a、314-b、314-c、314-d不包含连续的元件主动区或连续的金属层336/338,可大幅减少金属间介电质332,并/或大幅减少在半导体晶片310的分离制程及/或封装制程时发生晶片崩裂的数量。
在元件具有3~9层或更多的金属层时,已发现顶盖金属336是承受了大部分由热/机组合效应(thermal/mechanicalcombinational effect)所造成的应力,造成上述热/机组合效应的材料包含:基底110、保护(protecting/passivation)层330、金属间介电层332、顶盖金属层336、内连线金属层338、封装所使用的有机/无机填充物、及保护层330上的封装胶体。对使用金属层层数较少例如3~6个金属层的半导体制程而言,间隙区314-a、314-b、314-c、314-d较好为宽度0.5~10μm的带状区域,且不为顶盖金属层336或任何内连线金属层338所覆盖。如此一来,间隙区314-a、314-b、314-c、314-d除了在半导体晶片310的分离制程中改善由机械应力所造成的基板/介电质崩裂的问题之外;亦可以作为热/机械应力的缓冲区,以在半导体晶片310的封装或后续制程中改善因介电质崩裂或脱层所造成的潜在性的可靠度问题。对使用金属层层数较多例如6~9个金属层的半导体制程而言,间隙区314-a、314-b、314-c、314-d较好为宽度1~20μm的带状区域,其不会占用太多半导体晶片310的面积,而可以妥善对付因较厚的金属/介电质堆栈层所导致的较大的热/机械应力。
图3C与图3D是绘示间隙区314-a、314-b、314-c、314-d的剖面图,是显示可用于本实施例的结构的范例。具体而言,图3C是绘示间隙区314-a、314-b、314-c、314-d被介电质所覆盖、且其中不包含任何金属层与主动区的情形。图3D则绘示另一实施例,其中间隙区314-a、314-b、314-c、314-d不包含任何主动区,而各个金属层在间隙区314-a、314-b、314-c、314-d内呈现分离的状态。为了减少封装时所发生的缺陷而达到理想的可靠度,间隙区314-a、314-b、314-c、314-d的宽度为0.5~20μm且较好为一材料所填充,上述材料例如为低介电常数介电质、氧化硅、含碳的介电质、含氮的介电质或含氟的介电质等等。
以上所述仅为本发明较佳实施例,然其并非用以限定本发明的范围,任何熟悉本项技术的人员,在不脱离本发明的精神和范围内,可在此基础上做进一步的改进和变化,因此本发明的保护范围当以本申请的权利要求书所界定的范围为准。
附图中符号的简单说明如下:
100~晶圆
102~第一晶体管
104~第二晶体管
110~基底
112~浅沟槽隔离(isolation)结构
114~栅介电质
116~栅极
118~源/漏极
120~介电线层
122~间隔物
130~硅化(物)区
140~张力层
150~层间介电质
200~晶圆
310~半导体晶片
312~第一区
314-a~d~间隙区
316~焊垫
318~内连线
320~密封环
322~边线
324~微电子装置
326~第二区
328~切割边缘
330~保护层
332~金属间介电层
334~晶片角落
336~金属层
338~金属层
Claims (36)
1.一种半导体装置,其特征在于所述半导体装置包含:
一基底;
一晶体管形成于该基底上,该晶体管具有一栅极与一源/漏极,该晶体管并使流经该源/漏极的电流沿着该基底<100>的晶格方向流动;
一介电质形成于该栅极的侧面及邻接该栅极的该基底的上方;以及
一硅化物层形成于该基底的表面上,并位于该介电质的下方。
2.根据权利要求1所述的半导体装置,其特征在于:该介电质包含一介电线层与形成于该介电线层上的一间隔物。
3.根据权利要求2所述的半导体装置,其特征在于:该间隔物的宽度与该介电线层的厚度的比值小于5。
4.根据权利要求2所述的半导体装置,其特征在于:该间隔物的宽度与该栅极的长度的比值为0.8~1.5。
5.根据权利要求2所述的半导体装置,其特征在于:该介电质包含多个该介电线层。
7.根据权利要求1所述的半导体装置,其特征在于:该半导体装置是受到一张力层的被覆。
8.根据权利要求7所述的半导体装置,其特征在于:该介电质包含一间隔物,且该张力层的厚度与该间隔物的宽度的比值为0.5~1.6。
9.根据权利要求7所述的半导体装置,其特征在于:该张力层所施加的张应力为50MPa~2GPa。
10.根据权利要求7所述的半导体装置,其特征在于:该基底包含一具有刻痕的晶圆,而使得该基底<100>的晶格方向、与该刻痕和该晶圆中心所连成的线段之间的夹角小于7°。
11.根据权利要求1所述的半导体装置,其特征在于:该基底包含一浅沟槽隔离结构将应力传递至该基底。
12.根据权利要求1所述的半导体装置,其特征在于:该基底为绝缘层上覆半导体的基底,具有形成于第一硅层上的一绝缘层、与形成于该绝缘层上的第二硅层,其中该第一硅层<110>的晶格方向是沿着该第二硅层<100>的晶格方向,而该栅极硅形成于该第二硅层上。
13.根据权利要求1所述的半导体装置,其特征在于:该基底包含第一硅层、位于该第一硅层上的松弛Si1-xGex层、与位于该松弛Si1-xGex层上的应变硅层。
14.根据权利要求13所述的半导体装置,其特征在于:该半导体装置包含一PMOS晶体管与一NMOS晶体管,且该PMOS晶体管的栅极宽度与该NMOS晶体管的栅极宽度的比值等于该第一硅层中的电子迁移率与空穴迁移率的比值。
15.根据权利要求13所述的半导体装置,其特征在于:该半导体装置包含一PMOS晶体管与一NMOS晶体管,且该PMOS晶体管的栅极宽度与该NMOS晶体管的栅极宽度的比值等于该应变硅层中的电子迁移率与空穴迁移率的比值。
16.根据权利要求13所述的半导体装置,其特征在于:该半导体装置包含一PMOS晶体管与一NMOS晶体管,且该PMOS晶体管的栅极宽度与该NMOS晶体管的栅极宽度的比值等于该第一硅层中的电子迁移率与空穴迁移率的比值的平方根。
17.根据权利要求13所述的半导体装置,其特征在于:该半导体装置包含一PMOS晶体管与一NMOS晶体管,且该PMOS晶体管的栅极宽度与该NMOS晶体管的栅极宽度的比值等于该应变硅层中的电子迁移率与空穴迁移率的比值的平方根。
18.根据权利要求13所述的半导体装置,其特征在于:该x值大于0.1且小于0.5。
19.根据权利要求1所述的半导体装置,其特征在于:该半导体装置是被一层间介电质所覆盖,该层间介电质是沿着源极-漏极的方向施加0.1GPa~2GPa的张应力。
20.根据权利要求1所述的半导体装置,其特征在于:更包含第一区与第二区,该第一区包含多个微电子元件与多个金属层,该第二区包含多个金属层,且该第二区更包含一切割边缘与一间隙区,该间隙区为该基底上未被一顶盖金属层覆盖的区域。
21.根据权利要求20所述的半导体装置,其特征在于:该第二区中的该间隙区包含宽0.5~10μm的带状区域。
22.根据权利要求20所述的半导体装置,其特征在于:该第二区中的该间隙区包含该基底上未被内连线金属层覆盖的区域。
23.根据权利要求20所述的半导体装置,其特征在于:更包含七层或更多层的金属层形成于该基底上。
24.根据权利要求20所述的半导体装置,其特征在于:该第二区中的该间隙区包含宽0.5~10μm的带状区域,且该间隙区不包含主动区。
25.根据权利要求20所述的半导体装置,其特征在于:该第二区中的该间隙区包含一低介电常数介电层,其介电常数低于氧化硅的介电常数。
26.一种半导体装置,其特征在于所述半导体装置包含:
一基底,具有具第一晶格常数的第一半导体材料、与具第二晶格常数的第二半导体材料;以及
至少一场效晶体管形成于该第二半导体材料上,该场效晶体管具有一栅极与一源/漏极,该场效晶体管并使流经该源/漏极的电流沿着该基底<100>的晶格方向流动。
27.一种半导体装置,其特征在于所述半导体装置包含:
一基底具有第一硅层、位于该第一硅层上的松弛Si1-xGex层、与位于该松弛Si1-xGex层上的应变硅层;以及
至少一场效晶体管形成于该应变硅层上,该场效晶体管具有一栅极与一源/漏极,该场效晶体管并使流经该源/漏极的电流沿着该基底<100>的晶格方向流动。
28.一种半导体装置,其特征在于所述半导体装置包含:
一基底;
第一晶体管形成于该基底上,该第一晶体管具有第一栅极与第一源/漏极区,该第一晶体管的排列是使流经该第一源/漏极的电流沿着该基底<100>的晶格方向流动;以及
第二晶体管形成于该基底上,该第二晶体管具有第二栅极与第二源/漏极区,该第二晶体管的排列是使流经该第二源/漏极的电流沿着该基底<100>的晶格方向流动;
其中该第一栅极与该第二栅极各具有沿其侧壁形成的间隔物,该第一栅极的间隔物大于该第二栅极的间隔物。
29.一种半导体装置的形成方法,其特征在于所述半导体装置的形成方法包含:
提供一基底;
形成一晶体管于该基底上,该晶体管具有一栅极与沿着该栅极侧壁形成的间隔物;以及
沿着该基底的表面形成一硅化区,而使该硅化区的至少一部分延伸至该间隔物下;
其中流经该晶体管的一源/漏极的电流沿着该基底<100>的晶格方向流动。
30.根据权利要求29所述的半导体装置的形成方法,其特征在于:更包含形成一张力层于该晶体管上。
31.根据权利要求29所述的半导体装置的形成方法,其特征在于形成该硅化区的步骤更包含:
在该栅极、该基底与该间隔物之间形成一介电线层;
在该间隔物下方的该介电线层蚀刻出一凹陷区;
对该基底施以预洗;以及
形成该硅化区。
32.根据权利要求31所述的半导体装置的形成方法,其特征在于:该预洗的步骤是采湿式,将该基底浸入一溶液中,该溶液为氢氟酸、硫酸、过氧化氢、氢氧化铵或上述的组合。
33.根据权利要求29所述的半导体装置的形成方法,其特征在于:形成于该间隔物下方的该硅化物小于该间隔物宽度的百分之七十。
34.根据权利要求29所述的半导体装置的形成方法,其特征在于:更包含形成七层或更多层的金属层于该基底上。
35.一种半导体装置的形成方法,其特征在于所述半导体装置的形成方法包含:
提供一基底;
形成第一晶体管于该基底上,而使流经该第一晶体管的一源/漏极的电流沿着该基底<100>的晶格方向流动,该第一晶体管具有第一栅极与沿着该第一栅极的侧壁形成的第一间隔物;以及
形成第二晶体管于该基底上,而使流经该第二晶体管的一源/漏极的电流沿着该基底<100>的晶格方向流动,该第二晶体管具有第二栅极与沿着该第二栅极的侧壁形成的第二间隔物,该第二间隔物小于该第一间隔物。
36.一种半导体装置,其特征在于所述半导体装置包含:
提供一基底;
一晶体管形成于该基底上,该晶体管具有一栅极与一源/漏极区,该晶体管并使流经该源/漏极的电流沿着该基底<100>的晶格方向流动;
一低介电常数介电质形成于该基底与该栅极上;以及
一硅化物层形成于该介电质下的该基底上;
其中该半导体装置包含第一区与第二区,该第一区包含多个微电子元件与多个金属层、该第二区包含多个金属层,且该第二区更包含一切割边缘与一间隙区,该间隙区为该基底上未被一顶盖金属层覆盖的区域。
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CN2793924Y (zh) | 2006-07-05 |
TW200529424A (en) | 2005-09-01 |
US20050116360A1 (en) | 2005-06-02 |
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SG112066A1 (en) | 2005-06-29 |
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