CN100380632C - 制造半导体器件的方法 - Google Patents

制造半导体器件的方法 Download PDF

Info

Publication number
CN100380632C
CN100380632C CNB2005100057481A CN200510005748A CN100380632C CN 100380632 C CN100380632 C CN 100380632C CN B2005100057481 A CNB2005100057481 A CN B2005100057481A CN 200510005748 A CN200510005748 A CN 200510005748A CN 100380632 C CN100380632 C CN 100380632C
Authority
CN
China
Prior art keywords
semiconductor device
transistorized
pmos
wiring
nmos
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
CNB2005100057481A
Other languages
English (en)
Chinese (zh)
Other versions
CN1719597A (zh
Inventor
高桥浩司
中川进一
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Semiconductor Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Publication of CN1719597A publication Critical patent/CN1719597A/zh
Application granted granted Critical
Publication of CN100380632C publication Critical patent/CN100380632C/zh
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Images

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
    • H10B41/10—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the top-view layout
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/04—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS
    • G11C16/0466—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS comprising cells with charge storage in an insulating layer, e.g. metal-nitride-oxide-silicon [MNOS], silicon-oxide-nitride-oxide-silicon [SONOS]
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
    • H10B41/40—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the peripheral circuit region
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
    • H10B41/40—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the peripheral circuit region
    • H10B41/42—Simultaneous manufacture of periphery and memory cells
    • H10B41/43—Simultaneous manufacture of periphery and memory cells comprising only one type of peripheral transistor
    • H10B41/44—Simultaneous manufacture of periphery and memory cells comprising only one type of peripheral transistor with a control gate layer also being used as part of the peripheral transistor
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
    • H10B41/40—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the peripheral circuit region
    • H10B41/42—Simultaneous manufacture of periphery and memory cells
    • H10B41/49—Simultaneous manufacture of periphery and memory cells comprising different types of peripheral transistor
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D89/00—Aspects of integrated devices not covered by groups H10D84/00 - H10D88/00
    • H10D89/10—Integrated device layouts
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D89/00—Aspects of integrated devices not covered by groups H10D84/00 - H10D88/00
    • H10D89/60—Integrated devices comprising arrangements for electrical or thermal protection, e.g. protection circuits against electrostatic discharge [ESD]
    • H10D89/601—Integrated devices comprising arrangements for electrical or thermal protection, e.g. protection circuits against electrostatic discharge [ESD] for devices having insulated gate electrodes, e.g. for IGFETs or IGBTs
    • H10D89/811—Integrated devices comprising arrangements for electrical or thermal protection, e.g. protection circuits against electrostatic discharge [ESD] for devices having insulated gate electrodes, e.g. for IGFETs or IGBTs using FETs as protective elements

Landscapes

  • Engineering & Computer Science (AREA)
  • Manufacturing & Machinery (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Semiconductor Memories (AREA)
  • Non-Volatile Memory (AREA)
  • Semiconductor Integrated Circuits (AREA)
CNB2005100057481A 2004-07-06 2005-01-25 制造半导体器件的方法 Expired - Fee Related CN100380632C (zh)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP2004198888A JP2006024598A (ja) 2004-07-06 2004-07-06 半導体装置の製造方法
JP2004198888 2004-07-06

Publications (2)

Publication Number Publication Date
CN1719597A CN1719597A (zh) 2006-01-11
CN100380632C true CN100380632C (zh) 2008-04-09

Family

ID=35058439

Family Applications (1)

Application Number Title Priority Date Filing Date
CNB2005100057481A Expired - Fee Related CN100380632C (zh) 2004-07-06 2005-01-25 制造半导体器件的方法

Country Status (6)

Country Link
US (2) US7541236B2 (enExample)
EP (1) EP1615266A3 (enExample)
JP (1) JP2006024598A (enExample)
KR (1) KR100691701B1 (enExample)
CN (1) CN100380632C (enExample)
TW (1) TWI282113B (enExample)

Families Citing this family (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP1818989A3 (en) * 2006-02-10 2010-12-01 Semiconductor Energy Laboratory Co., Ltd. Nonvolatile semiconductor storage device and manufacturing method thereof
EP1837917A1 (en) * 2006-03-21 2007-09-26 Semiconductor Energy Laboratory Co., Ltd. Nonvolatile semiconductor memory device
TWI416738B (zh) * 2006-03-21 2013-11-21 Semiconductor Energy Lab 非揮發性半導體記憶體裝置
US8022460B2 (en) * 2006-03-31 2011-09-20 Semiconductor Energy Laboratory Co., Ltd. Nonvolatile semiconductor memory device
US7554854B2 (en) * 2006-03-31 2009-06-30 Semiconductor Energy Laboratory Co., Ltd. Method for deleting data from NAND type nonvolatile memory
JP4975398B2 (ja) * 2006-08-30 2012-07-11 ルネサスエレクトロニクス株式会社 半導体装置及びその製造方法
US7813158B2 (en) * 2007-05-14 2010-10-12 Hong Kong Applied Science And Technology Research Institute Co., Ltd. Recordable electrical memory
JP2010272649A (ja) * 2009-05-20 2010-12-02 Panasonic Corp 半導体装置及びその製造方法
US20140030860A1 (en) * 2012-07-24 2014-01-30 Eon Silicon Solution, Inc. Manufacturing method of tunnel oxide of nor flash memory

Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4646425A (en) * 1984-12-10 1987-03-03 Solid State Scientific, Inc. Method for making a self-aligned CMOS EPROM wherein the EPROM floating gate and CMOS gates are made from one polysilicon layer
US5251171A (en) * 1990-01-19 1993-10-05 Sharp Kabushiki Kaisha Method of operating a semiconductor memory device
JPH0870056A (ja) * 1994-08-31 1996-03-12 Toshiba Corp 半導体記憶装置
JPH10320983A (ja) * 1997-05-15 1998-12-04 Toshiba Corp 不揮発性半導体記憶装置
JP2000150666A (ja) * 1998-11-05 2000-05-30 Nec Corp 半導体装置及びその製造方法
JP2002043446A (ja) * 2000-05-19 2002-02-08 Matsushita Electric Ind Co Ltd 不揮発性半導体記憶装置

Family Cites Families (14)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CA2004436C (en) 1989-12-01 1999-06-29 Alain Comeau Test chip for use in semiconductor fault analysis
JP2976693B2 (ja) 1992-05-08 1999-11-10 日本電気株式会社 Ｃｍｏｓ型半導体集積回路
US5292681A (en) * 1993-09-16 1994-03-08 Micron Semiconductor, Inc. Method of processing a semiconductor wafer to form an array of nonvolatile memory devices employing floating gate transistors and peripheral area having CMOS transistors
JP2982862B2 (ja) 1996-07-17 1999-11-29 日本電気株式会社 半導体装置
JP2924832B2 (ja) * 1996-11-28 1999-07-26 日本電気株式会社 半導体装置の製造方法
JP3221369B2 (ja) * 1997-09-19 2001-10-22 日本電気株式会社 不揮発性半導体記憶装置及びその製造方法
JP3528575B2 (ja) * 1998-02-17 2004-05-17 セイコーエプソン株式会社 不揮発性半導体記憶装置及びその製造方法
JP4398541B2 (ja) 1999-06-30 2010-01-13 東芝メモリシステムズ株式会社 不揮発性半導体メモリ
JP2002064190A (ja) * 2000-08-18 2002-02-28 Mitsubishi Electric Corp 半導体装置
JP2002246562A (ja) * 2001-02-15 2002-08-30 Toshiba Corp 半導体記憶装置
KR100641667B1 (ko) * 2001-10-31 2006-11-08 인터내셔널 비지네스 머신즈 코포레이션 반도체 장치 및 그 제조 방법
JP5179692B2 (ja) 2002-08-30 2013-04-10 富士通セミコンダクター株式会社 半導体記憶装置及びその製造方法
JP4338495B2 (ja) * 2002-10-30 2009-10-07 富士通マイクロエレクトロニクス株式会社 シリコンオキシカーバイド、半導体装置、および半導体装置の製造方法
JP2004193282A (ja) * 2002-12-10 2004-07-08 Renesas Technology Corp 不揮発性半導体記憶装置

Patent Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4646425A (en) * 1984-12-10 1987-03-03 Solid State Scientific, Inc. Method for making a self-aligned CMOS EPROM wherein the EPROM floating gate and CMOS gates are made from one polysilicon layer
US5251171A (en) * 1990-01-19 1993-10-05 Sharp Kabushiki Kaisha Method of operating a semiconductor memory device
JPH0870056A (ja) * 1994-08-31 1996-03-12 Toshiba Corp 半導体記憶装置
JPH10320983A (ja) * 1997-05-15 1998-12-04 Toshiba Corp 不揮発性半導体記憶装置
JP2000150666A (ja) * 1998-11-05 2000-05-30 Nec Corp 半導体装置及びその製造方法
JP2002043446A (ja) * 2000-05-19 2002-02-08 Matsushita Electric Ind Co Ltd 不揮発性半導体記憶装置

Also Published As

Publication number Publication date
EP1615266A3 (en) 2014-01-29
TW200603209A (en) 2006-01-16
KR20060003815A (ko) 2006-01-11
TWI282113B (en) 2007-06-01
CN1719597A (zh) 2006-01-11
KR100691701B1 (ko) 2007-03-09
JP2006024598A (ja) 2006-01-26
US20080220573A1 (en) 2008-09-11
US20060008995A1 (en) 2006-01-12
US7541236B2 (en) 2009-06-02
EP1615266A2 (en) 2006-01-11
US7910431B2 (en) 2011-03-22

Similar Documents

Publication Publication Date Title
JP6066958B2 (ja) 不揮発性メモリ構造
US8158478B2 (en) Strained semiconductor device and method of making same
US8093650B2 (en) Scalable electrically eraseable and programmable memory (EEPROM) cell array
US8455923B2 (en) Embedded NOR flash memory process with NAND cell and true logic compatible low voltage device
US7910431B2 (en) Method for manufacturing semiconductor device
US9406687B1 (en) Integration of memory devices with different voltages
US9406764B2 (en) Simple and cost-free MTP structure
US20040053467A1 (en) Single-poly eprom and method for forming the same
US9171727B2 (en) Method of manufacturing a semiconductor device
US8134201B2 (en) Semiconductor memory device provided with stacked layer gate including charge accumulation layer and control gate, and manufacturing method thereof
US6617632B2 (en) Semiconductor device and a method of manufacturing the same
JP3452522B2 (ja) 埋込み型ｎｖｒａｍアレイを有する集積回路チップの製造方法
US10090311B1 (en) Cost-free MTP memory structure with reduced terminal voltages
US8664706B2 (en) Current in one-time-programmable memory cells
US10347773B2 (en) Split gate non-volatile memory (NVM) with improved programming efficiency
JP2002299475A (ja) 半導体装置及びその製造方法
US9299569B2 (en) Manufacturing method of semiconductor device
KR20150119819A (ko) 단순하고 무료인 mtp 구조

Legal Events

Date Code Title Description
C06 Publication
PB01 Publication
C10 Entry into substantive examination
SE01 Entry into force of request for substantive examination
C14 Grant of patent or utility model
GR01 Patent grant
ASS Succession or assignment of patent right

Owner name: FUJITSU MICROELECTRONICS CO., LTD.

Free format text: FORMER OWNER: FUJITSU LIMITED

Effective date: 20081107

C41 Transfer of patent application or patent right or utility model
TR01 Transfer of patent right

Effective date of registration: 20081107

Address after: Tokyo, Japan

Patentee after: FUJITSU MICROELECTRONICS Ltd.

Address before: Kawasaki, Kanagawa, Japan

Patentee before: Fujitsu Ltd.

C56 Change in the name or address of the patentee

Owner name: FUJITSU SEMICONDUCTOR CO., LTD.

Free format text: FORMER NAME: FUJITSU MICROELECTRON CO., LTD.

CP01 Change in the name or title of a patent holder

Address after: Japan's Kanagawa Prefecture Yokohama

Patentee after: FUJITSU MICROELECTRONICS Ltd.

Address before: Japan's Kanagawa Prefecture Yokohama

Patentee before: Fujitsu Microelectronics Ltd.

CP02 Change in the address of a patent holder

Address after: Japan's Kanagawa Prefecture Yokohama

Patentee after: Fujitsu Microelectronics Ltd.

Address before: Tokyo, Japan

Patentee before: Fujitsu Microelectronics Ltd.

CF01 Termination of patent right due to non-payment of annual fee

Granted publication date: 20080409

Termination date: 20180125

CF01 Termination of patent right due to non-payment of annual fee