CN100336187C - 半导体器件的导线形成方法 - Google Patents

半导体器件的导线形成方法 Download PDF

Info

Publication number
CN100336187C
CN100336187C CNB2004100619450A CN200410061945A CN100336187C CN 100336187 C CN100336187 C CN 100336187C CN B2004100619450 A CNB2004100619450 A CN B2004100619450A CN 200410061945 A CN200410061945 A CN 200410061945A CN 100336187 C CN100336187 C CN 100336187C
Authority
CN
China
Prior art keywords
film
cobalt
thermal treatment
rapid thermal
semiconductor
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Active
Application number
CNB2004100619450A
Other languages
English (en)
Other versions
CN1638064A (zh
Inventor
陈成坤
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Covenson wisdom N.B.868 company
Original Assignee
Hynix Semiconductor Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Family has litigation
First worldwide family litigation filed litigation Critical https://patents.darts-ip.com/?family=34698453&utm_source=google_patent&utm_medium=platform_link&utm_campaign=public_patent_search&patent=CN100336187(C) "Global patent litigation dataset” by Darts-ip is licensed under a Creative Commons Attribution 4.0 International License.
Application filed by Hynix Semiconductor Inc filed Critical Hynix Semiconductor Inc
Publication of CN1638064A publication Critical patent/CN1638064A/zh
Application granted granted Critical
Publication of CN100336187C publication Critical patent/CN100336187C/zh
Active legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Images

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/74—Making of localized buried regions, e.g. buried collector layers, internal connections substrate contacts
    • H01L21/743—Making of internal connections, substrate contacts
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • H01L21/283—Deposition of conductive or insulating materials for electrodes conducting electric current
    • H01L21/285—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation
    • H01L21/28506—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers
    • H01L21/28512—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers on semiconductor bodies comprising elements of Group IV of the Periodic Table
    • H01L21/28518—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers on semiconductor bodies comprising elements of Group IV of the Periodic Table the conductive layers comprising silicides

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Semiconductor Memories (AREA)
  • Electrodes Of Semiconductors (AREA)

Abstract

本发明公开了一种形成半导体器件导线的方法。在通过接触孔暴露的掺杂结区上形成钴硅化物层，该钴硅化物层可使接触电阻稳定，因此，掺杂结区的接触电阻在后续热处理工序中不发生变化。

Description

半导体器件的导线形成方法
技术领域
本发明涉及一种半导体器件的导线形成方法，更具体地说，涉及一种形成改善接触电阻特性的半导体器件的导线的改进方法。
背景技术
作为半导体器件的数据I/O路径的位线结构包括由多晶硅层或钨硅化物层组成的多晶金属硅化物结构(polycide structure)。对于高集成度和高速半导体器件而言，由于多晶金属硅化物结构具有高薄层电阻而受到限制，常用具有低电阻的钨位线代替。
因为钨位线的接触电阻随后续的热处理而变，所以需要使电阻稳定。
一般而言，在后续的热处理过程中，在形成厚Ti膜的P+区中由于在源极/漏极区中的掺杂损失使接触电阻显著增加。因此，采用较薄的Ti膜构成位线。
然而，尽管薄Ti膜可使P+区的接触电阻稳定，但N+区和栅电极的钨硅化物层的接触电阻却大大增加。
因此，需调整Ti膜的厚度，使P+区、N+区和栅极区的接触电阻具有适中的值。
然而，如图1所示，当接触面积较小时，接触电阻尤其是栅电极的接触电阻将急剧增加，因而，必须增加Ti膜的厚度以降低接触电阻。但如上所述，增加Ti膜的厚度又将增加P+区的接触电阻，结果导致器件的性能降低。
发明内容
据此，本发明要解决的技术问题是提供一种半导体器件的导线形成方法，其中，在源极/漏极区的表面上形成钴硅化物层，以稳定接触性能并提高器件的可靠性。
为了解决所述问题，本发明提供一种半导体器件的导线形成方法，该方法包括：在包括栅电极和掺杂结区的半导体基底上形成较低绝缘膜；蚀刻所述较低绝缘膜，以形成暴露栅电极上表面的第一接触孔和暴露掺杂结区的第二接触孔；在通过第二接触孔暴露的掺杂结区上形成钴硅化物层；在包括所述第一和第二接触孔的所述半导体基底上形成由Ti膜和TiN膜组成的叠层结构；在包括所述第一和第二接触孔的较低绝缘膜上形成导电层；及对导电层构图，以形成导线图形。
附图说明
下面参照附图对本发明进行描述，通过描述将能更深刻地理解本发明，所示附图仅为示例性说明，而并非是对本发明的限制。附图中：
图1为接触电阻随接触区变化而变的曲线；
图2A至2D为横截面图，它们示出了本发明的半导体器件的导线形成方法。
具体实施方式
下文将参照附图对本发明一优选实施方式的半导体器件导线形成方法进行详细描述。
图2A至2D为横截面图，它们示出了本发明的半导体器件的导线形成方法。
参见图2A，在半导体基底11上形成一层用于限定有源区的器件绝缘膜(图中未示出)。
接着，在半导体基底11上形成栅极氧化膜15、用于栅电极的多晶硅膜17、钨硅化物层19和硬掩模膜(hard mask film)21组成的叠层结构。再对该叠层结构进行蚀刻，以形成栅电极。
然后，用该栅电极作为注入掩模，在半导体基底11中离子注入n型或P型杂质，以形成掺杂结区13。
此后，在半导体基底11上形成绝缘膜(未示出)，并各向异性地进行蚀刻，以便在栅电极的侧壁处形成绝缘膜隔离部分23。
接着，在半导体基底11上形成使整个表面平面化(Planarizing)的较低绝缘膜25。对较低绝缘膜25和硬掩模膜21有选择地进行蚀刻，以形成暴露钨硅化物层19的第一接触孔27和暴露掺杂结区13的第二接触孔29。
可以除去第一接触孔27和第二接触孔29底部自然形成的氧化物膜。
随后，在包括第一和第二接触孔27和29的半导体基底11上形成钴膜31。优选用PVD工艺形成钴膜31，使其厚度范围为50至150。也可用钴膜和氮化钛膜组成的叠层结构代替钴膜31。
参见图2B，使钴膜31经受快速热处理工序，以使钴膜31与掺杂结区13的表面发生反应，从而形成钴硅化物层33。
优选所述快速热处理工序包括温度范围为650至750℃、进行时间为10至30秒的第一快速热处理工序；和温度范围为800至880℃、进行时间为10至30秒的第二快速热处理工序。也可以省去第一快速热处理工序。
参见图2C，除去钴膜31的未反应部分。优选用SC-1溶液，即NH4OH、H2O2和H2O的混合物溶液进行所述去除工序。
再参见图2D，在包括第一和第二接触孔27和29的半导体基底11上形成由Ti膜和TiN膜组成的叠层结构35。优选Ti膜厚度范围为100至200并通过第一PVD工序形成，而TiN膜厚度范围为100至400并通过第二PVD工序形成。
然后，在包括第一和第二接触孔27和29的较低绝缘膜25上形成导电层37。优选导电层37包括钨。
接着，对导电层37构图，以形成如位线图形或金属导线之类的导线图形。
如前所述，根据本发明，在源极/漏极区表面上形成钴硅化物层，以使接触性能稳定并提高器件的可靠性。
在不超出本发明的构思和主要特征的前提下，本发明可以有多种实施方式，因此应当理解，上面详细描述的实施方式并非是对本发明的限制，除非另有说明，应在所附的权利要求书限定的构思和保护范围内作宽广的解释，因此，落入权利要求书所界定的范围内的所有改变、改型或等同替换都将被所附的权利要求书涵盖。

Claims (7)

1.一种半导体器件的导线形成方法，包括以下步骤：
在包括一栅电极和一掺杂结区的一半导体基底上形成一较低绝缘膜；
蚀刻所述较低绝缘膜，以形成暴露所述栅电极的上表面的一第一接触孔和暴露所述掺杂结区的一第二接触孔；
在通过所述第二接触孔暴露的所述掺杂结区上形成一钴硅化物层；
在包括所述第一和第二接触孔的所述半导体基底上形成由一Ti膜和一TiN膜组成的一叠层结构；
在包括所述第一和第二接触孔的所述较低绝缘膜上形成一导电层；及
对所述导电层构图，以形成导线图形。
2.如权利要求1所述的方法，其中，所述形成钴硅化物层的步骤包括：
在包括所述第一和所述第二接触孔的所述半导体基底上形成一钴膜；
进行快速热处理工序，以使所述钴膜与所述掺杂结区的一表面发生反应；及
除去所述钴膜的未发生反应的部分。
3.如权利要求2所述的方法，其中，所述钴膜由PVD方法形成，其厚度范围从50至150。
4.如权利要求2所述的方法，其中，所述快速热处理工序包括：
在温度范围为650至750℃、时间为10至30秒的条件下，进行一第一快速热处理工序；
在温度范围为800至880℃、时间为10至30秒的条件下，进行一第二快速热处理工序。
5.如权利要求2所述的方法，其中，用NH4OH、H2O2和H2O的混合物溶液进行所述除去所述钴膜的未发生反应的部分的步骤。
6.如权利要求1所述的方法，其中，所述形成由一Ti膜和一TiN膜组成的叠层结构的步骤包括：
经第一PVD工序形成厚度范围为100至200的所述Ti膜；和
经第二PVD工序形成厚度范围为100至400的所述TiN膜。
7.如权利要求1所述的方法，其中，所述导线图形是位线图形或金属导线。
CNB2004100619450A 2003-12-24 2004-06-29 半导体器件的导线形成方法 Active CN100336187C (zh)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
KR0096378/2003 2003-12-24
KR1020030096378A KR100576464B1 (ko) 2003-12-24 2003-12-24 반도체소자의 도전배선 형성방법
KR0096378/03 2003-12-24

Publications (2)

Publication Number Publication Date
CN1638064A CN1638064A (zh) 2005-07-13
CN100336187C true CN100336187C (zh) 2007-09-05

Family

ID=34698453

Family Applications (1)

Application Number Title Priority Date Filing Date
CNB2004100619450A Active CN100336187C (zh) 2003-12-24 2004-06-29 半导体器件的导线形成方法

Country Status (4)

Country Link
US (1) US7101791B2 (zh)
KR (1) KR100576464B1 (zh)
CN (1) CN100336187C (zh)
TW (1) TWI302726B (zh)

Families Citing this family (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100639219B1 (ko) * 2005-05-27 2006-10-30 주식회사 하이닉스반도체 반도체 소자의 캐패시터 형성방법
CN100449711C (zh) * 2006-04-03 2009-01-07 中芯国际集成电路制造(上海)有限公司 硅化金属阻止区的形成方法及半导体器件的制造方法
KR100750194B1 (ko) 2006-07-06 2007-08-17 삼성전자주식회사 오믹콘택막의 형성 방법 및 이를 이용한 반도체 장치의금속배선 형성 방법
US20150372100A1 (en) * 2014-06-19 2015-12-24 GlobalFoundries, Inc. Integrated circuits having improved contacts and methods for fabricating same
TWI620234B (zh) * 2014-07-08 2018-04-01 聯華電子股份有限公司 一種製作半導體元件的方法
KR20180066746A (ko) * 2016-12-09 2018-06-19 삼성전자주식회사 반도체 소자 및 그 제조 방법
DE102020122120A1 (de) 2020-02-18 2021-08-19 Taiwan Semiconductor Manufacturing Co., Ltd. Metall-gate-strukturen und verfahren zum herstellen derselben in feldeffekttransistoren
US11476351B2 (en) 2020-02-18 2022-10-18 Taiwan Semiconductor Manufacturing Co., Ltd. Metal gate structures and methods of fabricating the same in field-effect transistors
KR20230011802A (ko) 2021-07-14 2023-01-25 에스케이하이닉스 주식회사 반도체소자의 도전배선 형성방법

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6083817A (en) * 1999-06-02 2000-07-04 Advanced Micro Devices, Inc. Cobalt silicidation using tungsten nitride capping layer
US6153485A (en) * 1998-11-09 2000-11-28 Chartered Semiconductor Manufacturing Ltd. Salicide formation on narrow poly lines by pulling back of spacer
US6200840B1 (en) * 1999-06-25 2001-03-13 United Microelectronics Corp. Method for producing PMOS devices
CN1377063A (zh) * 2001-03-23 2002-10-30 矽统科技股份有限公司 半导体元件的自行对准金属硅化物层形成方法

Family Cites Families (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH11283935A (ja) * 1998-03-30 1999-10-15 Nec Corp 半導体装置の製造方法
US5998873A (en) 1998-12-16 1999-12-07 National Semiconductor Corporation Low contact resistance and low junction leakage metal interconnect contact structure
KR20010028503A (ko) 1999-09-21 2001-04-06 김종수 자동 아날로그/디지털 변환회로
KR20010048188A (ko) 1999-11-25 2001-06-15 윤종용 텅스텐 플러그 형성방법
KR100483027B1 (ko) 2001-12-26 2005-04-15 주식회사 하이닉스반도체 반도체소자의 실리사이드층 형성 방법
US6815235B1 (en) * 2002-11-25 2004-11-09 Advanced Micro Devices, Inc. Methods of controlling formation of metal silicide regions, and system for performing same

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6153485A (en) * 1998-11-09 2000-11-28 Chartered Semiconductor Manufacturing Ltd. Salicide formation on narrow poly lines by pulling back of spacer
US6083817A (en) * 1999-06-02 2000-07-04 Advanced Micro Devices, Inc. Cobalt silicidation using tungsten nitride capping layer
US6200840B1 (en) * 1999-06-25 2001-03-13 United Microelectronics Corp. Method for producing PMOS devices
CN1377063A (zh) * 2001-03-23 2002-10-30 矽统科技股份有限公司 半导体元件的自行对准金属硅化物层形成方法

Also Published As

Publication number Publication date
TWI302726B (en) 2008-11-01
US7101791B2 (en) 2006-09-05
US20050142767A1 (en) 2005-06-30
KR20050064787A (ko) 2005-06-29
KR100576464B1 (ko) 2006-05-08
TW200522263A (en) 2005-07-01
CN1638064A (zh) 2005-07-13

Similar Documents

Publication Publication Date Title
KR100522125B1 (ko) 폴리실리콘 게이트 상부의 개선된 샐리사이드 저항을 위한장치 및 방법
US6013569A (en) One step salicide process without bridging
US5641985A (en) Antifuse element and semiconductor device having antifuse elements
US20030038305A1 (en) Method for manufacturing and structure of transistor with low-k spacer
CN1062979C (zh) 制造cmos器件栅电极的方法
GB2150349A (en) Process of fabricating semiconductor integrated circuit device
US5565702A (en) Antifuse element, semiconductor device having antifuse elements, and method for manufacturing the same
CN100336187C (zh) 半导体器件的导线形成方法
US4923823A (en) Method of fabricating a self aligned semiconductor device
CN1815729A (zh) 电熔丝的结构
US20060223296A1 (en) Semiconductor device having self-aligned silicide layer and method thereof
CN101032028A (zh) 可靠接点
KR100486229B1 (ko) 수소열처리를이용한티타늄실리사이드트랜지스터의전기적특성개선방법
DE102013209685A1 (de) Source- und Drainarchitektur in einem aktiven Gebiet eines P-Kanaltransistors durch schräge Implantation
KR19980067517A (ko) 반도체장치의 게이트패턴 및 그 제조방법
KR20000013433A (ko) 선택적 금속 실리사이드막 형성방법
CN1472796A (zh) 形成屏蔽式只读存储器中的金属硅化物的方法
KR100236059B1 (ko) 실리사이드막 형성방법 및 그를 이용한 반도체소자의 제조방법
CN1787188A (zh) 金属硅化层的制造方法
CN1610077A (zh) 可避免短路的自行对准金属硅化物制程的处理方法
JPH0621088A (ja) 半導体装置の製造方法
KR100318273B1 (ko) 반도체 소자의 비트라인 형성방법
KR950000657B1 (ko) 반도체장치 및 제조방법
KR100596792B1 (ko) 반도체소자의 제조방법
KR100400279B1 (ko) 텅스텐 실리사이드를 갖는 반도체 소자 제조방법

Legal Events

Date Code Title Description
C06 Publication
PB01 Publication
C10 Entry into substantive examination
SE01 Entry into force of request for substantive examination
C14 Grant of patent or utility model
GR01 Patent grant
ASS Succession or assignment of patent right

Owner name: 658868 NEW BRUNSWICK, INC.

Free format text: FORMER OWNER: HAIRYOKSA SEMICONDUCTOR CO., LTD.

Effective date: 20120611

C41 Transfer of patent application or patent right or utility model
TR01 Transfer of patent right

Effective date of registration: 20120611

Address after: new brunswick

Patentee after: Hynix Semiconductor Inc.

Address before: Gyeonggi Do, South Korea

Patentee before: Hairyoksa Semiconductor Co., Ltd.

C56 Change in the name or address of the patentee

Owner name: CONVERSANT INTELLECTUAL PROPERTY N.B.868 INC.

Free format text: FORMER NAME: 658868 NEW BRUNSWICK, INC.

CP01 Change in the name or title of a patent holder

Address after: new brunswick

Patentee after: Covenson wisdom N.B.868 company

Address before: new brunswick

Patentee before: Hynix Semiconductor Inc.