CN101032028A - 可靠接点 - Google Patents

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CN101032028A
CN101032028A CNA200480043680XA CN200480043680A CN101032028A CN 101032028 A CN101032028 A CN 101032028A CN A200480043680X A CNA200480043680X A CN A200480043680XA CN 200480043680 A CN200480043680 A CN 200480043680A CN 101032028 A CN101032028 A CN 101032028A
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nickel
substrate
layer
coalescent
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池东植
李家耀
李德宝
刘晓丽
姚海标
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Abstract

一种镍基锗化物接点包括处理材料，该处理材料在形成接点的处理过程中以及在锗化工艺之后的过程中抑制镍基锗化物的聚结。该处理材料是以镍层上的覆盖层形式存在或者结合在用于形成镍基接点的镍层内。聚结减少提高了接点的电特性。

Description

可靠接点
本发明总体涉及用于集成电路(IC)中锗化物接点的形成。更具体地说，本发明涉及用于集成电路中镍基锗化物接点的改进形成。
背景技术
图1表示常规CMOS IC的一部分100。该部分包括形成在硅基板101上的第一和第二互补晶体管120和140。第一晶体管是形成在深p掺杂井121上的n-MOS晶体管，同时第二晶体管是形成在深n掺杂井141上的p-MOS晶体管。浅p掺杂井122在n-MOS晶体管的下方，同时浅n掺杂井位于p-MOS晶体管142下方。浅沟槽隔离件160被用于隔离晶体管。每个晶体管包括源电极(123或143)、漏电极(124或144)以及栅电极(125或145)。对于n-MOS晶体管来说，源电极、漏电极和栅电极掺杂诸如磷的n型掺杂剂。对于p-MOS晶体管来说，源电极、漏电极和栅电极掺杂诸如硼的p型掺杂剂。
为了减小例如晶体管的源电极、漏电极和栅电极中的接点电阻，采用硅化钛或硅化钴。硅化钛和硅化钴因其良好的电特性和相对较高的热稳定性而被用作接点170。采用自对准硅化物工艺形成金属硅化物接点。作为自对准工艺的一部分，可以采用在栅电极侧面的介电侧壁间隔件(128和148)。例如在Sze的“ULSI Technology”-McGraw-Hill(1996年)中描述了硅化物工艺，为了所有目的而将该文献结合在此作为参考。
对于高速应用来说，采用诸如锗或锗硅的锗基基板。锗基基板因其有助于大驱动电流的高载流移动特性而有利于高速应用。为了形成用于锗基基板中的源电极、漏电极和栅电极的接点，采用金属锗化物工艺。
广泛用于形成硅化物接点的钛和钴金属与锗化物工艺不相容。这是因为形成具有良好电特性(例如低电阻)的钛或钴接点需要相对较高的退火温度，这对于基于锗的应用是不利的。例如，高温导致锗蒸发或者在使用有意应变材料时高温使该材料中的应力不合乎要求地松弛。
从以上描述中可知，需要提供一种用于IC的改进的锗化物接点。
发明内容
本发明总体涉及例如集成电路的制造。在一种实施方式中，设置基板。该基板包括含有锗的活性区域。在该活性区域上形成镍基接点。该镍基接点包括在处理过程中抑制镍聚结的处理材料。这样产生镍基接点的改进电特性。
在一种实施方式中，在基板上沉积镍层，从而覆盖活性区域。在镍层上形成包含处理材料的覆盖层。在另一实施方式中，镍层包含处理材料，从而形成镍合金层。随后通过退火处理基板以形成镍基接点。覆盖层或接点层的处理材料在退火过程中抑制镍聚结以形成镍基接点。
附图说明
图1表示常规CMOS IC的一部分；以及
图2-6表示用于形成根据本发明一种实施方式的镍基接点的工艺。
具体实施方式
图2-6表示用于形成根据本发明一种实施方式的镍基接点的工艺。参照图2，示出了基板201的一部分的横截面。该基板用于形成集成电路组件。在一种实施方式中，该基板包括多层基板，在该多层基板中至少顶层或表面层包含锗。例如，多层基板包括绝缘体上的锗(germanium-on-insulator)基板。该绝缘体上的锗基板可以包含具有顶层205的硅衬底基板203，所述顶层205包括通过绝缘体层204例如二氧化硅分隔的锗。基板的顶层包括例如单晶材料、多晶或非晶材料，或它们的组合。可以拉紧或松弛锗层。还可以在硅锗衬底层上设置包含锗的表面。
在另一实施方式中，至少基板的顶层或表面层包含硅锗。优选地，硅锗层包含Si1-xGex，其中x小于50原子百分比。可以拉紧或松弛硅锗层。基板还可以包括在硅锗上具有不同锗百分比的硅锗。还可以设置包含锗，包括硅锗的单层基板。在另一实施方式中，基板上顶层表面的至少一部分包括锗，其包含硅锗。
备选地，还可以在锗层的顶部设置薄硅应变层。该硅层应该足够薄以保持拉伸应力。通常，薄硅应变层的厚度小于100纳米。
参照图3，基板的一部分制备有用于晶体管的掺杂井。如图所示，这些井制备用于CMOS应用。还可以采用其他类型的应用。在一种实施方式中，分别设置用于p-MOS和n-MOS晶体管的活性区域308和309。p-MOS晶体管的活性区域包括深p井321和浅n井322。n-MOS晶体管的活性区域包括深n井341和浅p井342。浅沟槽隔离件(STI)360分隔这些活性区域。
如图4所示，通过在活性区域308和309中形成p-MOS和n-MOS晶体管420和440而继续所述工艺。晶体管各自包括第一和第二扩散区域(423-424或443-444)和栅极(425或445)。p-MOS晶体管的扩散区域包括p型掺杂剂，同时n-MOS晶体管的扩散区域包括n型掺杂剂。晶体管的栅极包括锗。通常，栅极包含多晶锗。还可以采用其他类型的材料，例如硅或硅锗。优选地，栅极掺杂有掺杂剂。在一种实施方式中，晶体管的栅极掺杂有p型掺杂剂。还可以利用其他掺杂剂掺杂栅极。还可以利用不同类型的掺杂剂掺杂p-MOS和n-MOS晶体管的栅极。栅极的下方为栅极氧化层。栅极氧化层包括例如热生长的二氧化硅。还可以采用其他类型的栅极氧化材料。在一种实施方式中，在p-MOS和n-MOS栅极的侧面设置绝缘侧壁间隔件428和448。
参照图5，通过沉积用于在扩散区域和栅极上形成镍基锗化物接点的材料而继续所述工艺。在一种实施方式中，在基板上沉积镍层571。可以采用多种技术形成镍层，例如喷镀，包括磁控管喷镀。例如在大约5×10-7托(Torr)、大约室温下喷镀镍层。还可以采用用于形成镍层的其他技术或参数。镍层的厚度大约是5纳米-100纳米。优选地，镍层的厚度小于大约50纳米。还可以采用其他厚度。
在镍层上形成覆盖层572。在一种实施方式中，覆盖层包含抑制锗化镍层聚结的材料。在一种实施方式中，覆盖层的材料在镍基接点中不可溶。在一种实施方式中，覆盖层包含钼、钽、钛、钨、锆或它们的组合。还可以采用能够在处理温度下抑制锗化镍聚结的其他材料。在另一实施方式中，覆盖层包含可溶于镍基接点中的材料，例如钯和/或铂。还可以采用可溶和不可溶于镍基接点中的材料的组合形成覆盖层。
可以采用多种技术形成覆盖层，例如喷镀，包括磁控管喷镀。在一种实施方式中，在室温下完成喷镀。还可以采用用于形成覆盖层的其他技术或参数，例如热和电子束蒸镀。
覆盖层的厚度应该足以在高于大约500℃的温度下抑制层中的聚结。优选地，覆盖层的厚度应该足以在至少高达700℃的温度下抑制层中的聚结。在一些实施方式中，覆盖层的厚度应该足以在大约500℃-700℃的温度下抑制层中的聚结。例如，覆盖层的厚度小于或等于大约50纳米。优选地，覆盖层的厚度大约是5纳米。
在形成接点层之后，对基板进行退火以形成接点。退火导致接点层和基板的材料发生反应，从而在包含锗的基板区域中形成镍基锗或镍基硅化锗接点。对于用于接点层的锗的底层来说，形成镍基单锗化物接点同时形成用于硅锗底层的镍基硅化锗接点。在一种实施方式中，退火包括快速热退火(RTP)。还可以采用其他类型的退火。在大约200℃到至少大约700℃的温度下执行RTP大约1-100秒。优选地，在大约280℃到至少大约500℃的温度下执行RTP。RTP的环境例如为氮。还可以采用其他类型的环境，例如真空、氦、氩。还可以采用其他类型的惰性气体。
参照图6，接点层的图案被构造成留出接点层的部分以该区域形成接点。在一种实施方式中，在STI和侧壁间隔件上方区域690和691中去除接点层材料，从而在扩散区域和栅极的表面上留下接点层。例如通过常规掩模和蚀刻技术构造接点层的图案。例如，光致抗蚀层被沉积并且图案被构造成暴露所述层待去除的部分，接着通过蚀刻工艺去除未受光致抗蚀层保护的层。在另一实施方式中，在用于形成接点的退火工艺之前构造接点层的图案。
在备选实施方式中，包含镍基合金的接点层沉积在制备有晶体管的基板上，例如在图4中所述。镍基合金包括NiY，其中Y包括从抑制接点层聚结的材料中选定的材料。在一种实施方式中，Y包括不可溶于镍基接点中的材料。在一种实施方式中，Y包括钼、钽、钛、钼、钨、锆或者他们的组合。还可以采用不可溶于镍基接点中的其他材料。在另一实施方式中，Y包括可溶于镍基接点中的材料，例如钯和/或铂。还可以提供包括在镍基接点中可溶和不可溶材料的组合的Y。镍基合金层的厚度例如为大约5纳米-100纳米。优选地，镍基合金层的厚度小于50纳米。
在一种实施方式中，Y的百分比应该足以在高于大约500℃的温度下抑制层中的聚结。优选地，Y的百分比应该足以在至少高达700℃下抑制层中的聚结。更优选地，Y的百分比应该足以在大约500℃-700℃的温度下抑制层中的聚结。Y的百分比例如是大约0.1-50原子百分比。优选地，Y的百分比小于大约20原子百分比。
在形成镍基合金层之后，继续所述工艺以通过对接点层进行退火而形成接点。退火工艺例如包括在前所述的RTP。接点在包括镍和锗的区域形成接点。在不存在锗的区域(例如STI上方)，不发生任何反应。选择性采用例如用于镍层已反应部分的湿蚀刻技术选择性去除镍层的未反应部分。因此，形成自对准锗化镍或锗硅化镍接点。
尽管已经参照多种实施方式特别示出并描述了本发明，但本领域技术人员将会认识到，在不脱离本发明的精神和范围的前提下可以对本发明作出修改和变形。因此应该不参照以上描述而参照附加权利要求及其等效内容的全部范围来确定本发明的范围。

Claims (16)

1.一种制造接点的方法，该方法包括：
设置包括至少一个活性区域的基板，所述活性区域包含锗；
在活性区域上沉积包含镍的接点层；
在接点层设置处理材料；以及
处理基板以形成镍基接点，所述处理包括对基板进行退火以产生反应，从而形成镍基接点，其中处理材料抑制在处理过程中接点层的聚结。
2.如权利要求1所述的方法，其特征在于，所述基板包括多层基板，在该基板中上表面层包含锗或硅锗。
3.如权利要求1所述的方法，其特征在于，所述基板包含锗或硅锗。
4.如权利要求1-3中任意一项所述的方法，其特征在于，所述处理材料不可溶于镍基接点中。
5.如权利要求4所述的方法，其特征在于，所述处理材料包括钽、钛、钼、钨、锆或它们的组合。
6.如权利要求1-5中任意一项所述的方法，其特征在于，所述设置处理材料包括在接点层上形成覆盖层。
7.如权利要求6所述的方法，其特征在于，覆盖层的厚度足以在高于或等于大约500℃的温度下抑制聚结。
8.如权利要求6所述的方法，其特征在于，覆盖层的厚度足以在至少高达大约700℃的温度下抑制聚结。
9.如权利要求6所述的方法，其特征在于，覆盖层的厚度小于或等于大约50纳米。
10.如权利要求1-5中任意一项所述的方法，其特征在于，所述设置处理材料包括将处理材料结合在沉积接点层的步骤中以形成包含镍和处理材料的镍基合金接点层。
11.如权利要求10所述的方法，其特征在于，所述镍基合金中的处理材料小于大约50原子百分比。
12.如权利要求10所述的方法，其特征在于，接点层中的处理材料的百分比足以在高于或等于大约500℃的温度下抑制处理过程中的聚结。
13.如权利要求10所述的方法，其特征在于，接点层中的处理材料的百分比足以在至少高达大约700℃的温度下抑制处理过程中的聚结。
14.如权利要求1-3中任意一项所述的方法，其特征在于，所述处理材料包括可溶于和不可溶于镍基接点中的材料的组合。
15.如权利要求1-3中任意一项所述的方法，其特征在于，所述处理材料包括铂和/或钯。
16.一种集成电路，包括：
具有至少一个活性区域的基板，所述活性区域包含镍；
与活性区域相连的接点，该接点包含镍；以及
与接点接触的处理材料，其中处理材料在形成接点的处理过程中抑制接点中镍的聚结。
CNA200480043680XA 2004-07-27 2004-07-27 可靠接点 Pending CN101032028A (zh)

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