CH707901B1 - SIC-Vorrichtung mit hoher Sperrspannung, abgeschlossen durch einen Abflachungskantenabschluss. - Google Patents

SIC-Vorrichtung mit hoher Sperrspannung, abgeschlossen durch einen Abflachungskantenabschluss. Download PDF

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Publication number
CH707901B1
CH707901B1 CH01183/14A CH11832014A CH707901B1 CH 707901 B1 CH707901 B1 CH 707901B1 CH 01183/14 A CH01183/14 A CH 01183/14A CH 11832014 A CH11832014 A CH 11832014A CH 707901 B1 CH707901 B1 CH 707901B1
Authority
CH
Switzerland
Prior art keywords
semiconductor device
edge termination
resistance
layer
sic semiconductor
Prior art date
Application number
CH01183/14A
Other languages
German (de)
English (en)
Inventor
Cheng Lin
Kumar Agarwal Anant
John O'loughlin Michael
Augustus Burk Albert Jr
Williams Palmour John
Original Assignee
Cree Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority claimed from US13/366,658 external-priority patent/US9349797B2/en
Application filed by Cree Inc filed Critical Cree Inc
Publication of CH707901B1 publication Critical patent/CH707901B1/de

Links

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/64—Double-diffused metal-oxide semiconductor [DMOS] FETs
    • H10D30/66—Vertical DMOS [VDMOS] FETs
    • H10D30/668—Vertical DMOS [VDMOS] FETs having trench gate electrodes, e.g. UMOS transistors
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D10/00—Bipolar junction transistors [BJT]
    • H10D10/40—Vertical BJTs
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D18/00—Thyristors
    • H10D18/60—Gate-turn-off devices 
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/64—Double-diffused metal-oxide semiconductor [DMOS] FETs
    • H10D30/66—Vertical DMOS [VDMOS] FETs
    • H10D30/665—Vertical DMOS [VDMOS] FETs having edge termination structures
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
    • H10D62/10—Shapes, relative sizes or dispositions of the regions of the semiconductor bodies; Shapes of the semiconductor bodies
    • H10D62/102—Constructional design considerations for preventing surface leakage or controlling electric field concentration
    • H10D62/103—Constructional design considerations for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse-biased devices
    • H10D62/104—Constructional design considerations for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse-biased devices having particular shapes of the bodies at or near reverse-biased junctions, e.g. having bevels or moats
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D8/00—Diodes
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
    • H10D62/10—Shapes, relative sizes or dispositions of the regions of the semiconductor bodies; Shapes of the semiconductor bodies
    • H10D62/17—Semiconductor regions connected to electrodes not carrying current to be rectified, amplified or switched, e.g. channel regions
    • H10D62/177—Base regions of bipolar transistors, e.g. BJTs or IGBTs
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
    • H10D62/10—Shapes, relative sizes or dispositions of the regions of the semiconductor bodies; Shapes of the semiconductor bodies
    • H10D62/17—Semiconductor regions connected to electrodes not carrying current to be rectified, amplified or switched, e.g. channel regions
    • H10D62/192—Base regions of thyristors
    • H10D62/199—Anode base regions of thyristors
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
    • H10D62/10—Shapes, relative sizes or dispositions of the regions of the semiconductor bodies; Shapes of the semiconductor bodies
    • H10D62/17—Semiconductor regions connected to electrodes not carrying current to be rectified, amplified or switched, e.g. channel regions
    • H10D62/393—Body regions of DMOS transistors or IGBTs 
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
    • H10D62/60—Impurity distributions or concentrations
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
    • H10D62/80—Semiconductor bodies, or regions thereof, of devices having potential barriers characterised by the materials
    • H10D62/83—Semiconductor bodies, or regions thereof, of devices having potential barriers characterised by the materials being Group IV materials, e.g. B-doped Si or undoped Ge
    • H10D62/832—Semiconductor bodies, or regions thereof, of devices having potential barriers characterised by the materials being Group IV materials, e.g. B-doped Si or undoped Ge being Group IV materials comprising two or more elements, e.g. SiGe
    • H10D62/8325—Silicon carbide

Landscapes

  • Thyristors (AREA)
  • Bipolar Transistors (AREA)
  • Electrodes Of Semiconductors (AREA)
CH01183/14A 2012-02-06 2013-02-05 SIC-Vorrichtung mit hoher Sperrspannung, abgeschlossen durch einen Abflachungskantenabschluss. CH707901B1 (de)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US13/366,658 US9349797B2 (en) 2011-05-16 2012-02-06 SiC devices with high blocking voltage terminated by a negative bevel
PCT/US2013/024740 WO2013119548A1 (en) 2012-02-06 2013-02-05 Sic devices with high blocking voltage terminated by a negative bevel

Publications (1)

Publication Number Publication Date
CH707901B1 true CH707901B1 (de) 2017-09-15

Family

ID=47780185

Family Applications (1)

Application Number Title Priority Date Filing Date
CH01183/14A CH707901B1 (de) 2012-02-06 2013-02-05 SIC-Vorrichtung mit hoher Sperrspannung, abgeschlossen durch einen Abflachungskantenabschluss.

Country Status (4)

Country Link
JP (1) JP6335795B2 (enExample)
CH (1) CH707901B1 (enExample)
DE (1) DE112013000866B4 (enExample)
WO (1) WO2013119548A1 (enExample)

Families Citing this family (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US10103540B2 (en) 2014-04-24 2018-10-16 General Electric Company Method and system for transient voltage suppression devices with active control
US9806157B2 (en) 2014-10-03 2017-10-31 General Electric Company Structure and method for transient voltage suppression devices with a two-region base
WO2017033233A1 (ja) * 2015-08-21 2017-03-02 株式会社日立製作所 半導体基板、半導体基板の研削方法および半導体装置の製造方法
CN109830529A (zh) * 2019-01-31 2019-05-31 西安理工大学 一种提升开通速度的超高压碳化硅晶闸管及其制作方法

Family Cites Families (12)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5967795A (en) * 1995-08-30 1999-10-19 Asea Brown Boveri Ab SiC semiconductor device comprising a pn junction with a voltage absorbing edge
JP4011848B2 (ja) * 2000-12-12 2007-11-21 関西電力株式会社 高耐電圧半導体装置
SE525574C2 (sv) 2002-08-30 2005-03-15 Okmetic Oyj Lågdopat kiselkarbidsubstrat och användning därav i högspänningskomponenter
US6974720B2 (en) 2003-10-16 2005-12-13 Cree, Inc. Methods of forming power semiconductor devices using boule-grown silicon carbide drift layers and power semiconductor devices formed thereby
JP4585772B2 (ja) 2004-02-06 2010-11-24 関西電力株式会社 高耐圧ワイドギャップ半導体装置及び電力装置
US7345310B2 (en) * 2005-12-22 2008-03-18 Cree, Inc. Silicon carbide bipolar junction transistors having a silicon carbide passivation layer on the base region thereof
US7372087B2 (en) * 2006-06-01 2008-05-13 Northrop Grumman Corporation Semiconductor structure for use in a static induction transistor having improved gate-to-drain breakdown voltage
JP5140347B2 (ja) * 2007-08-29 2013-02-06 株式会社日立製作所 バイポーラトランジスタ及びその製造方法
JP5358926B2 (ja) * 2007-11-01 2013-12-04 富士電機株式会社 炭化珪素トレンチｍｏｓ型半導体装置
US8097919B2 (en) * 2008-08-11 2012-01-17 Cree, Inc. Mesa termination structures for power semiconductor devices including mesa step buffers
US7759186B2 (en) * 2008-09-03 2010-07-20 The United States Of America As Represented By The Secretary Of The Navy Method for fabricating junction termination extension with formation of photosensitive dopant mask to control doping profile and lateral width for high-voltage electronic devices
SE537101C2 (sv) 2010-03-30 2015-01-07 Fairchild Semiconductor Halvledarkomponent och förfarande för utformning av en struktur i ett målsubstrat för tillverkning av en halvledarkomponent

Also Published As

Publication number Publication date
DE112013000866B4 (de) 2019-09-19
DE112013000866T5 (de) 2014-10-23
JP2015510272A (ja) 2015-04-02
JP6335795B2 (ja) 2018-05-30
WO2013119548A1 (en) 2013-08-15

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