CA2350922C - Concurrent processing for event-based systems - Google Patents
Concurrent processing for event-based systems Download PDFInfo
- Publication number
- CA2350922C CA2350922C CA2350922A CA2350922A CA2350922C CA 2350922 C CA2350922 C CA 2350922C CA 2350922 A CA2350922 A CA 2350922A CA 2350922 A CA2350922 A CA 2350922A CA 2350922 C CA2350922 C CA 2350922C
- Authority
- CA
- Canada
- Prior art keywords
- processor
- events
- processors
- event
- software
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
Links
- 238000012545 processing Methods 0.000 title claims abstract description 117
- 230000015654 memory Effects 0.000 claims description 41
- 238000000034 method Methods 0.000 claims description 24
- 238000004891 communication Methods 0.000 claims description 14
- 238000003672 processing method Methods 0.000 claims description 13
- 238000013507 mapping Methods 0.000 claims description 12
- 230000004044 response Effects 0.000 claims description 8
- 230000008569 process Effects 0.000 claims description 7
- 239000011159 matrix material Substances 0.000 abstract description 7
- 239000003550 marker Substances 0.000 description 23
- 238000001514 detection method Methods 0.000 description 14
- 238000013461 design Methods 0.000 description 9
- 238000010586 diagram Methods 0.000 description 9
- 238000013459 approach Methods 0.000 description 5
- 230000011664 signaling Effects 0.000 description 5
- 239000013256 coordination polymer Substances 0.000 description 4
- 238000012163 sequencing technique Methods 0.000 description 4
- 238000004458 analytical method Methods 0.000 description 2
- 230000009286 beneficial effect Effects 0.000 description 2
- 238000011156 evaluation Methods 0.000 description 2
- 230000006870 function Effects 0.000 description 2
- 238000003780 insertion Methods 0.000 description 2
- 230000037431 insertion Effects 0.000 description 2
- 230000007246 mechanism Effects 0.000 description 2
- 238000012986 modification Methods 0.000 description 2
- 230000004048 modification Effects 0.000 description 2
- 238000012546 transfer Methods 0.000 description 2
- 230000001131 transforming effect Effects 0.000 description 2
- XXXSILNSXNPGKG-ZHACJKMWSA-N Crotoxyphos Chemical compound COP(=O)(OC)O\C(C)=C\C(=O)OC(C)C1=CC=CC=C1 XXXSILNSXNPGKG-ZHACJKMWSA-N 0.000 description 1
- 238000007630 basic procedure Methods 0.000 description 1
- 239000000872 buffer Substances 0.000 description 1
- 238000012512 characterization method Methods 0.000 description 1
- 230000000977 initiatory effect Effects 0.000 description 1
- 230000010354 integration Effects 0.000 description 1
- 230000007774 longterm Effects 0.000 description 1
- 238000012423 maintenance Methods 0.000 description 1
- 238000013508 migration Methods 0.000 description 1
- 230000005012 migration Effects 0.000 description 1
- 238000012805 post-processing Methods 0.000 description 1
- 239000005364 simax Substances 0.000 description 1
- 238000000638 solvent extraction Methods 0.000 description 1
- 230000003068 static effect Effects 0.000 description 1
Classifications
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
- G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/46—Multiprogramming arrangements
- G06F9/50—Allocation of resources, e.g. of the central processing unit [CPU]
- G06F9/5061—Partitioning or combining of resources
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/46—Multiprogramming arrangements
- G06F9/52—Program synchronisation; Mutual exclusion, e.g. by means of semaphores
Landscapes
- Engineering & Computer Science (AREA)
- Software Systems (AREA)
- Theoretical Computer Science (AREA)
- Physics & Mathematics (AREA)
- General Engineering & Computer Science (AREA)
- General Physics & Mathematics (AREA)
- Multi Processors (AREA)
- Computer And Data Communications (AREA)
Applications Claiming Priority (3)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| SE9803901A SE9803901D0 (sv) | 1998-11-16 | 1998-11-16 | a device for a service network |
| SE9803901-9 | 1999-03-29 | ||
| PCT/SE1999/002064 WO2000029942A1 (en) | 1998-11-16 | 1999-11-12 | Concurrent processing for event-based systems |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CA2350922A1 CA2350922A1 (en) | 2000-05-25 |
| CA2350922C true CA2350922C (en) | 2014-06-03 |
Family
ID=50202830
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CA2350922A Expired - Fee Related CA2350922C (en) | 1998-11-16 | 1999-11-12 | Concurrent processing for event-based systems |
Country Status (7)
| Country | Link |
|---|---|
| EP (1) | EP1131703A1 (pt) |
| JP (1) | JP4489958B2 (pt) |
| KR (1) | KR100401443B1 (pt) |
| AU (1) | AU1437300A (pt) |
| BR (1) | BR9915363B1 (pt) |
| CA (1) | CA2350922C (pt) |
| WO (1) | WO2000029942A1 (pt) |
Families Citing this family (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6633865B1 (en) | 1999-12-23 | 2003-10-14 | Pmc-Sierra Limited | Multithreaded address resolution system |
| US7080238B2 (en) * | 2000-11-07 | 2006-07-18 | Alcatel Internetworking, (Pe), Inc. | Non-blocking, multi-context pipelined processor |
| US7526770B2 (en) | 2003-05-12 | 2009-04-28 | Microsoft Corporation | System and method for employing object-based pipelines |
| JP2006146678A (ja) | 2004-11-22 | 2006-06-08 | Hitachi Ltd | 情報処理装置におけるプログラム制御方法、情報処理装置、及びプログラム |
| US8122006B2 (en) | 2007-05-29 | 2012-02-21 | Oracle International Corporation | Event processing query language including retain clause |
| US20090070786A1 (en) * | 2007-09-11 | 2009-03-12 | Bea Systems, Inc. | Xml-based event processing networks for event server |
| WO2011107163A1 (en) * | 2010-03-05 | 2011-09-09 | Telefonaktiebolaget L M Ericsson (Publ) | A processing system with processing load control |
| EP2650750A1 (en) * | 2012-04-12 | 2013-10-16 | Telefonaktiebolaget L M Ericsson AB (Publ) | Apparatus and method for allocating tasks in a node of a telecommunication network |
Family Cites Families (24)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS58149555A (ja) * | 1982-02-27 | 1983-09-05 | Fujitsu Ltd | 並列処理装置 |
| JPS6347835A (ja) * | 1986-08-18 | 1988-02-29 | Agency Of Ind Science & Technol | パイプライン計算機 |
| JPS63301332A (ja) * | 1987-06-02 | 1988-12-08 | Nec Corp | ジョブ実行方式 |
| US5072364A (en) * | 1989-05-24 | 1991-12-10 | Tandem Computers Incorporated | Method and apparatus for recovering from an incorrect branch prediction in a processor that executes a family of instructions in parallel |
| JP2957223B2 (ja) | 1990-03-20 | 1999-10-04 | 富士通株式会社 | コールプロセッサの負荷分散制御方式 |
| JPH07122866B1 (pt) * | 1990-05-07 | 1995-12-25 | Mitsubishi Electric Corp | |
| JPH04100449A (ja) | 1990-08-20 | 1992-04-02 | Toshiba Corp | Ａｔｍ通信システム |
| JPH04273535A (ja) * | 1991-02-28 | 1992-09-29 | Nec Software Ltd | マルチタスク制御方式 |
| US5287467A (en) * | 1991-04-18 | 1994-02-15 | International Business Machines Corporation | Pipeline for removing and concurrently executing two or more branch instructions in synchronization with other instructions executing in the execution unit |
| CA2067576C (en) * | 1991-07-10 | 1998-04-14 | Jimmie D. Edrington | Dynamic load balancing for a multiprocessor pipeline |
| JPH0546415A (ja) * | 1991-08-14 | 1993-02-26 | Nec Software Ltd | 排他管理制御方式 |
| JP3182806B2 (ja) | 1991-09-20 | 2001-07-03 | 株式会社日立製作所 | バージョンアップ方法 |
| JPH05204876A (ja) * | 1991-10-01 | 1993-08-13 | Hitachi Ltd | 階層型ネットワークおよび階層型ネットワークを用いたマルチプロセッサシステム |
| US5471580A (en) | 1991-10-01 | 1995-11-28 | Hitachi, Ltd. | Hierarchical network having lower and upper layer networks where gate nodes are selectively chosen in the lower and upper layer networks to form a recursive layer |
| US5511172A (en) * | 1991-11-15 | 1996-04-23 | Matsushita Electric Co. Ind, Ltd. | Speculative execution processor |
| US5379428A (en) * | 1993-02-01 | 1995-01-03 | Belobox Systems, Inc. | Hardware process scheduler and processor interrupter for parallel processing computer systems |
| JP2655466B2 (ja) | 1993-03-18 | 1997-09-17 | 日本電気株式会社 | パケット交換装置 |
| WO1994027216A1 (en) | 1993-05-14 | 1994-11-24 | Massachusetts Institute Of Technology | Multiprocessor coupling system with integrated compile and run time scheduling for parallelism |
| JP3005397B2 (ja) * | 1993-09-06 | 2000-01-31 | 関西日本電気ソフトウェア株式会社 | デッドロック多発自動回避方式 |
| ES2138051T3 (es) * | 1994-01-03 | 2000-01-01 | Intel Corp | Metodo y aparato para la realizacion de un sistema de resolucion de bifurcaciones en cuatro etapas en un procesador informatico. |
| JPH0836552A (ja) * | 1994-07-22 | 1996-02-06 | Nippon Telegr & Teleph Corp <Ntt> | 分散処理方法、分散処理システム及び分散処理管理装置 |
| JP2000502202A (ja) | 1995-12-19 | 2000-02-22 | テレフオンアクチーボラゲツト エル エム エリクソン（パブル） | 命令プロセッサのジョブスケジューリング |
| US5848257A (en) * | 1996-09-20 | 1998-12-08 | Bay Networks, Inc. | Method and apparatus for multitasking in a computer system |
| US6240509B1 (en) * | 1997-12-16 | 2001-05-29 | Intel Corporation | Out-of-pipeline trace buffer for holding instructions that may be re-executed following misspeculation |
-
1999
- 1999-11-12 EP EP99972323A patent/EP1131703A1/en not_active Withdrawn
- 1999-11-12 BR BRPI9915363-7A patent/BR9915363B1/pt not_active IP Right Cessation
- 1999-11-12 AU AU14373/00A patent/AU1437300A/en not_active Abandoned
- 1999-11-12 KR KR10-2001-7005796A patent/KR100401443B1/ko not_active IP Right Cessation
- 1999-11-12 CA CA2350922A patent/CA2350922C/en not_active Expired - Fee Related
- 1999-11-12 JP JP2000582885A patent/JP4489958B2/ja not_active Expired - Fee Related
- 1999-11-12 WO PCT/SE1999/002064 patent/WO2000029942A1/en active IP Right Grant
Also Published As
| Publication number | Publication date |
|---|---|
| JP2002530737A (ja) | 2002-09-17 |
| JP4489958B2 (ja) | 2010-06-23 |
| BR9915363B1 (pt) | 2012-12-25 |
| KR20010080958A (ko) | 2001-08-25 |
| CA2350922A1 (en) | 2000-05-25 |
| WO2000029942A1 (en) | 2000-05-25 |
| EP1131703A1 (en) | 2001-09-12 |
| BR9915363A (pt) | 2001-07-31 |
| AU1437300A (en) | 2000-06-05 |
| KR100401443B1 (ko) | 2003-10-17 |
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Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| EEER | Examination request | ||
| MKLA | Lapsed |
Effective date: 20161114 |