CA2350922C - Traitement simultane pour systemes bases sur des evenements - Google Patents

Traitement simultane pour systemes bases sur des evenements Download PDF

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Publication number
CA2350922C
CA2350922C CA2350922A CA2350922A CA2350922C CA 2350922 C CA2350922 C CA 2350922C CA 2350922 A CA2350922 A CA 2350922A CA 2350922 A CA2350922 A CA 2350922A CA 2350922 C CA2350922 C CA 2350922C
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CA
Canada
Prior art keywords
processor
events
processors
event
software
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
CA2350922A
Other languages
English (en)
Other versions
CA2350922A1 (fr
Inventor
Per Anders Holmberg
Lars-Orjan Kling
Sten Edward Johnson
Milind Sohoni
Nikhil Tikekar
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Telefonaktiebolaget LM Ericsson AB
Original Assignee
Telefonaktiebolaget LM Ericsson AB
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority claimed from SE9803901A external-priority patent/SE9803901D0/xx
Application filed by Telefonaktiebolaget LM Ericsson AB filed Critical Telefonaktiebolaget LM Ericsson AB
Publication of CA2350922A1 publication Critical patent/CA2350922A1/fr
Application granted granted Critical
Publication of CA2350922C publication Critical patent/CA2350922C/fr
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

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Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/46—Multiprogramming arrangements
    • G06F9/50—Allocation of resources, e.g. of the central processing unit [CPU]
    • G06F9/5061—Partitioning or combining of resources
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/46—Multiprogramming arrangements
    • G06F9/52—Program synchronisation; Mutual exclusion, e.g. by means of semaphores

Landscapes

  • Engineering & Computer Science (AREA)
  • Software Systems (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Multi Processors (AREA)
  • Computer And Data Communications (AREA)

Abstract

Selon l'invention, des processeurs multiples (11) à mémoire partagée sont introduits au niveau le plus haut ou à des niveaux les plus hauts de données d'un système de traitement hiérarchique réparti (1) et l'utilisation des processeurs est optimisée sur la base de flux d'événements simultanés identifiés dans le système. Selon un premier aspect, des catégories dites non en transit (NCC) d'événements sont projetées sur les processeurs multiples (11) pour procéder à une exécution simultanée. Selon un second aspect de l'invention, les processeurs (11) sont exploités sous la forme d'un pipeline multiprocesseur, dans lequel chaque événement arrivant dans le pipeline est traité par tranches à la manière d'une chaîne d'événements intérieurs, lesquelles sont exécutées à différents étages du pipeline. On obtient une structure de traitement général par ce que l'on appelle traitement matriciel, dans laquelle des catégories non en transit sont exécutées par différents ensembles de processeurs, et au moins un ensemble de processeurs fonctionne à la manière d'une pipeline multiprocesseur dans lequel un événement extérieur est traité par tranches dans différents étages de processeurs du pipeline.
CA2350922A 1998-11-16 1999-11-12 Traitement simultane pour systemes bases sur des evenements Expired - Fee Related CA2350922C (fr)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
SE9803901A SE9803901D0 (sv) 1998-11-16 1998-11-16 a device for a service network
SE9803901-9 1999-06-22
PCT/SE1999/002064 WO2000029942A1 (fr) 1998-11-16 1999-11-12 Traitement simultane pour systemes bases sur des evenements

Publications (2)

Publication Number Publication Date
CA2350922A1 CA2350922A1 (fr) 2000-05-25
CA2350922C true CA2350922C (fr) 2014-06-03

Family

ID=50202830

Family Applications (1)

Application Number Title Priority Date Filing Date
CA2350922A Expired - Fee Related CA2350922C (fr) 1998-11-16 1999-11-12 Traitement simultane pour systemes bases sur des evenements

Country Status (7)

Country Link
EP (1) EP1131703A1 (fr)
JP (1) JP4489958B2 (fr)
KR (1) KR100401443B1 (fr)
AU (1) AU1437300A (fr)
BR (1) BR9915363B1 (fr)
CA (1) CA2350922C (fr)
WO (1) WO2000029942A1 (fr)

Families Citing this family (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6633865B1 (en) 1999-12-23 2003-10-14 Pmc-Sierra Limited Multithreaded address resolution system
US7080238B2 (en) 2000-11-07 2006-07-18 Alcatel Internetworking, (Pe), Inc. Non-blocking, multi-context pipelined processor
US7526770B2 (en) 2003-05-12 2009-04-28 Microsoft Corporation System and method for employing object-based pipelines
JP2006146678A (ja) 2004-11-22 2006-06-08 Hitachi Ltd 情報処理装置におけるプログラム制御方法、情報処理装置、及びプログラム
US8122006B2 (en) 2007-05-29 2012-02-21 Oracle International Corporation Event processing query language including retain clause
US8543534B2 (en) 2007-09-11 2013-09-24 Oracle International Corporation Concurrency in event processing networks for event server
WO2011107163A1 (fr) * 2010-03-05 2011-09-09 Telefonaktiebolaget L M Ericsson (Publ) Système de traitement à gestion de la charge de traitement
EP2650750A1 (fr) * 2012-04-12 2013-10-16 Telefonaktiebolaget L M Ericsson AB (Publ) Appareil et procédé d'attribution de tâches dans un nýud d'un réseau de télécommunication

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JPS58149555A (ja) * 1982-02-27 1983-09-05 Fujitsu Ltd 並列処理装置
JPS6347835A (ja) * 1986-08-18 1988-02-29 Agency Of Ind Science & Technol パイプライン計算機
JPS63301332A (ja) * 1987-06-02 1988-12-08 Nec Corp ジョブ実行方式
US5072364A (en) * 1989-05-24 1991-12-10 Tandem Computers Incorporated Method and apparatus for recovering from an incorrect branch prediction in a processor that executes a family of instructions in parallel
JP2957223B2 (ja) 1990-03-20 1999-10-04 富士通株式会社 コールプロセッサの負荷分散制御方式
JPH07122866B1 (fr) * 1990-05-07 1995-12-25 Mitsubishi Electric Corp
JPH04100449A (ja) 1990-08-20 1992-04-02 Toshiba Corp Ａｔｍ通信システム
JPH04273535A (ja) * 1991-02-28 1992-09-29 Nec Software Ltd マルチタスク制御方式
US5287467A (en) * 1991-04-18 1994-02-15 International Business Machines Corporation Pipeline for removing and concurrently executing two or more branch instructions in synchronization with other instructions executing in the execution unit
CA2067576C (fr) * 1991-07-10 1998-04-14 Jimmie D. Edrington Equilibrage dynamique des charges pour pipeline a multiprocesseur
JPH0546415A (ja) * 1991-08-14 1993-02-26 Nec Software Ltd 排他管理制御方式
JP3182806B2 (ja) 1991-09-20 2001-07-03 株式会社日立製作所 バージョンアップ方法
JPH05204876A (ja) * 1991-10-01 1993-08-13 Hitachi Ltd 階層型ネットワークおよび階層型ネットワークを用いたマルチプロセッサシステム
US5471580A (en) 1991-10-01 1995-11-28 Hitachi, Ltd. Hierarchical network having lower and upper layer networks where gate nodes are selectively chosen in the lower and upper layer networks to form a recursive layer
US5511172A (en) * 1991-11-15 1996-04-23 Matsushita Electric Co. Ind, Ltd. Speculative execution processor
US5379428A (en) * 1993-02-01 1995-01-03 Belobox Systems, Inc. Hardware process scheduler and processor interrupter for parallel processing computer systems
JP2655466B2 (ja) 1993-03-18 1997-09-17 日本電気株式会社 パケット交換装置
WO1994027216A1 (fr) 1993-05-14 1994-11-24 Massachusetts Institute Of Technology Systeme de couplage multiprocesseur a ordonnancement integre de la compilation et de l'execution assurant un traitement parallele
JP3005397B2 (ja) * 1993-09-06 2000-01-31 関西日本電気ソフトウェア株式会社 デッドロック多発自動回避方式
DE69420540T2 (de) * 1994-01-03 2000-02-10 Intel Corp., Santa Clara Verfahren und Vorrichtung zum Implementieren eines vierstufigen Verzweigungsauflosungssystem in einem Rechnerprozessor
JPH0836552A (ja) * 1994-07-22 1996-02-06 Nippon Telegr & Teleph Corp <Ntt> 分散処理方法、分散処理システム及び分散処理管理装置
AU714853B2 (en) * 1995-12-19 2000-01-13 Telefonaktiebolaget Lm Ericsson (Publ) Job scheduling for instruction processor
US5848257A (en) * 1996-09-20 1998-12-08 Bay Networks, Inc. Method and apparatus for multitasking in a computer system
US6240509B1 (en) * 1997-12-16 2001-05-29 Intel Corporation Out-of-pipeline trace buffer for holding instructions that may be re-executed following misspeculation

Also Published As

Publication number Publication date
JP4489958B2 (ja) 2010-06-23
KR20010080958A (ko) 2001-08-25
JP2002530737A (ja) 2002-09-17
KR100401443B1 (ko) 2003-10-17
CA2350922A1 (fr) 2000-05-25
EP1131703A1 (fr) 2001-09-12
BR9915363A (pt) 2001-07-31
BR9915363B1 (pt) 2012-12-25
WO2000029942A1 (fr) 2000-05-25
AU1437300A (en) 2000-06-05

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Effective date: 20161114