BR9915363B1 - sistema de processamento hierÁrquico distribuÍdo com base em eventos, mÉtodo de processamento num sistema de processamento hierÁrquico distribuÍdo com base em eventos, e, sistema de comunicaÇço. - Google Patents

sistema de processamento hierÁrquico distribuÍdo com base em eventos, mÉtodo de processamento num sistema de processamento hierÁrquico distribuÍdo com base em eventos, e, sistema de comunicaÇço.

Info

Publication number
BR9915363B1
BR9915363B1 BRPI9915363-7A BR9915363A BR9915363B1 BR 9915363 B1 BR9915363 B1 BR 9915363B1 BR 9915363 A BR9915363 A BR 9915363A BR 9915363 B1 BR9915363 B1 BR 9915363B1
Authority
BR
Brazil
Prior art keywords
event
based distributed
distributed hierarchical
processing system
hierarchical processing
Prior art date
Application number
BRPI9915363-7A
Other languages
English (en)
Other versions
BR9915363A (pt
Inventor
Per Anders Holmberg
Lars-Oerjan Kling
Sten Edward Johnson
Milind Sohoni
Nikhil Tikekar
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority claimed from SE9803901A external-priority patent/SE9803901D0/xx
Application filed filed Critical
Publication of BR9915363A publication Critical patent/BR9915363A/pt
Publication of BR9915363B1 publication Critical patent/BR9915363B1/pt

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/46—Multiprogramming arrangements
    • G06F9/50—Allocation of resources, e.g. of the central processing unit [CPU]
    • G06F9/5061—Partitioning or combining of resources
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/46—Multiprogramming arrangements
    • G06F9/52—Program synchronisation; Mutual exclusion, e.g. by means of semaphores

Landscapes

  • Engineering & Computer Science (AREA)
  • Software Systems (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Multi Processors (AREA)
  • Computer And Data Communications (AREA)
BRPI9915363-7A 1998-11-16 1999-11-12 sistema de processamento hierÁrquico distribuÍdo com base em eventos, mÉtodo de processamento num sistema de processamento hierÁrquico distribuÍdo com base em eventos, e, sistema de comunicaÇço. BR9915363B1 (pt)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
SE9803901A SE9803901D0 (sv) 1998-11-16 1998-11-16 a device for a service network
PCT/SE1999/002064 WO2000029942A1 (en) 1998-11-16 1999-11-12 Concurrent processing for event-based systems

Publications (2)

Publication Number Publication Date
BR9915363A BR9915363A (pt) 2001-07-31
BR9915363B1 true BR9915363B1 (pt) 2012-12-25

Family

ID=50202830

Family Applications (1)

Application Number Title Priority Date Filing Date
BRPI9915363-7A BR9915363B1 (pt) 1998-11-16 1999-11-12 sistema de processamento hierÁrquico distribuÍdo com base em eventos, mÉtodo de processamento num sistema de processamento hierÁrquico distribuÍdo com base em eventos, e, sistema de comunicaÇço.

Country Status (7)

Country Link
EP (1) EP1131703A1 (pt)
JP (1) JP4489958B2 (pt)
KR (1) KR100401443B1 (pt)
AU (1) AU1437300A (pt)
BR (1) BR9915363B1 (pt)
CA (1) CA2350922C (pt)
WO (1) WO2000029942A1 (pt)

Families Citing this family (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6633865B1 (en) 1999-12-23 2003-10-14 Pmc-Sierra Limited Multithreaded address resolution system
US7080238B2 (en) 2000-11-07 2006-07-18 Alcatel Internetworking, (Pe), Inc. Non-blocking, multi-context pipelined processor
US7526770B2 (en) 2003-05-12 2009-04-28 Microsoft Corporation System and method for employing object-based pipelines
JP2006146678A (ja) 2004-11-22 2006-06-08 Hitachi Ltd 情報処理装置におけるプログラム制御方法、情報処理装置、及びプログラム
US20080301125A1 (en) 2007-05-29 2008-12-04 Bea Systems, Inc. Event processing query language including an output clause
US20090070765A1 (en) 2007-09-11 2009-03-12 Bea Systems, Inc. Xml-based configuration for event processing networks
WO2011107163A1 (en) * 2010-03-05 2011-09-09 Telefonaktiebolaget L M Ericsson (Publ) A processing system with processing load control
EP2650750A1 (en) * 2012-04-12 2013-10-16 Telefonaktiebolaget L M Ericsson AB (Publ) Apparatus and method for allocating tasks in a node of a telecommunication network

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JPS58149555A (ja) * 1982-02-27 1983-09-05 Fujitsu Ltd 並列処理装置
JPS6347835A (ja) * 1986-08-18 1988-02-29 Agency Of Ind Science & Technol パイプライン計算機
JPS63301332A (ja) * 1987-06-02 1988-12-08 Nec Corp ジョブ実行方式
US5072364A (en) * 1989-05-24 1991-12-10 Tandem Computers Incorporated Method and apparatus for recovering from an incorrect branch prediction in a processor that executes a family of instructions in parallel
JP2957223B2 (ja) 1990-03-20 1999-10-04 富士通株式会社 コールプロセッサの負荷分散制御方式
JPH07122866B1 (pt) * 1990-05-07 1995-12-25 Mitsubishi Electric Corp
JPH04100449A (ja) 1990-08-20 1992-04-02 Toshiba Corp Ａｔｍ通信システム
JPH04273535A (ja) * 1991-02-28 1992-09-29 Nec Software Ltd マルチタスク制御方式
US5287467A (en) * 1991-04-18 1994-02-15 International Business Machines Corporation Pipeline for removing and concurrently executing two or more branch instructions in synchronization with other instructions executing in the execution unit
CA2067576C (en) * 1991-07-10 1998-04-14 Jimmie D. Edrington Dynamic load balancing for a multiprocessor pipeline
JPH0546415A (ja) * 1991-08-14 1993-02-26 Nec Software Ltd 排他管理制御方式
JP3182806B2 (ja) 1991-09-20 2001-07-03 株式会社日立製作所 バージョンアップ方法
JPH05204876A (ja) * 1991-10-01 1993-08-13 Hitachi Ltd 階層型ネットワークおよび階層型ネットワークを用いたマルチプロセッサシステム
US5471580A (en) 1991-10-01 1995-11-28 Hitachi, Ltd. Hierarchical network having lower and upper layer networks where gate nodes are selectively chosen in the lower and upper layer networks to form a recursive layer
US5511172A (en) * 1991-11-15 1996-04-23 Matsushita Electric Co. Ind, Ltd. Speculative execution processor
US5379428A (en) * 1993-02-01 1995-01-03 Belobox Systems, Inc. Hardware process scheduler and processor interrupter for parallel processing computer systems
JP2655466B2 (ja) 1993-03-18 1997-09-17 日本電気株式会社 パケット交換装置
WO1994027216A1 (en) 1993-05-14 1994-11-24 Massachusetts Institute Of Technology Multiprocessor coupling system with integrated compile and run time scheduling for parallelism
JP3005397B2 (ja) * 1993-09-06 2000-01-31 関西日本電気ソフトウェア株式会社 デッドロック多発自動回避方式
ES2138051T3 (es) * 1994-01-03 2000-01-01 Intel Corp Metodo y aparato para la realizacion de un sistema de resolucion de bifurcaciones en cuatro etapas en un procesador informatico.
JPH0836552A (ja) * 1994-07-22 1996-02-06 Nippon Telegr & Teleph Corp <Ntt> 分散処理方法、分散処理システム及び分散処理管理装置
AU714853B2 (en) 1995-12-19 2000-01-13 Telefonaktiebolaget Lm Ericsson (Publ) Job scheduling for instruction processor
US5848257A (en) * 1996-09-20 1998-12-08 Bay Networks, Inc. Method and apparatus for multitasking in a computer system
US6240509B1 (en) * 1997-12-16 2001-05-29 Intel Corporation Out-of-pipeline trace buffer for holding instructions that may be re-executed following misspeculation

Also Published As

Publication number Publication date
JP2002530737A (ja) 2002-09-17
CA2350922A1 (en) 2000-05-25
WO2000029942A1 (en) 2000-05-25
CA2350922C (en) 2014-06-03
BR9915363A (pt) 2001-07-31
KR20010080958A (ko) 2001-08-25
AU1437300A (en) 2000-06-05
KR100401443B1 (ko) 2003-10-17
EP1131703A1 (en) 2001-09-12
JP4489958B2 (ja) 2010-06-23

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Legal Events

Date Code Title Description
B07A Technical examination (opinion): publication of technical examination (opinion) [chapter 7.1 patent gazette]
B06A Notification to applicant to reply to the report for non-patentability or inadequacy of the application [chapter 6.1 patent gazette]
B09A Decision: intention to grant [chapter 9.1 patent gazette]
B16A Patent or certificate of addition of invention granted

Free format text: PRAZO DE VALIDADE: 10 (DEZ) ANOS CONTADOS A PARTIR DE 26/12/2012, OBSERVADAS AS CONDICOES LEGAIS.

B21F Lapse acc. art. 78, item iv - on non-payment of the annual fees in time

Free format text: REFERENTE A 17A ANUIDADE.

B24J Lapse because of non-payment of annual fees (definitively: art 78 iv lpi, resolution 113/2013 art. 12)

Free format text: EM VIRTUDE DA EXTINCAO PUBLICADA NA RPI 2386 DE 27-09-2016 E CONSIDERANDO AUSENCIA DE MANIFESTACAO DENTRO DOS PRAZOS LEGAIS, INFORMO QUE CABE SER MANTIDA A EXTINCAO DA PATENTE E SEUS CERTIFICADOS, CONFORME O DISPOSTO NO ARTIGO 12, DA RESOLUCAO 113/2013.