AU1437300A - Concurrent processing for event-based systems - Google Patents

Concurrent processing for event-based systems

Info

Publication number
AU1437300A
AU1437300A AU14373/00A AU1437300A AU1437300A AU 1437300 A AU1437300 A AU 1437300A AU 14373/00 A AU14373/00 A AU 14373/00A AU 1437300 A AU1437300 A AU 1437300A AU 1437300 A AU1437300 A AU 1437300A
Authority
AU
Australia
Prior art keywords
event
based systems
concurrent processing
concurrent
processing
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Abandoned
Application number
AU14373/00A
Inventor
Per Anders Holmberg
Sten Edward Johnson
Lars-Orjan Kling
Milind Sohoni
Nikhil Tikekar
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Telefonaktiebolaget LM Ericsson AB
Original Assignee
Telefonaktiebolaget LM Ericsson AB
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority claimed from SE9803901A external-priority patent/SE9803901D0/en
Application filed by Telefonaktiebolaget LM Ericsson AB filed Critical Telefonaktiebolaget LM Ericsson AB
Publication of AU1437300A publication Critical patent/AU1437300A/en
Abandoned legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/46—Multiprogramming arrangements
    • G06F9/50—Allocation of resources, e.g. of the central processing unit [CPU]
    • G06F9/5061—Partitioning or combining of resources
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/46—Multiprogramming arrangements
    • G06F9/52—Program synchronisation; Mutual exclusion, e.g. by means of semaphores

Landscapes

  • Engineering & Computer Science (AREA)
  • Software Systems (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Multi Processors (AREA)
  • Computer And Data Communications (AREA)
AU14373/00A 1998-11-16 1999-11-12 Concurrent processing for event-based systems Abandoned AU1437300A (en)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
SE9803901A SE9803901D0 (en) 1998-11-16 1998-11-16 a device for a service network
SE9803901 1998-11-16
PCT/SE1999/002064 WO2000029942A1 (en) 1998-11-16 1999-11-12 Concurrent processing for event-based systems

Publications (1)

Publication Number Publication Date
AU1437300A true AU1437300A (en) 2000-06-05

Family

ID=50202830

Family Applications (1)

Application Number Title Priority Date Filing Date
AU14373/00A Abandoned AU1437300A (en) 1998-11-16 1999-11-12 Concurrent processing for event-based systems

Country Status (7)

Country Link
EP (1) EP1131703A1 (en)
JP (1) JP4489958B2 (en)
KR (1) KR100401443B1 (en)
AU (1) AU1437300A (en)
BR (1) BR9915363B1 (en)
CA (1) CA2350922C (en)
WO (1) WO2000029942A1 (en)

Families Citing this family (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6633865B1 (en) 1999-12-23 2003-10-14 Pmc-Sierra Limited Multithreaded address resolution system
US7080238B2 (en) * 2000-11-07 2006-07-18 Alcatel Internetworking, (Pe), Inc. Non-blocking, multi-context pipelined processor
US7526770B2 (en) 2003-05-12 2009-04-28 Microsoft Corporation System and method for employing object-based pipelines
JP2006146678A (en) 2004-11-22 2006-06-08 Hitachi Ltd Method for controlling program in information processor, information processor and program
US20080301125A1 (en) 2007-05-29 2008-12-04 Bea Systems, Inc. Event processing query language including an output clause
US8543534B2 (en) * 2007-09-11 2013-09-24 Oracle International Corporation Concurrency in event processing networks for event server
WO2011107163A1 (en) * 2010-03-05 2011-09-09 Telefonaktiebolaget L M Ericsson (Publ) A processing system with processing load control
EP2650750A1 (en) * 2012-04-12 2013-10-16 Telefonaktiebolaget L M Ericsson AB (Publ) Apparatus and method for allocating tasks in a node of a telecommunication network

Family Cites Families (24)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS58149555A (en) * 1982-02-27 1983-09-05 Fujitsu Ltd Parallel processing device
JPS6347835A (en) * 1986-08-18 1988-02-29 Agency Of Ind Science & Technol Pipeline computer
JPS63301332A (en) * 1987-06-02 1988-12-08 Nec Corp Job executing system
US5072364A (en) * 1989-05-24 1991-12-10 Tandem Computers Incorporated Method and apparatus for recovering from an incorrect branch prediction in a processor that executes a family of instructions in parallel
JP2957223B2 (en) 1990-03-20 1999-10-04 富士通株式会社 Load distribution control method for call processor
JPH07122866B1 (en) * 1990-05-07 1995-12-25 Mitsubishi Electric Corp
JPH04100449A (en) 1990-08-20 1992-04-02 Toshiba Corp Atm communication system
JPH04273535A (en) * 1991-02-28 1992-09-29 Nec Software Ltd Multitask control system
US5287467A (en) * 1991-04-18 1994-02-15 International Business Machines Corporation Pipeline for removing and concurrently executing two or more branch instructions in synchronization with other instructions executing in the execution unit
CA2067576C (en) * 1991-07-10 1998-04-14 Jimmie D. Edrington Dynamic load balancing for a multiprocessor pipeline
JPH0546415A (en) * 1991-08-14 1993-02-26 Nec Software Ltd Exclusive management control system
JP3182806B2 (en) 1991-09-20 2001-07-03 株式会社日立製作所 How to upgrade
US5471580A (en) 1991-10-01 1995-11-28 Hitachi, Ltd. Hierarchical network having lower and upper layer networks where gate nodes are selectively chosen in the lower and upper layer networks to form a recursive layer
JPH05204876A (en) * 1991-10-01 1993-08-13 Hitachi Ltd Hierarchical network and multiprocessor using the same
US5511172A (en) * 1991-11-15 1996-04-23 Matsushita Electric Co. Ind, Ltd. Speculative execution processor
US5379428A (en) * 1993-02-01 1995-01-03 Belobox Systems, Inc. Hardware process scheduler and processor interrupter for parallel processing computer systems
JP2655466B2 (en) 1993-03-18 1997-09-17 日本電気株式会社 Packet switching equipment
WO1994027216A1 (en) * 1993-05-14 1994-11-24 Massachusetts Institute Of Technology Multiprocessor coupling system with integrated compile and run time scheduling for parallelism
JP3005397B2 (en) * 1993-09-06 2000-01-31 関西日本電気ソフトウェア株式会社 Deadlock frequent automatic avoidance method
DE69420540T2 (en) * 1994-01-03 2000-02-10 Intel Corp., Santa Clara Method and apparatus for implementing a four-stage branch resolution system in a computer processor
JPH0836552A (en) * 1994-07-22 1996-02-06 Nippon Telegr & Teleph Corp <Ntt> Method, system, and management device for decentralized porocessing
JP2000502202A (en) 1995-12-19 2000-02-22 テレフオンアクチーボラゲツト エル エム エリクソン（パブル） Instruction Processor Job Scheduling
US5848257A (en) * 1996-09-20 1998-12-08 Bay Networks, Inc. Method and apparatus for multitasking in a computer system
US6240509B1 (en) * 1997-12-16 2001-05-29 Intel Corporation Out-of-pipeline trace buffer for holding instructions that may be re-executed following misspeculation

Also Published As

Publication number Publication date
CA2350922C (en) 2014-06-03
KR20010080958A (en) 2001-08-25
BR9915363B1 (en) 2012-12-25
KR100401443B1 (en) 2003-10-17
JP4489958B2 (en) 2010-06-23
BR9915363A (en) 2001-07-31
CA2350922A1 (en) 2000-05-25
EP1131703A1 (en) 2001-09-12
WO2000029942A1 (en) 2000-05-25
JP2002530737A (en) 2002-09-17

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Legal Events

Date Code Title Description
MK6 Application lapsed section 142(2)(f)/reg. 8.3(3) - pct applic. not entering national phase