CA2006175A1 - Methode pour l'obtention d'une couche de caoutchouc de silicone a motif - Google Patents

Methode pour l'obtention d'une couche de caoutchouc de silicone a motif

Info

Publication number
CA2006175A1
CA2006175A1 CA2006175A CA2006175A CA2006175A1 CA 2006175 A1 CA2006175 A1 CA 2006175A1 CA 2006175 A CA2006175 A CA 2006175A CA 2006175 A CA2006175 A CA 2006175A CA 2006175 A1 CA2006175 A1 CA 2006175A1
Authority
CA
Canada
Prior art keywords
silicone rubber
rubber layer
polyimide film
patterned
forming patterned
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
CA2006175A
Other languages
English (en)
Other versions
CA2006175C (fr
Inventor
Kozo Matuo
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Rohm Co Ltd
Original Assignee
Rohm Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Rohm Co Ltd filed Critical Rohm Co Ltd
Publication of CA2006175A1 publication Critical patent/CA2006175A1/fr
Application granted granted Critical
Publication of CA2006175C publication Critical patent/CA2006175C/fr
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
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    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02—Bonding areas ; Manufacturing methods related thereto
    • H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L24/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
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    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3105—After-treatment
    • H01L21/311—Etching the insulating layers by chemical or physical means
    • H01L21/31144—Etching the insulating layers by chemical or physical means using masks
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    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/312—Organic layers, e.g. photoresist
    • H01L21/3121—Layers comprising organo-silicon compounds
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    • H01L23/29—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the material, e.g. carbon
    • H01L23/293—Organic, e.g. plastic
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    • H01L24/42—Wire connectors; Manufacturing methods related thereto
    • H01L24/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L24/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
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    • H01L21/02118—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer carbon based polymeric organic or inorganic material, e.g. polyimides, poly cyclobutene or PVC
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    • H01L2224/0212—Auxiliary members for bonding areas, e.g. spacers
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    • H01L2224/039—Methods of manufacturing bonding areas involving a specific sequence of method steps
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    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/04042—Bonding areas specifically adapted for wire connectors, e.g. wirebond pads
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    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
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    • H01L2224/0554—External layer
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    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/00014—Technical content checked by a classifier the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
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    • H01L2924/10162—Shape being a cuboid with a square active surface
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    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/102—Material of the semiconductor or solid state bodies
    • H01L2924/1025—Semiconducting materials
    • H01L2924/10251—Elemental semiconductors, i.e. Group IV
    • H01L2924/10253—Silicon [Si]

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • General Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
  • Drying Of Semiconductors (AREA)
  • Wire Bonding (AREA)
  • Formation Of Insulating Films (AREA)
  • Application Of Or Painting With Fluid Materials (AREA)
CA002006175A 1988-12-21 1989-12-20 Methode pour l'obtention d'une couche de caoutchouc de silicone a motif Expired - Fee Related CA2006175C (fr)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP63-324492 1988-12-21
JP63324492A JP2597396B2 (ja) 1988-12-21 1988-12-21 シリコーンゴム膜のパターン形成方法

Publications (2)

Publication Number Publication Date
CA2006175A1 true CA2006175A1 (fr) 1990-06-21
CA2006175C CA2006175C (fr) 1993-06-15

Family

ID=18166410

Family Applications (1)

Application Number Title Priority Date Filing Date
CA002006175A Expired - Fee Related CA2006175C (fr) 1988-12-21 1989-12-20 Methode pour l'obtention d'une couche de caoutchouc de silicone a motif

Country Status (3)

Country Link
US (1) US4988403A (fr)
JP (1) JP2597396B2 (fr)
CA (1) CA2006175C (fr)

Families Citing this family (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE59009067D1 (de) * 1990-04-27 1995-06-14 Siemens Ag Verfahren zur Herstellung einer Öffnung in einem Halbleiterschichtaufbau und dessen Verwendung zur Herstellung von Kontaktlöchern.
JPH04261049A (ja) * 1991-01-31 1992-09-17 Mitsubishi Electric Corp 半導体装置およびその製造方法
US5450286A (en) * 1992-12-04 1995-09-12 Parlex Corporation Printed circuit having a dielectric covercoat
SE9502258D0 (sv) * 1995-06-21 1995-06-21 Pharmacia Biotech Ab Method for the manufacture of a membrane-containing microstructure
FR2750250B1 (fr) * 1996-06-20 1998-08-21 Solaic Sa Procede de protection d'une galette de circuits integres, et galette de circuits integres obtenue
US20040102022A1 (en) * 2002-11-22 2004-05-27 Tongbi Jiang Methods of fabricating integrated circuitry
JP5644192B2 (ja) * 2010-06-09 2014-12-24 住友電気工業株式会社 積層樹脂膜の形成方法及び半導体デバイスの製造方法

Family Cites Families (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3833436A (en) * 1972-09-05 1974-09-03 Buckbee Mears Co Etching of polyimide films
US4119483A (en) * 1974-07-30 1978-10-10 U.S. Philips Corporation Method of structuring thin layers
US4218283A (en) * 1974-08-23 1980-08-19 Hitachi, Ltd. Method for fabricating semiconductor device and etchant for polymer resin
JPS57149734A (en) * 1981-03-12 1982-09-16 Anelva Corp Plasma applying working device
JPS6020919B2 (ja) * 1981-09-18 1985-05-24 住友電気工業株式会社 印刷配線板の製造方法
JPS61175919A (ja) * 1985-01-29 1986-08-07 Sharp Corp 薄膜磁気ヘツドの製造方法
JPS61190947A (ja) * 1985-02-19 1986-08-25 Toshiba Corp 微細パタ−ンの形成方法
JPS61222179A (ja) * 1985-03-27 1986-10-02 Nec Corp 半導体装置

Also Published As

Publication number Publication date
US4988403A (en) 1991-01-29
JP2597396B2 (ja) 1997-04-02
JPH02168619A (ja) 1990-06-28
CA2006175C (fr) 1993-06-15

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